Atmel SAM9X25, Manual

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30.4 Initialization Sequence
The addresses given are for example purposes only. The real address depends on implementa-
tion in the product.
30.4.1 SDR-SDRAM Initialization
The initialization sequence is generated by software. The SDR-SDRAM devices are initialized
by the following sequence:
1. Program the memory device type into the Memory Device Register (see Section 30.7.8
on page 463 ).
2. Program the features of the SDR-SDRAM device into the Timing Register (asynchro-
nous timing (trc, tras, etc.)), and into the Configuration Register (number of columns,
rows, banks, cas latency) (see
Section 30.7.3 on page 454 , Section 30.7.4 on page 457
and Section 30.7.5 on page 459 ).
3. For low-power SDRAM, temperature-compensated self refresh (TCSR), drive strength
(DS) and partial array self refresh (PASR) must be set in the Low-power Register (see
Section 30.7.7 on page 461 ).
A minimum pause of 200 μs is provided to precede any signal toggle.
4. A NOP command is issued to the SDR-SDRAM. Program NOP command into Mode
Register, the application must set Mode to 1 in the Mode Register (See
Section 30.7.1
on page 452 ). Perform a write access to any SDR-SDRAM address to acknowledge
this command. Now the clock which drives SDR-SDRAM device is enabled.
5. An all banks precharge command is issued to the SDR-SDRAM. Program all banks
precharge command into Mode Register, the application must set Mode to 2 in the
Mode Register (See
Section 30.7.1 on page 452 ). Perform a write access to any SDR-
SDRAM address to acknowledge this command.
6. Eight auto-refresh (CBR) cycles are provided. Program the auto refresh command
(CBR) into Mode Register, the application must set Mode to 4 in the Mode Register
(see
Section 30.7.1 on page 452 ).Performs a write access to any SDR-SDRAM loca-
tion eight times to acknowledge these commands.
7. A Mode Register set (MRS) cycle is issued to program the parameters of the SDR-
SDRAM devices, in particular CAS latency and burst length. The application must set
Mode to 3 in the Mode Register (see
Section 30.7.1 on page 452 ) and perform a write
access to the SDR-SDRAM to acknowledge this command. The write address must be
chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDR-SDRAM
(12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done
at the address 0x20000000.
Note: This address is for example purposes only. The real address is dependent on implementation in
the product.
8. For low-power SDR-SDRAM initialization, an Extended Mode Register set (EMRS)
cycle is issued to program the SDR-SDRAM parameters (TCSR, PASR, DS). The appli-
cation must set Mode to 5 in the Mode Register (see
Section 30.7.1 on page 452 ) and
perform a write access to the SDR-SDRAM to acknowledge this command. The write
address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0. For example,
with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank address the SDRAM
write access should be done at the address 0x20800000.
9. The application must go into Normal Mode, setting Mode to 0 in the Mode Register (see
Section 30.7.1 on page 452 ) and perform a write access at any location in the SDRAM
to acknowledge this command.