Atmel SAM9X25, Manual

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22.6 USB Device and Host Clocks
The USB Device and Host High Speed ports clocks are controlled by the UDPHS and UHPHS
bits in PMC_PCER. To save power on this peripheral when they are is not used, the user can
set these bits in PMC_PCDR. The UDPHS and UHPHS bits in PMC_PCR give the activity of
these clocks.
The PMC also provides the clocks UHP48M and UHP12M to the USB Host OHCI. The USB
Host OHCI clocks are controlled by the UHP bit in PMC_SCER. To save power on this periph-
eral when it is not used, the user can set the UHP bit in PMC_SCDR. The UHP bit in
PMC_SCSR gives the activity of this clock. The USB host OHCI requires both the 12/48 MHz
signal and the Master Clock. USBDIV field in PMC_USB register is to be programmed to 9 (divi-
sion by 10) for normal operations.
To save more power consumption the user can stop UTMI PLL, in this case USB high-speed
operations are not possible. Nevertheless, as the USB OHCI Input clock can be selected with
USBS bit (PLLA or UTMI PLL) in PMC_USB register, OHCI full-speed operation remain
possible.
The user must program the USB OHCI Input Clock and the USBDIV divider in PMC_USB regis-
ter to generate a 48 MHz and a 12 MHz signal with an accuracy of ± 0.25%.
22.7 LP-DDR/DDR2 Clock
The Power Management Controller controls the clocks of the DDR memory. It provides SysClk
DDR internal clock. That clock is used by the DDR Controller to provide DDR control, data and
DDR clock signals.
The DDR clock can be enabled and disabled with DDRCK bit respectively in PMC_SCER and
PMC_SDER registers. At reset DDR clock is disabled to save power consumption.
The Input clock is the same as Master Clock. The Output SysClk DDR Clock is 2xMCK.
In the case MDIV = ‘00’, (PCK = MCK) SysClk DDR and DDRCK clocks are not available.
If Input clock is PLLACK/PLLADIV2 the DDR Controller can drive DDR2 and LP-DDR at up to
133MHz with MDIV = ‘11’.
To save PLLA power consumption, the user can choose UPLLCK an Input clock for the system.
In this case the DDR Controller can drive LD-DDR at up to 120MHz.
22.8 Software Modem Clock
The Power Management Controller controls the clocks of the Software Modem.
SMDCK is a division of UPLL or PLLA.
22.9 Peripheral Clock Controller
The Power Management Controller controls the clocks of each embedded peripheral by means
of the Peripheral Clock Controller. The user can individually enable and disable the clock on the
peripherals and select a division factor from MCK. This is done through the Peripheral Control
Register (PMC_PCR).
In order to save power consumption, the division factor can be 1, 2, 4 or 8. PMC_PCR is a regis-
ter that features a command and acts like a mailbox. To write the division factor on a particular
peripheral, the user needs to write a WRITE command, the peripheral ID and the chosen divi-