Atmel SAM4S Series, Preliminary Data Sheet

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
30.7 Functional Description
This chapter contains the functional description of the following: SSC Functional Block, Clock
Management, Data format, Start, Transmitter, Receiver and Frame Sync.
The receiver and transmitter operate separately. However, they can work synchronously by pro-
gramming the receiver to use the transmit clock and/or to start a data transfer when transmission
starts. Alternatively, this can be done by programming the transmitter to use the receive clock
and/or to start a data transfer when reception starts. The transmitter and the receiver can be pro-
grammed to operate with the clock signals provided on either the TK or RK pins. This allows the
SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK
and RK pins is the master clock divided by 2.
Figure 30-3. SSC Functional Block Diagram
30.7.1 Clock Management
The transmitter clock can be generated by:
• An external clock received on the TK I/O pad
• The receiver clock
• The internal clock divider
NVIC
Frame Sync
Controller
Clock Output
Controller
Data
Controller
Start
Selector
Start
Selector
RF
RXEN
RC0R
TX Start
TXEN
TF
RX Start
TX Start
Interrupt Control
User
Interface
APB
MCK
Receive Clock
Controller
TX Clock
RK Input
Transmit Clock
Controller
Transmit Shift Register
Transmit Sync
Holding Register
Transmit Holding
Register
RX clock
TX clock
TK Input
RD
RF
RK
Clock Output
Controller
Frame Sync
Controller
Receive Shift Register
Receive Sync
Holding Register
Receive Holding
Register
TD
TF
TK
RX Clock
Receiver
Transmitter
Data
Controller
Clock
Divider
RX Start