Atmel SAM4S Series, Preliminary Data Sheet

Page: 444 / 1163

444
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
25.13 Slow Clock Mode
The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when
an internal signal driven by the Power Management Controller is asserted because MCK has
been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-pro-
grammed waveforms are ignored and the slow clock mode waveforms are applied. This mode is
provided so as to avoid reprogramming the User Interface with appropriate waveforms at very
slow clock rate. When activated, the slow mode is active on all chip selects.
25.13.1 Slow Clock Mode Waveforms
Figure 25-28 illustrates the read and write operations in slow clock mode. They are valid on all
chip selects. Table 25-3 indicates the value of read and write parameters in slow clock mode.
Figure 25-28. Read/Write Cycles in Slow Clock Mode
25.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode
When switching from slow clock mode to the normal mode, the current slow clock mode transfer
is completed at high clock rate, with the set of slow clock mode parameters.See
Figure 25-29 on
page 445 . The external device may not be fast enough to support such timings.
Figure 25-30 illustrates the recommended procedure to properly switch from one mode to the
other.
A[23:0]
NCS
1
MCK
NWE 1
1
NWE_CYCLE = 3
A[23:0]
MCK
NRD
NRD_CYCLE = 2
1
1
NCS
SLOW CLOCK MODE WRITE SLOW CLOCK MODE READ
Table 25-3. Read and Write Timing Parameters in Slow Clock Mode
Read Parameters Duration (cycles) Write Parameters Duration (cycles)
NRD_SETUP 1 NWE_SETUP 1
NRD_PULSE 1 NWE_PULSE 1
NCS_RD_SETUP 0 NCS_WR_SETUP 0
NCS_RD_PULSE 2 NCS_WR_PULSE 3
NRD_CYCLE 2 NWE_CYCLE 3