4.
Data Gateway Interface
The Atmel EDBG features an interface for streaming data from the target device to a computer, called the
Data Gateway Interface (DGI). This is meant as an aid in debugging and demonstration of features in the
application running on the target device.
DGI consists of multiple channels for data streaming. The available channels are listed in the sections
below. Note that not all interfaces need to be implemented on all kits, and that different kits can
implement a different subset of these interfaces. Refer to the specific kit's user guide for details.
4.1.
SPI Interface
The Serial Peripheral Interface (SPI) is connected through four digital signals; MOSI, MISO, SCK, and
CS. The SPI is set to operate in slave mode, meaning that the target device must be set to master mode.
The active low CS (Chip Select) line indicates to the SPI that it should expect data to be received and/or
sent. If the master expects to receive data from the slave, it must poll for them by initiating a transfer. All
pins are tri-stated until the interface is activated from the PC and the CS line is driven low.
It is possible to configure the mode (clock phase and data setup) of the SPI module. Valid settings are
0-3. The bit count for each transfer can also be set between 5 and 8 bits per transfer.
In normal operation, DMA will automatically buffer incoming data transfers. It is also possible to enable
timestamping to get a more accurate timing of incoming data. Note that the timestamping will add an
overhead to each data transfer, and a lower maximal throughput and a longer required inter-byte delay is
expected. For sending data to the target device DMA is always used.
4.2.
USART Interface
The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) interface is connected through
three digital signals; RX, TX, and XCK. All pins are tri-stated until the interface is activated from the PC.
Both synchronous and asynchronous modes are supported. If operated in asynchronous mode, the
correct baud rate setting must be supplied. The baud rate is flexible and is accurate up to 2Mbps.
Supported parity settings are none, even, odd, mark, and space. Stop bit can be set to 1, 1.5, and 2 stop
bits. It is possible to use a transfer size of 5-8 bits. If used in synchronous mode, a clock signal must be
supplied by the target device.
In normal operation, DMA will automatically buffer incoming data transfers. It is also possible to enable
timestamping to get a more accurate timing of incoming data. Note that the timestamping will add an
overhead to each data transfer, and a lower maximal throughput and a longer required inter-byte delay is
expected. For sending data to the target device DMA is always used.
4.3.
I
2
C Interface
The Two-Wire Interface (I
2
C) is connected to through two signals; SDA and SCL. The two-wire interface
is set to slave mode, meaning that communication must be initiated by a target device in master mode.
The interface must be enabled from the PC before communication can begin.
The slave address of the I
2
C interface can be configured, but is default set to 0x28.
Communication from the target device to I
2
C DGI is done by sending the slave address with the write bit,
followed by the data bytes. The master must poll the DGI for data by sending the slave address with the
read bit. Then the DGI will send a 1 byte length, directly followed by the data.
Atmel EDBG [USER GUIDE]
Atmel-42096C-EDBG_User Guide-10/2016
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