268
8210C–AVR–09/11
Atmel AVR XMEGA D
when the ADC channel interrupt vector is executed. The bit can also be cleared by writing a one
to the bit location.
21.15.5
RESH – Result register High
For all result registers and with any ADC result resolution, a signed number is represented in 2’s
complement form, and the msb represents the sign bit.
The RESL and RESH register pair represents the 16-bit value, ADCRESULT. Reading and writ-
ing 16-bit values require special attention. Refer to
”Accessing 16-bit Registers” on page 11
for
details.
21.15.5.1
12-bit Mode, Left Adjusted
• Bit 7:0 – RES[11:4]: Channel Result High
These are the eight msbs of the 12-bit ADC result.
21.15.5.2
12-bit Mode, Right Adjusted
• Bit 7:4 – Reserved
These bits will in practice be the extension of the sign bit, CHRES11, when the ADC works in dif-
ferential mode, and set to zero when the ADC works in signed mode.
• Bits 3:0 – RES[11:8]: Channel Result High
These are the four msbs of the 12-bit ADC result.
21.15.5.3
8-bit Mode
• Bit 7:0 – Reserved
These bits will in practice be the extension of the sign bit, CHRES7, when the ADC works in
signed mode, and set to zero when the ADC works in single-ended mode.
21.15.6
RESL – Result register Low
21.15.6.1
12-/8-bit Mode
• Bit 7:0 – RES[7:0]: Result Low
These are the eight lsbs of the ADC result.
Bit
7
6
5
4
3
2
1
0
12-bit, left.
RES[11:4]
12-bit, right
–
–
–
–
RES[11:8]
8-bit
–
–
–
–
–
–
–
–
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
12-/8-bit, right
RES[7:0]
12-bit, left.
RES[3:0]
–
–
–
–
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0