Atmel AVR XMEGA AU series, Manual

Page: 349 / 512

349
8331B–AVR–03/12
Atmel AVR XMEGA AU
• Bit 13:0 – INITDLY[13:0]: SDRAM Initialization Delay
This register is used to delay the initialisation sequence after the controller is enabled until all
voltages are stabilized and the SDRAM clock has been running long enough to take the SDRAM
chip through its initialisation sequence. The initialisation sequence includes pre-charge all banks
to their idle state issuing an auto-refresh cycle and then loading the mode register. The setting in
this register is as a number of Clk
PER2
cycles.
27.10.5 SDRAMCTRLB – SDRAM Control register B
• Bit 7:6 – MRDLY[1:0]: SDRAM Mode Register Delay
These bits select the delay between a LOAD MODE command and an ACTIVE command, in
number of Clk
PER2
cycles, according to Table 27-15 on page 349 .
• Bit 5:3 – ROWCYCDLY[2:0]: SDRAM Row Cycle Delay
These bits select the delay between a REFRESH and an ACTIVE command in number of
Clk
PER2
cycles, according to Table 27-16 on page 349 .
• Bit 2:0 – RPDLY[2:0]: SDRAM Row to Precharge Delay
RPDLY defines the delay between an Active command and a Precharge command in number of
Clk
PER2
cycles, according to Table 27-17 on page 350 .
Bit 7 6 5 4 3 2 1 0
+0x08 MRDLY[1:0] ROWCYCDLY[2:0] RPDLY[2:0] SDRAMCTRLB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 27-15. SDRAM Load Mode to Active commnad delays settings.
MRDLY[1:0] Group Configuration Description
00 0CLK Zero Clk
PER2
cycles delay
01 1CLK One Clk
PER2
cycles delay
10 2CLK Two Clk
PER2
cycles delay
11 3CLK Three Clk
PER2
cycles delay
Table 27-16. SDRAM Row cycle delay settings.
ROWCYDLY[2:0] Group Configuration Description
000 0CLK Zero Clk
PER2
cycles delay
001 1CLK One Clk
PER2
cycles delay
010 2CLK Two Clk
PER2
cycles delay
011 3CLK Three Clk
PER2
cycles delay
100 4CLK Four Clk
PER2
cycles delay
101 5CLK Five Clk
PER2
cycles delay
110 6CLK Six Clk
PER2
cycles delay
111 7CLK seven Clk
PER2
cycles delay