ATtiny10/11/12
36
•
Bit 3 - ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Analog Comparator Interrupt is activated.
When cleared (zero), the interrupt is disabled.
•
Bit 2 - Res: Reserved bit
This bit is a reserved bit in the ATtiny10/11/12 and will always read as zero.
•
Bits 1,0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator Interrupt. The different settings are
shown in Table 18.
Note:
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its interrupt enable bit in
the ACSR register. Otherwise, an interrupt can occur when the bits are changed.
Caution: Using the SBI or CBI instruction on bits other than ACI in this register will write a one back into ACI if it is read as
set, thus clearing the flag.
I/O Port B
All AVR ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction
of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instruc-
tions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if
configured as input).
Port B is a 6-bit bi-directional I/O port.
Three I/O memory address locations are allocated for Port B, one each for the Data Register – PORTB, $18, Data Direction
Register – DDRB, $17, and the Port B Input Pins – PINB, $16. The Port B Input Pins address is read only, while the Data
Register and the Data Direction Register are read/write.
Ports PB5..3 have special functions as described in the section “Pin Descriptions” on page 5. If PB5 is not configured as
external reset, it is input with no pull-up. On ATtiny12, it can also output a logical zero, acting as an open-drain output. If
PB4 and/or PB3 are not used for clock function, they are I/O pins. All I/O pins have individually selectable pull-ups.
The Port B output buffers on PB0 to PB4 can sink 20 mA and thus drive LED displays directly. On ATtiny12, PB5 can sink
12 mA. When pins PB0 to PB4 are used as inputs and are externally pulled low, they will source current (I
IL
) if the internal
pull-ups are activated.
The Port B pins with alternate functions are shown in Table 19:
Table 18. ACIS1/ACIS0 Settings
ACIS1
ACIS0
Interrupt Mode
0
0
Comparator Interrupt on Output Toggle
0
1
Reserved
1
0
Comparator Interrupt on Falling Output Edge
1
1
Comparator Interrupt on Rising Output Edge
Table 19. Port B Pins Alternate Functions
Port Pin
Alternate Functions
Device
PB0
AIN0 (Analog Comparator Positive Input)
ATtiny10/11/12
MOSI (Data Input Line for Memory Downloading)
ATtiny12
PB1
INT0 (External Interrupt0 Input)
ATtiny10/11/12
AIN1 (Analog Comparator Negative Input)
ATtiny10/11/12
MOSI (Data Output Line for Memory Downloading)
ATtiny12
