ATtiny10/11/12
26
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Bit 1 - TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical one to the flag. When the SREG
I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is
executed.
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Bit 0 - Res: Reserved bit
This bit is a reserved bit in the ATtiny10/11/12 and always reads as zero.
External Interrupt
The external interrupt is triggered by the INT0 pin. Observe that, if enabled, the interrupt will trigger even if the INT0 pin is
configured as an output. This feature provides a way of generating a software interrupt. The external interrupt can be trig-
gered by a falling or rising edge, a pin change, or a low level. This is set up as indicated in the specification for the MCU
Control Register – MCUCR. When the external interrupt is enabled and is configured as level triggered, the interrupt will
trigger as long as the pin is held low.
The external interrupt is set up as described in the specification for the MCU Control Register – MCUCR.
Pin Change Interrupt
The pin change interrupt is triggered by any change on any input or I/O pin. Change on pins PB2..0 will always cause an
interrupt. Change on pins PB5..3 will cause an interrupt if the pin is configured as input or I/O, as described in the section
“Pin Descriptions” on page 5. Observe that, if enabled, the interrupt will trigger even if the changing pin is configured as an
output. This feature provides a way of generating a software interrupt. Also observe that the pin change interrupt will trigger
even if the pin activity triggers another interrupt, for example, the external interrupt. This implies that one external event
might cause several interrupts.
The values on the pins are sampled before detecting edges. If pin change interrupt is enabled, pulses that last longer than
one CPU clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
MCU Control Register – MCUCR
The MCU Control Register contains control bits for general MCU functions.
Note:
The Pull-up Disable (PUD) bit is only available in ATtiny12.
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Bit 7 - Res: Reserved bit
This bit is a reserved bit in the ATtiny10/11/12 and always reads as zero.
•
Bit 6 - Res: Reserved bit in ATtiny10/11
This bit is a reserved bit in the ATtiny10/11 and always reads as zero.
•
Bit 6 - PUD: Pull-up Disable in ATtiny12
Setting this bit, disables all pull-ups on port B. If this bit is cleared, the pull-ups can be individually enabled as described in
section “I/O Port B” on page 36.
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Bit 5 - SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the Sleep Mode when the SLEEP instruction is executed. To avoid
the MCU entering the Sleep Mode unless it is the programmer’s purpose, it is recommended to set the Sleep Enable SE bit
just before the execution of the SLEEP instruction.
•
Bit 4 - SM: Sleep Mode
This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode.
When SM is set (one), Power-down Mode is selected as Sleep Mode. For details, refer to the paragraph “Sleep Modes”
below.
Bit
7
6
5
4
3
2
1
0
$35
-
(PUD)
SE
SM
-
-
ISC01
ISC00
MCUCR
Read/Write
R
R(/W)
R/W
R/W
R
R
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
