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8025I–AVR–02/09

ATmega48P/88P/168P/328P

masters have started transmission at the same time should not be detectable to the slaves, i.e.
the data being transferred on the bus must not be corrupted.

• Different masters may use different SCL frequencies. A scheme must be devised to

synchronize the serial clocks from all masters, in order to let the transmission proceed in a
lockstep fashion. This will facilitate the arbitration process.

The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from
all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one
from the Master with the shortest high period. The low period of the combined clock is equal to
the low period of the Master with the longest low period. Note that all masters listen to the SCL
line, effectively starting to count their SCL high and low time-out periods when the combined
SCL line goes high or low, respectively.

Figure 19-7. SCL Synchronization Between Multiple Masters

Arbitration is carried out by all masters continuously monitoring the SDA line after outputting
data. If the value read from the SDA line does not match the value the Master had output, it has
lost the arbitration. Note that a Master can only lose arbitration when it outputs a high SDA value
while another Master outputs a low value. The losing Master should immediately go to Slave
mode, checking if it is being addressed by the winning Master. The SDA line should be left high,
but losing masters are allowed to generate a clock signal until the end of the current data or
address packet. Arbitration will continue until only one Master remains, and this may take many
bits. If several masters are trying to address the same Slave, arbitration will continue into the
data packet.

TA

low

TA

high

SCL from

Master A

SCL from

Master B

SCL Bus

Line

TB

low

TB

high

Masters Start

Counting Low Period

Masters Start

Counting High Period

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218
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221
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Summary of Contents for AVR ATmega328P

Page 1: ... Temperature Measurement Programmable Serial USART Master Slave SPI Serial Interface Byte oriented 2 wire Serial Interface Philips I2 C compatible Programmable Watchdog Timer with Separate On chip Oscillator On chip Analog Comparator Interrupt and Wake up on Pin Change Special Microcontroller Features Power on Reset and Programmable Brown out Detection Internal Calibrated Oscillator External and I...

Page 2: ...AREF AVCC PB5 SCK PCINT5 PB4 MISO PCINT4 PB3 MOSI OC2A PCINT3 PB2 SS OC1B PCINT2 PB1 OC1A PCINT1 PDIP 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 32 MLF Top View PCINT19 OC2B INT1 PD3 PCINT20 XCK T0 PD4 GND VCC GND VCC PCINT6 XTAL1 TOSC1 PB6 PCINT7 XTAL2 TOSC2 PB7 PC1 ADC1 PCINT9 PC0 ADC0 PCINT8 ADC7 GND AREF ADC6 AVCC PB5 SCK PCINT5 PCINT21 OC0B T1 PD5 P...

Page 3: ...irectional I O port with internal pull up resistors selected for each bit The PC5 0 output buffers have symmetrical drive characteristics with both high sink and source capability As inputs Port C pins that are externally pulled low will source current if the pull up resistors are activated The Port C pins are tri stated when a reset condition becomes active even if the clock is not running 1 1 5 ...

Page 4: ...1 1 8 AREF AREF is the analog reference pin for the A D Converter 1 1 9 ADC7 6 TQFP and QFN MLF Package Only In the TQFP and QFN MLF package ADC7 6 serve as analog inputs to the A D converter These pins are powered from the analog supply and serve as 10 bit ADC channels 2 Overview The ATmega48P 88P 168P 328P is a low power CMOS 8 bit microcontroller based on the AVR enhanced RISC architecture By e...

Page 5: ... of In System Programmable Flash with Read While Write capabilities 256 512 512 1K bytes EEPROM 512 1K 1K 2K bytes SRAM 23 general purpose I O lines 32 general purpose work ing registers three flexible Timer Counters with compare modes internal and external interrupts a serial programmable USART a byte oriented 2 wire Serial Interface an SPI serial port a 6 channel 10 bit ADC 8 channels in TQFP an...

Page 6: ...ction will continue to run while the Application Flash section is updated providing true Read While Write operation By combining an 8 bit RISC CPU with In System Self Programmable Flash on a monolithic chip the Atmel ATmega48P 88P 168P 328P is a powerful microcontroller that pro vides a highly flexible and cost effective solution to many embedded control applications The ATmega48P 88P 168P 328P AV...

Page 7: ...ata retention failure rate is much less than 1 PPM over 20 years at 85 C or 100 years at 25 C 3 4 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device These code examples assume that the part specific header file is included before compilation Be aware that not all C compiler vendors include bit definitions in the header files and ...

Page 8: ...e level pipelining While one instruction is being executed the next instruc tion is pre fetched from the program memory This concept enables instructions to be executed in every clock cycle The program memory is In System Reprogrammable Flash memory The fast access Register File contains 32 x 8 bit general purpose working registers with a single clock cycle access time This allows single cycle Ari...

Page 9: ...before subroutines or interrupts are executed The Stack Pointer SP is read write accessible in the I O space The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture The memory spaces in the AVR architecture are all linear and regular memory maps A flexible interrupt module has its control registers in the I O space with an additional Globa...

Page 10: ... nation for the operated bit A bit from a register in the Register File can be copied into T by the BST instruction and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction Bit 5 H Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations Half Carry Is useful in BCD arithmetic See the Instruction Set Description for detailed...

Page 11: ... Working Registers Most of the instructions operating on the Register File have direct access to all registers and most of them are single cycle instructions As shown in Figure 4 2 each register is also assigned a data memory address mapping them directly into the first 32 locations of the user Data Space Although not being physically imple mented as SRAM locations this memory organization provide...

Page 12: ...ill decrease the Stack Pointer The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point above start of the SRAM see Figure 5 3 on page 18 See Table 4 1 for Stack Pointer details The AVR Stack Pointer is implemented a...

Page 13: ...arallel Instruction Fetches and Instruction Executions Figure 4 5 shows the internal timing concept for the Register File In a single clock cycle an ALU operation using two register operands is executed and the result is stored back to the destina tion register Figure 4 5 Single Cycle ALU Operation Bit 15 14 13 12 11 10 9 8 0x3E 0x5E SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D 0x5D SP7 SP6 SP5 ...

Page 14: ... interrupt routine The I bit is automatically set when a Return from Interrupt instruction RETI is executed There are basically two types of interrupts The first type is triggered by an event that sets the Interrupt Flag For these interrupts the Program Counter is vectored to the actual Interrupt Vec tor in order to execute the interrupt handling routine and hardware clears the corresponding Inter...

Page 15: ...onse time is increased by four clock cycles This increase comes in addition to the start up time from the selected sleep mode A return from an interrupt handling routine takes four clock cycles During these four clock cycles the Program Counter two bytes is popped back from the Stack the Stack Pointer is incremented by two and the I bit in SREG is set Assembly Code Example in r16 SREG store SREG v...

Page 16: ...n Program sections and the SPM instruction can be executed from the entire Flash See SELFPRGEN description in section SPMCSR Store Program Memory Control and Status Register on page 275 and page 292for more details The Flash memory has an endurance of at least 10 000 write erase cycles The ATmega48P 88P 168P 328P Program Counter PC is 11 12 13 14 bits wide thus addressing the 2 4 8 16K program mem...

Page 17: ...igure 5 1 Program Memory Map ATmega48P Figure 5 2 Program Memory Map ATmega88P ATmega168P and ATmega328P 0x0000 0x7FF Program Memory Application Flash Section 0x0000 0x0FFF 0x1FFF 0x3FFF Program Memory Application Flash Section Boot Flash Section ...

Page 18: ... memory cover Direct Indirect with Displace ment Indirect Indirect with Pre decrement and Indirect with Post increment In the Register File registers R26 to R31 feature the indirect addressing pointer registers The direct addressing reaches the entire data space The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y or Z register When using register i...

Page 19: ... are accessible in the I O space The write access time for the EEPROM is given in Table 5 2 A self timing function however lets the user software detect when the next byte can be written If the user code contains instruc tions that write the EEPROM some precautions must be taken In heavily filtered power supplies VCC is likely to rise or fall slowly on power up down This causes the device for some...

Page 20: ...he I O space I O Registers within the address range 0x00 0x1F are directly bit accessible using the SBI and CBI instructions In these registers the value of single bits can be checked by using the SBIS and SBIC instructions Refer to the instruction set section for more details When using the I O specific commands IN and OUT the I O addresses 0x00 0x3F must be used When addressing I O Registers as ...

Page 21: ... the EEPROM at the address given by EEAR 5 6 3 EECR The EEPROM Control Register Bits 7 6 Res Reserved Bits These bits are reserved bits in the ATmega48P 88P 168P 328P and will always read as zero Bits 5 4 EEPM1 and EEPM0 EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be trig gered when writing EEPE It is possible to program data in o...

Page 22: ...ure should be followed when writing the EEPROM the order of steps 3 and 4 is not essential 1 Wait until EEPE becomes zero 2 Wait until SELFPRGEN in SPMCSR becomes zero 3 Write new EEPROM address to EEAR optional 4 Write new EEPROM data to EEDR optional 5 Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR 6 Within four clock cycles after setting EEMPE write a logical one to E...

Page 23: ...on is executed The user should poll the EEPE bit before starting the read operation If a write operation is in progress it is neither possible to read the EEPROM nor to change the EEAR Register The calibrated Oscillator is used to time the EEPROM accesses Table 5 2 lists the typical pro gramming time for EEPROM access from the CPU The following code examples show one assembly and one C function fo...

Page 24: ... Write data r16 to Data Register out EEDR r16 Write logical one to EEMPE sbi EECR EEMPE Start eeprom write by setting EEPE sbi EECR EEPE ret C Code Example void EEPROM_write unsigned int uiAddress unsigned char ucData Wait for completion of previous write while EECR 1 EEPE Set up address and Data Registers EEAR uiAddress EEDR ucData Write logical one to EEMPE EECR 1 EEMPE Start eeprom write by set...

Page 25: ...ut EEARH r18 out EEARL r17 Start eeprom read by writing EERE sbi EECR EERE Read data from Data Register in r16 EEDR ret C Code Example unsigned char EEPROM_read unsigned int uiAddress Wait for completion of previous write while EECR 1 EEPE Set up address register EEAR uiAddress Start eeprom read by writing EERE EECR 1 EERE Return data from Data Register return EEDR Bit 7 6 5 4 3 2 1 0 0x2B 0x4B MS...

Page 26: ...d calculations 6 1 2 I O Clock clkI O The I O clock is used by the majority of the I O modules like Timer Counters SPI and USART The I O clock is also used by the External Interrupt module but note that some external inter rupts are detected by asynchronous logic allowing such interrupts to be detected even if the I O clock is halted Also note that start condition detection in the USI module is ca...

Page 27: ...MHz and with the fuse CKDIV8 pro grammed resulting in 1 0MHz system clock The startup time is set to maximum and time out period enabled CKSEL 0010 SUT 10 CKDIV8 0 The default setting ensures that all users can make their desired clock source setting using any available programming interface 6 2 2 Clock Startup Sequence Any clock source needs a sufficient VCC to start oscillating and a minimum num...

Page 28: ...uence for the clock includes both the time out delay and the start up time when the device starts up from reset When starting up from Power save or Power down mode VCC is assumed to be at a sufficient level and only the start up time is included 6 3 Low Power Crystal Oscillator Pins XTAL1 and XTAL2 are input and output respectively of an inverting amplifier which can be configured for use as an On...

Page 29: ...y specification of the device The CKSEL0 Fuse together with the SUT1 0 Fuses select the start up times as shown in Table 6 4 Table 6 3 Low Power Crystal Oscillator Operating Modes 3 Frequency Range 1 MHz Recommended Range for Capacitors C1 and C2 pF CKSEL3 1 0 4 0 9 100 2 0 9 3 0 12 22 101 3 0 8 0 12 22 110 8 0 16 0 12 22 111 Table 6 4 Start up Times for the Low Power Crystal Oscillator Clock Sele...

Page 30: ...nly operate for VCC 2 7 5 5 volts C1 and C2 should always be equal for both crystals and resonators The optimal value of the capacitors depends on the crystal or resonator in use the amount of stray capacitance and the electromagnetic noise of the environment Some initial guidelines for choosing capacitors for use with crystals are given in Table 6 6 on page 31 For ceramic resonators the capacitor...

Page 31: ... start up is not important for the application Table 6 6 Start up Times for the Full Swing Crystal Oscillator Clock Selection Oscillator Source Power Conditions Start up Time from Power down and Power save Additional Delay from Reset VCC 5 0V CKSEL0 SUT1 0 Ceramic resonator fast rising power 258 CK 14CK 4 1 ms 1 0 00 Ceramic resonator slowly rising power 258 CK 14CK 65 ms 1 0 01 Ceramic resonator ...

Page 32: ...ce for a 32 768 kHz crystal specified by the crystal vendor and CS is the total stray capacitance for one TOSC pin Crystals specifying load capacitance CL higher than 6 pF require external capacitors applied as described in Figure 6 2 on page 29 The Low frequency Crystal Oscillator must be selected by setting the CKSEL Fuses to 0110 or 0111 as shown in Table 6 9 Start up times are determined by th...

Page 33: ...he Watchdog Timer and for the Reset Time out For more information on the pre programmed cali bration value see the section Calibration Byte on page 299 Notes 1 This is the recommended CKSEL settings for the different frequency ranges 2 If 8 MHz frequency exceeds the specification of the device depends on VCC the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8 When this...

Page 34: ... the device on an external clock the CKSEL Fuses must be programmed to 0000 see Table 6 14 Figure 6 4 External Clock Drive Configuration When this clock source is selected start up times are determined by the SUT Fuses as shown in Table 6 15 Table 6 12 128 kHz Internal Oscillator Operating Modes Nominal Frequency 1 CKSEL3 0 128 kHz 0011 Table 6 13 Start up Times for the 128 kHz Internal Oscillator...

Page 35: ...hare the Timer Counter Oscillator Pins TOSC1 and TOSC2 with XTAL1 and XTAL2 When using the Timer Counter Oscillator the system clock needs to be four times the oscillator frequency Due to this and the pin sharing the Timer Counter Oscillator can only be used when the Calibrated Internal RC Oscillator is selected as system clock source Applying an external clock source to TOSC1 can be done if EXTCL...

Page 36: ...ly predicted From the time the CLKPS values are written it takes between T1 T2 and T1 2 T2 before the new clock frequency is active In this interval 2 active clock edges are produced Here T1 is the pre vious clock period and T2 is the period corresponding to the new prescaler setting To avoid unintentional changes of clock frequency a special write procedure must befollowed to change the CLKPS bit...

Page 37: ...han OSCCAL 0x80 The CAL6 0 bits are used to tune the frequency within the selected range A setting of 0x00 gives the lowest frequency in that range and a setting of 0x7F gives the highest frequency in the range 6 12 2 CLKPR Clock Prescale Register Bit 7 CLKPCE Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits The CLKPCE bit is only updated...

Page 38: ...alue can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions The device is shipped with the CKDIV8 Fuse programmed Table 6 16 Clock Prescaler Select CLKPS3 CLKPS2 CLKPS1 CLKPS...

Page 39: ...e written to logic one and a SLEEP instruction must be executed The SM2 SM1 and SM0 bits in the SMCR Register select which sleep mode Idle ADC Noise Reduction Power down Power save Standby or Extended Standby will be activated by the SLEEP instruction See Table 7 2 on page 44 for a summary If an enabled interrupt occurs while the MCU is in a sleep mode the MCU wakes up The MCU is then halted for f...

Page 40: ...d the interrupt system to continue operating This sleep mode basically halts clkCPU and clkFLASH while allowing the other clocks to run Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts If wake up from the Analog Comparator interrupt is not required the Analog Comparator can be powered dow...

Page 41: ...e mode This mode is identical to Power down with one exception If Timer Counter2 is enabled it will keep running during sleep The device can wake up from either Timer Overflow or Output Compare event from Timer Counter2 if the corresponding Timer Counter2 interrupt enable bits are set in TIMSK2 and the Global Interrupt Enable bit in SREG is set If Timer Counter2 is not running Power down mode is r...

Page 42: ...sion will be an extended conversion Refer to Analog to Digital Converter on page 250 for details on ADC operation 7 10 2 Analog Comparator When entering Idle mode the Analog Comparator should be disabled if not used When entering ADC Noise Reduction mode the Analog Comparator should be disabled In other sleep modes the Analog Comparator is automatically disabled However if the Analog Comparator is...

Page 43: ...input logic is needed for detecting wake up conditions and it will then be enabled Refer to the section Digital Input Enable and Sleep Modes on page 79 for details on which pins are enabled If the input buffer is enabled and the input signal is left floating or have an analog signal level close to VCC 2 the input buffer will use excessive power For analog input pins the digital input buffer should...

Page 44: ... purpose it is recommended to write the Sleep Enable SE bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up 7 11 2 MCUCR MCU Control Register Bit 6 BODS BOD Sleep The BODS bit must be written to logic one in order to turn off BOD during sleep see Table 7 1 on page 39 Writing to the BODS bit is controlled by a timed sequence and an enable bit BO...

Page 45: ...he Timer Counter0 module When the Timer Counter0 is enabled operation will continue like before the shutdown Bit 4 Res Reserved bit This bit is reserved in ATmega48P 88P 168P 328P and will always read as zero Bit 3 PRTIM1 Power Reduction Timer Counter1 Writing a logic one to this bit shuts down the Timer Counter1 module When the Timer Counter1 is enabled operation will continue like before the shu...

Page 46: ...arameters of the reset circuitry The I O ports of the AVR are immediately reset to their initial state when a reset source goes active This does not require any clock source to be running After all reset sources have gone inactive a delay counter is invoked stretching the internal reset This allows the power to reach a stable level before normal operation starts The time out period of the delay co...

Page 47: ...OR circuit ensures that the device is reset from Power on Reaching the Power on Reset threshold voltage invokes the delay counter which determines how long the device is kept in RESET after VCC rise The RESET signal is activated again without any delay when VCC decreases below the detection level Figure 8 2 MCU Start up RESET Tied to VCC MCU Status Register MCUSR Brown out Reset Circuit BODLEVEL 2...

Page 48: ...68P 328P has an On chip Brown out Detection BOD circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level The trigger level for the BOD can be selected by the BODLEVEL Fuses The trigger level has a hysteresis to ensure spike free Brown out Detection The hysteresis on the detection level should be interpreted as VBOT VBOT VHYST 2 and VBOT VBOT VHYST 2 When the B...

Page 49: ...o the Analog Comparator or the ADC 8 7 1 Voltage Reference Enable Signals and Start up Time The voltage reference has a start up time that may influence the way it should be used The start up time is given in System and Reset Characteristics on page 320 To save power the reference is not always turned on The reference is on during the following situations 1 When the BOD is enabled by programming t...

Page 50: ...rt the counter an interrupt or system reset will be issued Figure 8 7 Watchdog Timer In Interrupt mode the WDT gives an interrupt when the timer expires This interrupt can be used to wake the device from sleep modes and also as a general system timer One example is to limit the maximum time allowed for certain operations giving an interrupt when the operation has run longer than expected In System...

Page 51: ...hange enable bit WDCE and WDE A logic one must be written to WDE regardless of the previous value of the WDE bit 2 Within the next four clock cycles write the WDE and Watchdog prescaler bits WDP as desired but with the WDCE bit cleared This must be done in one operation The following code example shows one assembly and one C function for turning off the Watch dog Timer The example assumes that int...

Page 52: ...lisation routine even if the Watchdog is not in use Assembly Code Example 1 WDT_off Turn off global interrupt cli Reset Watchdog Timer wdr Clear WDRF in MCUSR in r16 MCUSR andi r16 0xff 0 WDRF out MCUSR r16 Write logical one to WDCE and WDE Keep old prescaler setting to prevent unintentional time out lds r16 WDTCSR ori r16 1 WDCE 1 WDE sts WDTCSR r16 Turn off WDT ldi r16 0 WDE sts WDTCSR r16 Turn ...

Page 53: ...ple 1 WDT_Prescaler_Change Turn off global interrupt cli Reset Watchdog Timer wdr Start timed sequence lds r16 WDTCSR ori r16 1 WDCE 1 WDE sts WDTCSR r16 Got four cycles to set the new values from here Set new prescaler time out value 64K cycles 0 5 s ldi r16 1 WDE 1 WDP2 1 WDP0 sts WDTCSR r16 Finished setting new values used 2 cycles Turn on global interrupt sei ret C Code Example 1 void WDT_Pres...

Page 54: ...occurs the source of the reset can be found by examining the Reset Flags 8 9 2 WDTCSR Watchdog Timer Control Register Bit 7 WDIF Watchdog Interrupt Flag This bit is set when a time out occurs in the Watchdog Timer and the Watchdog Timer is config ured for interrupt WDIF is cleared by hardware when executing the corresponding interrupt handling vector Alternatively WDIF is cleared by writing a logi...

Page 55: ...in MCUSR This means that WDE is always set when WDRF is set To clear WDE WDRF must be cleared first This feature ensures multiple resets during con ditions causing failure and a safe start up after the failure Bit 5 2 0 WDP3 0 Watchdog Timer Prescaler 3 2 1 and 0 The WDP3 0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run ning The different prescaling values and their co...

Page 56: ...0 512K 524288 cycles 4 0 s 1 0 0 1 1024K 1048576 cycles 8 0 s 1 0 1 0 Reserved 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Table 8 2 Watchdog Timer Prescale Select Continued WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time out at VCC 5 0V ...

Page 57: ...tion 1 0x000 RESET External Pin Power on Reset Brown out Reset and Watchdog System Reset 2 0x001 INT0 External Interrupt Request 0 3 0x002 INT1 External Interrupt Request 1 4 0x003 PCINT0 Pin Change Interrupt Request 0 5 0x004 PCINT1 Pin Change Interrupt Request 1 6 0x005 PCINT2 Pin Change Interrupt Request 2 7 0x006 WDT Watchdog Time out Interrupt 8 0x007 TIMER2 COMPA Timer Counter2 Compare Match...

Page 58: ...r0 Compare A Handler 0x00F rjmp TIM0_COMPB Timer0 Compare B Handler 0x010 rjmp TIM0_OVF Timer0 Overflow Handler 0x011 rjmp SPI_STC SPI Transfer Complete Handler 0x012 rjmp USART_RXC USART RX Complete Handler 0x013 rjmp USART_UDRE USART UDR Empty Handler 0x014 rjmp USART_TXC USART TX Complete Handler 0x015 rjmp ADC ADC Conversion Complete Handler 0x016 rjmp EE_RDY EEPROM Ready Handler 0x017 rjmp AN...

Page 59: ...errupt Definition 1 0x000 1 RESET External Pin Power on Reset Brown out Reset and Watchdog System Reset 2 0x001 INT0 External Interrupt Request 0 3 0x002 INT1 External Interrupt Request 1 4 0x003 PCINT0 Pin Change Interrupt Request 0 5 0x004 PCINT1 Pin Change Interrupt Request 1 6 0x005 PCINT2 Pin Change Interrupt Request 2 7 0x006 WDT Watchdog Time out Interrupt 8 0x007 TIMER2 COMPA Timer Counter...

Page 60: ...TIM1_OVF Timer1 Overflow Handler 0x00E rjmp TIM0_COMPA Timer0 Compare A Handler 0x00F rjmp TIM0_COMPB Timer0 Compare B Handler 0x010 rjmp TIM0_OVF Timer0 Overflow Handler 0x011 rjmp SPI_STC SPI Transfer Complete Handler 0x012 rjmp USART_RXC USART RX Complete Handler 0x013 rjmp USART_UDRE USART UDR Empty Handler 0x014 rjmp USART_TXC USART TX Complete Handler 0x015 rjmp ADC ADC Conversion Complete H...

Page 61: ...l and general program setup for the Reset and Interrupt Vector Addresses in ATmega88P is Address Labels Code Comments org 0x001 0x001 rjmp EXT_INT0 IRQ0 Handler 0x002 rjmp EXT_INT1 IRQ1 Handler 0x019 rjmp SPM_RDY Store Program Memory Ready Handler org 0xC00 0xC00 RESET ldi r16 high RAMEND Main program start 0xC01 out SPH r16 Set Stack Pointer to top of RAM 0xC02 ldi r16 low RAMEND 0xC03 out SPL r1...

Page 62: ...0 3 0x0004 INT1 External Interrupt Request 1 4 0x0006 PCINT0 Pin Change Interrupt Request 0 5 0x0008 PCINT1 Pin Change Interrupt Request 1 6 0x000A PCINT2 Pin Change Interrupt Request 2 7 0x000C WDT Watchdog Time out Interrupt 8 0x000E TIMER2 COMPA Timer Counter2 Compare Match A 9 0x0010 TIMER2 COMPB Timer Counter2 Compare Match B 10 0x0012 TIMER2 OVF Timer Counter2 Overflow 11 0x0014 TIMER1 CAPT ...

Page 63: ...MPA Timer2 Compare A Handler 0x0010 jmp TIM2_COMPB Timer2 Compare B Handler 0x0012 jmp TIM2_OVF Timer2 Overflow Handler 0x0014 jmp TIM1_CAPT Timer1 Capture Handler 0x0016 jmp TIM1_COMPA Timer1 Compare A Handler 0x0018 jmp TIM1_COMPB Timer1 Compare B Handler 0x001A jmp TIM1_OVF Timer1 Overflow Handler 0x001C jmp TIM0_COMPA Timer0 Compare A Handler 0x001E jmp TIM0_COMPB Timer0 Compare B Handler 0x00...

Page 64: ...Q0 Handler 0x1C04 jmp EXT_INT1 IRQ1 Handler 0x1C32 jmp SPM_RDY Store Program Memory Ready Handler When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega168P is Address Labels Code Comments org 0x0002 0x0002 jmp EXT_INT0 IRQ0 Handler 0x0004 jmp EXT_INT1 IRQ1 Handler 0x0032 jmp SP...

Page 65: ... 3 0x0004 INT1 External Interrupt Request 1 4 0x0006 PCINT0 Pin Change Interrupt Request 0 5 0x0008 PCINT1 Pin Change Interrupt Request 1 6 0x000A PCINT2 Pin Change Interrupt Request 2 7 0x000C WDT Watchdog Time out Interrupt 8 0x000E TIMER2 COMPA Timer Counter2 Compare Match A 9 0x0010 TIMER2 COMPB Timer Counter2 Compare Match B 10 0x0012 TIMER2 OVF Timer Counter2 Overflow 11 0x0014 TIMER1 CAPT T...

Page 66: ...al and general program setup for the Reset and Interrupt Vector Addresses in ATmega328P is Address Labels Code Comments 0x0000 jmp RESET Reset Handler 0x0002 jmp EXT_INT0 IRQ0 Handler 0x0004 jmp EXT_INT1 IRQ1 Handler 0x0006 jmp PCINT0 PCINT0 Handler 0x0008 jmp PCINT1 PCINT1 Handler 0x000A jmp PCINT2 PCINT2 Handler 0x000C jmp WDT Watchdog Timer Handler 0x000E jmp TIM2_COMPA Timer2 Compare A Handler...

Page 67: ...ts 0x0038 instr xxx When the BOOTRST Fuse is unprogrammed the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega328P is Address Labels Code Comments 0x0000 RESET ldi r16 high RAMEND Main program start 0x0001 out SPH r16 Set Stack Pointer ...

Page 68: ...D 0x3C36 out SPL r16 0x3C37 sei Enable interrupts 0x3C38 instr xxx 9 5 Register Description 9 5 1 Moving Interrupts Between Application and Boot Space ATmega88P ATmega168P and ATmega328P The MCU Control Register controls the placement of the Interrupt Vector table 9 5 2 MCUCR MCU Control Register Bit 1 IVSEL Interrupt Vector Select When the IVSEL bit is cleared zero the Interrupt Vectors are place...

Page 69: ...d Boot Lock bit BLB12 is programed interrupts are disabled while executing from the Boot Loader section Refer to the section Boot Loader Support Read While Write Self Programming ATmega88P ATmega168P and ATmega328P on page 277 for details on Boot Lock bits This bit is not available in ATmega48P Bit 0 IVCE Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of ...

Page 70: ...terrupts are enabled and are configured as level triggered the inter rupts will trigger as long as the pin is held low Note that recognition of falling or rising edge interrupts on INT0 or INT1 requires the presence of an I O clock described in Clock Systems and their Distribution on page 26 Low level interrupt on INT0 and INT1 is detected asynchro nously This implies that this interrupt can be us...

Page 71: ...ated by the external pin INT0 if the SREG I flag and the corre sponding interrupt mask are set The level and edges on the external INT0 pin that activate the interrupt are defined in Table 10 2 The value on the INT0 pin is sampled before detecting edges If edge or toggle interrupt is selected pulses that last longer than one clock period will generate an interrupt Shorter pulses are not guaranteed...

Page 72: ...t even if INT0 is configured as an output The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector 10 2 3 EIFR External Interrupt Flag Register Bit 7 2 Res Reserved Bits These bits are unused bits in the ATmega48P 88P 168P 328P and will always read as zero Bit 1 INTF1 External Interrupt Flag 1 When an edge or logic change on the INT1 pin triggers an in...

Page 73: ... any enabled PCINT7 0 pin will cause an interrupt The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Inter rupt Vector PCINT7 0 pins are enabled individually by the PCMSK0 Register 10 2 5 PCIFR Pin Change Interrupt Flag Register Bit 7 3 Res Reserved Bits These bits are unused bits in the ATmega48P 88P 168P 328P and will always read as zero Bit 2 PCIF2 Pin Change ...

Page 74: ...ange Enable Mask 14 8 Each PCINT14 8 bit selects whether pin change interrupt is enabled on the corresponding I O pin If PCINT14 8 is set and the PCIE1 bit in PCICR is set pin change interrupt is enabled on the corresponding I O pin If PCINT14 8 is cleared pin change interrupt on the corresponding I O pin is disabled 10 2 8 PCMSK0 Pin Change Mask Register 0 Bit 7 0 PCINT7 0 Pin Change Enable Mask ...

Page 75: ...d a lower case n represents the bit number However when using the register or bit defines in a program the precise form must be used For example PORTB3 for bit no 3 in Port B here documented generally as PORTxn The physical I O Regis ters and bit locations are listed in Register Description on page 92 Three I O memory address locations are allocated for each port one each for the Data Register POR...

Page 76: ...x I O address the PORTxn bits at the PORTx I O address and the PINxn bits at the PINx I O address The DDxn bit in the DDRx Register selects the direction of this pin If DDxn is written logic one Pxn is configured as an output pin If DDxn is written logic zero Pxn is configured as an input pin If PORTxn is written logic one when the pin is configured as an input pin the pull up resistor is activate...

Page 77: ...able all pull ups in all ports Switching between input with pull up and output low generates the same problem The user must use either the tri state DDxn PORTxn 0b00 or the output high state DDxn PORTxn 0b11 as an intermediate step Table 11 1 summarizes the control signals for the pin value 11 2 4 Reading the Pin Value Independent of the setting of Data Direction bit DDxn the port pin can be read ...

Page 78: ... reading back a software assigned pin value a nop instruction must be inserted as indi cated in Figure 11 4 The out instruction sets the SYNC LATCH signal at the positive edge of the clock In this case the delay tpd through the synchronizer is 1 system clock period Figure 11 4 Synchronization when Reading a Software Assigned Pin Value The following code example shows how to set port B pins 0 and 1...

Page 79: ...ibed in Alternate Port Functions on page 80 If a logic high level one is present on an asynchronous external interrupt pin configured as Interrupt on Rising Edge Falling Edge or Any Logic Change on Pin while the external interrupt is not enabled the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode as the clamping in these sleep mode produces the r...

Page 80: ...rves as a generic description applicable to all port pins in the AVR microcontroller family Figure 11 5 Alternate Port Functions 1 Note 1 WRx WPx WDx RRx RPx and RDx are common to all pins within the same port clkI O SLEEP and PUD are common to all ports All other signals are unique for each pin clk RPx RRx WRx RDx WDx PUD SYNCHRONIZER WDx WRITE DDRx WRx WRITE PORTx RRx READ PORTx REGISTER RPx REA...

Page 81: ...put Driver is enabled disabled when DDOV is set cleared regardless of the setting of the DDxn Register bit PVOE Port Value Override Enable If this signal is set and the Output Driver is enabled the port value is controlled by the PVOV signal If PVOE is cleared and the Output Driver is enabled the port Value is controlled by the PORTxn Register bit PVOV Port Value Override Value If PVOE is set the ...

Page 82: ...NB7 will all read 0 XTAL1 TOSC1 PCINT6 Port B Bit 6 XTAL1 Chip clock Oscillator pin 1 Used for all chip clock sources except internal calibrated RC Oscillator When used as a clock pin the pin can not be used as an I O pin TOSC1 Timer Oscillator pin 1 Used only if internal calibrated RC Oscillator is selected as chip clock source and the asynchronous timer is enabled by the correct setting in ASSR ...

Page 83: ...PI Master Data output Slave Data input for SPI channel When the SPI is enabled as a Slave this pin is configured as an input regardless of the setting of DDB3 When the SPI is enabled as a Master the data direction of this pin is controlled by DDB3 When the pin is forced by the SPI to be an input the pull up can still be controlled by the PORTB3 bit OC2 Output Compare Match Output The PB3 pin can s...

Page 84: ...o the overriding signals shown in Figure 11 5 on page 80 SPI MSTR INPUT and SPI SLAVE OUTPUT consti tute the MISO signal while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT Notes 1 INTRC means that one of the internal RC Oscillators are selected by the CKSEL fuses EXTCK means that external clock is selected by the CKSEL fuses Table 11 4 Overriding Signals for Alternate Functions in PB7 ...

Page 85: ...NT2 PCIE0 PCINT1 PCIE0 PCINT0 PCIE0 DIEOV 1 1 1 1 DI PCINT3 INPUT SPI SLAVE INPUT PCINT2 INPUT SPI SS PCINT1 INPUT PCINT0 INPUT ICP1 INPUT AIO Table 11 6 Port C Pins Alternate Functions Port Pin Alternate Function PC6 RESET Reset pin PCINT14 Pin Change Interrupt 14 PC5 ADC5 ADC Input Channel 5 SCL 2 wire Serial Bus Clock Line PCINT13 Pin Change Interrupt 13 PC4 ADC4 ADC Input Channel 4 SDA 2 wire ...

Page 86: ... can also be used as ADC input Channel 5 Note that ADC input channel 5 uses digital power PCINT13 Pin Change Interrupt source 13 The PC5 pin can serve as an external interrupt source SDA ADC4 PCINT12 Port C Bit 4 SDA 2 wire Serial Interface Data When the TWEN bit in TWCR is set one to enable the 2 wire Serial Interface pin PC4 is disconnected from the port and becomes the Serial Data I O pin for t...

Page 87: ...re 11 5 on page 80 Note 1 When enabled the 2 wire Serial Interface enables slew rate controls on the output pins PC4 and PC5 This is not shown in the figure In addition spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module Table 11 7 Overriding Signals for Alternate Functions in PC6 PC4 1 Signal Name PC6 RESET PCINT14 PC5 SCL ADC5 PCIN...

Page 88: ...UT Table 11 9 Port D Pins Alternate Functions Port Pin Alternate Function PD7 AIN1 Analog Comparator Negative Input PCINT23 Pin Change Interrupt 23 PD6 AIN0 Analog Comparator Positive Input OC0A Timer Counter0 Output Compare Match A Output PCINT22 Pin Change Interrupt 22 PD5 T1 Timer Counter 1 External Counter Input OC0B Timer Counter0 Output Compare Match B Output PCINT21 Pin Change Interrupt 21 ...

Page 89: ...upt source 22 The PD6 pin can serve as an external interrupt source T1 OC0B PCINT21 Port D Bit 5 T1 Timer Counter1 counter source OC0B Output Compare Match output The PD5 pin can serve as an external output for the Timer Counter0 Compare Match B The PD5 pin has to be configured as an output DDD5 set one to serve this function The OC0B pin is also the output pin for the PWM mode timer function PCIN...

Page 90: ... is configured as an input regardless of the value of DDD0 When the USART forces this pin to be an input the pull up can still be controlled by the PORTD0 bit PCINT16 Pin Change Interrupt source 16 The PD0 pin can serve as an external interrupt source Table 11 10 and Table 11 11 relate the alternate functions of Port D to the overriding signals shown in Figure 11 5 on page 80 Table 11 10 Overridin...

Page 91: ...INT0 PCINT18 PD1 TXD PCINT17 PD0 RXD PCINT16 PUOE 0 0 TXEN RXEN PUO 0 0 0 PORTD0 PUD DDOE 0 0 TXEN RXEN DDOV 0 0 1 0 PVOE OC2B ENABLE 0 TXEN 0 PVOV OC2B 0 TXD 0 DIEOE INT1 ENABLE PCINT19 PCIE2 INT0 ENABLE PCINT18 PCIE1 PCINT17 PCIE2 PCINT16 PCIE2 DIEOV 1 1 1 1 DI PCINT19 INPUT INT1 INPUT PCINT18 INPUT INT0 INPUT PCINT17 INPUT PCINT16 INPUT RXD AIO ...

Page 92: ...e 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x05 0x25 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x04 0x24 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x03 0x23 PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PIN...

Page 93: ...D5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x0A 0x2A DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x09 0x29 PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND Read Write R R R R R R R R Initial Value N A N A N A...

Page 94: ... Counter module with two independent Output Compare Units and with PWM support It allows accurate program execution timing event man agement and wave generation A simplified block diagram of the 8 bit Timer Counter is shown in Figure 12 1 For the actual placement of I O pins refer to Pinout ATmega48P 88P 168P 328P on page 2 CPU accessible I O Registers including I O bits and I O pins are shown in ...

Page 95: ...t abbreviated to Int Req in the figure signals are all visible in the Timer Interrupt Flag Register TIFR0 All interrupts are individually masked with the Timer Inter rupt Mask Register TIMSK0 TIFR0 and TIMSK0 are not shown in the figure Clock Select Timer Counter DATA BUS OCRnA OCRnB TCNTn Waveform Generation Waveform Generation OCnA OCnB Fixed TOP Value Control Logic 0 TOP BOTTOM Count Clear Dire...

Page 96: ... in the Timer Counter Control Register TCCR0B For details on clock sources and pres caler see Timer Counter0 and Timer Counter1 Prescalers on page 141 12 4 Counter Unit The main part of the 8 bit Timer Counter is the programmable bi directional counter unit Figure 12 2 shows a block diagram of the counter and its surroundings Figure 12 2 Counter Unit Block Diagram Signal description internal signa...

Page 97: ...enerates an Output Compare interrupt The Output Compare Flag is automatically cleared when the interrupt is exe cuted Alternatively the flag can be cleared by software by writing a logical one to its I O bit location The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM02 0 bits and Compare Output mode COM0x1 0 bits The max and bottom signals...

Page 98: ...ependently of whether the Timer Counter is running or not If the value written to TCNT0 equals the OCR0x value the compare match will be missed resulting in incorrect waveform generation Similarly do not write the TCNT0 value equal to BOTTOM when the counter is downcounting The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output The easiest w...

Page 99: ...ister is to be performed on the next compare match For compare output actions in the non PWM modes refer to Table 12 2 on page 106 For fast PWM mode refer to Table 12 3 on page 106 and for phase correct PWM refer to Table 12 4 on page 107 A change of the COM0x1 0 bits state will have effect at the first compare match after the bits are written For non PWM modes the action can be forced to have imm...

Page 100: ...TCNT0 matches the OCR0A The OCR0A defines the top value for the counter hence also its resolution This mode allows greater control of the compare match output frequency It also simplifies the operation of counting external events The timing diagram for the CTC mode is shown in Figure 12 5 The counter value TCNT0 increases until a compare match occurs between TCNT0 and OCR0A and then counter TCNT0 ...

Page 101: ...ration the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual slope operation This high frequency makes the fast PWM mode well suited for power regulation rectification and DAC applications High frequency allows physically small sized external components coils capacitors and therefore reduces total system cost In fast PWM mode the counter is i...

Page 102: ... compare match COM0x1 0 1 The waveform generated will have a maximum frequency of fOC0 fclk_I O 2 when OCR0A is set to zero This feature is similar to the OC0A toggle in CTC mode except the double buffer feature of the Out put Compare unit is enabled in the fast PWM mode 12 7 4 Phase Correct PWM Mode The phase correct PWM mode WGM02 0 1 or 5 provides a high resolution phase correct PWM waveform ge...

Page 103: ...e OC0x Register at compare match between OCR0x and TCNT0 when the counter decrements The PWM frequency for the output when using phase correct PWM can be calculated by the following equation The N variable represents the prescale factor 1 8 64 256 or 1024 The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode If the OCR...

Page 104: ...llowing figures The figures include information on when interrupt flags are set Figure 12 8 contains timing data for basic Timer Counter operation The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode Figure 12 8 Timer Counter Timing Diagram no Prescaling Figure 12 9 shows the same timing data but with the prescaler enabled Figure 12 9 Timer Coun...

Page 105: ...e setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is TOP Figure 12 11 Timer Counter Timing Diagram Clear Timer on Compare Match mode with Pres caler fclk_I O 8 OCFnx OCRnx TCNTn OCRnx Value OCRnx 1 OCRnx OCRnx 1 OCRnx 2 clkI O clkTn clkI O 8 OCFnx OCRnx TCNTn CTC TOP TOP 1 TOP BOTTOM BOTTOM 1 clkI O clkTn clkI O 8 ...

Page 106: ...ity when the WGM01 0 bits are set to fast PWM mode Note 1 A special case occurs when OCR0A equals TOP and COM0A1 is set In this case the Com pare Match is ignored but the set or clear is done at BOTTOM See Fast PWM Mode on page 101 for more details Bit 7 6 5 4 3 2 1 0 0x24 0x44 COM0A1 COM0A0 COM0B1 COM0B0 WGM01 WGM00 TCCR0A Read Write R W R W R W R W R R R W R W Initial Value 0 0 0 0 0 0 0 0 Table...

Page 107: ...s the COM0B1 0 bit functionality when the WGM02 0 bits are set to fast PWM mode Note 1 A special case occurs when OCR0B equals TOP and COM0B1 is set In this case the Com pare Match is ignored but the set or clear is done at TOP See Fast PWM Mode on page 101 for more details Table 12 4 Compare Output Mode Phase Correct PWM Mode 1 COM0A1 COM0A0 Description 0 0 Normal port operation OC0A disconnected...

Page 108: ...ation supported by the Timer Counter unit are Normal mode counter Clear Timer on Compare Match CTC mode and two types of Pulse Width Modulation PWM modes see Modes of Operation on page 99 Notes 1 MAX 0xFF 2 BOTTOM 0x00 Table 12 7 Compare Output Mode Phase Correct PWM Mode 1 COM0B1 COM0B0 Description 0 0 Normal port operation OC0B disconnected 0 1 Reserved 1 0 Clear OC0B on Compare Match when up co...

Page 109: ...on PWM mode However for ensuring compatibility with future devices this bit must be set to zero when TCCR0B is written when operating in PWM mode When writing a logical one to the FOC0B bit an immediate Compare Match is forced on the Waveform Generation unit The OC0B output is changed according to its COM0B1 0 bits setting Note that the FOC0B bit is implemented as a strobe Therefore it is the valu...

Page 110: ...r to generate a waveform output on the OC0A pin 12 9 5 OCR0B Output Compare Register B The Output Compare Register B contains an 8 bit value that is continuously compared with the counter value TCNT0 A match can be used to generate an Output Compare interrupt or to generate a waveform output on the OC0B pin Table 12 9 Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source Ti...

Page 111: ...0 bit is set in the Timer Counter 0 Inter rupt Flag Register TIFR0 12 9 7 TIFR0 Timer Counter 0 Interrupt Flag Register Bits 7 3 Res Reserved Bits These bits are reserved bits in the ATmega48P 88P 168P 328P and will always read as zero Bit 2 OCF0B Timer Counter 0 Output Compare B Match Flag The OCF0B bit is set when a Compare Match occurs between the Timer Counter and the data in OCR0B Output Comp...

Page 112: ...ting the corresponding interrupt handling vector Alternatively TOV0 is cleared by writing a logic one to the flag When the SREG I bit TOIE0 Timer Counter0 Overflow Interrupt Enable and TOV0 are set the Timer Counter0 Overflow interrupt is executed The setting of this flag is dependent of the WGM02 0 bit setting Refer to Table 12 8 Waveform Generation Mode Bit Description on page 108 ...

Page 113: ...ng measurement Most register and bit references in this section are written in general form A lower case n replaces the Timer Counter number and a lower case x replaces the Output Compare unit channel However when using the register or bit defines in a program the precise form must be used i e TCNT1 for accessing Timer Counter1 counter value and so on A simplified block diagram of the 16 bit Timer...

Page 114: ...K1 TIFR1 and TIMSK1 are not shown in the figure The Timer Counter can be clocked internally via the prescaler or by an external clock source on the T1 pin The Clock Select logic block controls which clock source and edge the Timer Counter uses to increment or decrement its value The Timer Counter is inactive when no clock source is selected The output from the Clock Select logic is referred to as ...

Page 115: ...er for temporary storing of the high byte of the 16 bit access The same temporary register is shared between all 16 bit registers within each 16 bit timer Accessing the low byte triggers the 16 bit read or write operation When the low byte of a 16 bit register is written by the CPU the high byte stored in the temporary register and the low byte written are both copied into the 16 bit register in t...

Page 116: ...rrupt code updates the temporary register by accessing the same or any other of the 16 bit Timer Regis ters then the result of the access outside the interrupt will be corrupted Therefore when both the main code and the interrupt code update the temporary register the main code must disable the interrupts during the 16 bit access The following code examples show how to do an atomic read of the TCN...

Page 117: ...ng code examples show how to do an atomic write of the TCNT1 Register contents Writing any of the OCR1A B or ICR1 Registers can be done by using the same principle Assembly Code Example 1 TIM16_ReadTCNT1 Save global interrupt flag in r18 SREG Disable interrupts cli Read TCNT1 into r17 r16 in r16 TCNT1L in r17 TCNT1H Restore global interrupt flag out SREG r18 ret C Code Example 1 unsigned int TIM16...

Page 118: ... operation described previously also applies in this case 13 4 Timer Counter Clock Sources The Timer Counter can be clocked by an internal or an external clock source The clock source is selected by the Clock Select logic which is controlled by the Clock Select CS12 0 bits located in the Timer Counter control Register B TCCR1B For details on clock sources and prescaler see Timer Counter0 and Timer...

Page 119: ...ter value within one clock cycle via the 8 bit data bus It is important to notice that there are special cases of writing to the TCNT1 Register when the counter is counting that will give unpredictable results The special cases are described in the sections where they are of importance Depending on the mode of operation used the counter is cleared incremented or decremented at each timer clock clk...

Page 120: ... on the Analog Comparator output ACO and this change confirms to the setting of the edge detector a capture will be triggered When a capture is triggered the 16 bit value of the counter TCNT1 is written to the Input Capture Register ICR1 The Input Capture Flag ICF1 is set at the same system clock as the TCNT1 value is copied into ICR1 Register If enabled ICIE1 1 the Input Capture Flag generates an...

Page 121: ...oves noise immunity by using a simple digital filtering scheme The noise canceler input is monitored over four samples and all four must be equal for changing the output that in turn is used by the edge detector The noise canceler is enabled by setting the Input Capture Noise Canceler ICNC1 bit in Timer Counter Control Register B TCCR1B When enabled the noise canceler introduces addi tional four s...

Page 122: ...eration See Section 13 9 on page 125 A special feature of Output Compare unit A allows it to define the Timer Counter TOP value i e counter resolution In addition to the counter resolution the TOP value defines the period time for waveforms generated by the Waveform Generator Figure 13 4 shows a block diagram of the Output Compare unit The small n in the register and bit names indicates the device...

Page 123: ...rcing compare match will not set the OCF1x Flag or reload clear the timer but the OC1x pin will be updated as if a real compare match had occurred the COM11 0 bits settings define whether the OC1x pin is set cleared or toggled 13 7 2 Compare Match Blocking by TCNT1 Write All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer clock cycle even when the timer ...

Page 124: ...ts are set However the OC1x pin direction input or out put is still controlled by the Data Direction Register DDR for the port pin The Data Direction Register bit for the OC1x pin DDR_OC1x must be set as output before the OC1x value is visi ble on the pin The port override function is generally independent of the Waveform Generation mode but there are some exceptions Refer to Table 13 1 Table 13 2...

Page 125: ...erflow Flag TOV1 will be set in the same timer clock cycle as the TCNT1 becomes zero The TOV1 Flag in this case behaves like a 17th bit except that it is only set not cleared However combined with the timer overflow interrupt that automatically clears the TOV1 Flag the timer resolution can be increased by soft ware There are no special cases to consider in the Normal mode a new counter value can b...

Page 126: ...e pin is set to output DDR_OC1A 1 The waveform generated will have a maximum fre quency of fOC1A fclk_I O 2 when OCR1A is set to zero 0x0000 The waveform frequency is defined by the following equation The N variable represents the prescaler factor 1 8 64 256 or 1024 As for the Normal mode of operation the TOV1 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000 13 ...

Page 127: ...at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value If one of the interrupts are enabled the interrupt han dler routine can be used for updating the TOP and compare values When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers If the TOP value is lower than any ...

Page 128: ... the fast PWM mode If the OCR1x is set equal to BOTTOM 0x0000 the out put will be a narrow spike for each TOP 1 timer clock cycle Setting the OCR1x equal to TOP will result in a constant high or low output depending on the polarity of the output set by the COM1x1 0 bits A frequency with 50 duty cycle waveform output in fast PWM mode can be achieved by set ting OC1A to toggle its logical level on e...

Page 129: ...rflow Flag TOV1 is set each time the counter reaches BOTTOM When either OCR1A or ICR1 is used for defining the TOP value the OC1A or ICF1 Flag is set accord ingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value at TOP The Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value When changing the TOP val...

Page 130: ...nerating a PWM waveform output in the phase correct PWM mode If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non inverted PWM mode For inverted PWM the output will have the opposite logic values If OCR1A is used to define the TOP value WGM13 0 11 and COM1A1 0 1 the OC1A output will toggle with a 50 duty cycle ...

Page 131: ...3 9 Phase and Frequency Correct PWM Mode Timing Diagram The Timer Counter Overflow Flag TOV1 is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value at BOTTOM When either OCR1A or ICR1 is used for defining the TOP value the OC1A or ICF1 Flag set when TCNT1 has reached TOP The Interrupt Flags can then be used to generate an interrupt each time the counte...

Page 132: ...g phase and frequency correct PWM can be calculated by the following equation The N variable represents the prescaler divider 1 8 64 256 or 1024 The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set t...

Page 133: ...g diagrams will be the same but TOP should be replaced by BOTTOM TOP 1 by BOTTOM 1 and so on The same renaming applies for modes that set the TOV1 Flag at BOTTOM Figure 13 12 Timer Counter Timing Diagram no Prescaling OCFnx OCRnx TCNTn OCRnx Value OCRnx 1 OCRnx OCRnx 1 OCRnx 2 clkI O clkTn clkI O 8 TOVn FPWM and ICFn if used as TOP OCRnx Update at TOP TCNTn CTC and FPWM TCNTn PC and PFC PWM TOP 1 ...

Page 134: ...irection Register DDR bit correspond ing to the OC1A or OC1B pin must be set in order to enable the output driver When the OC1A or OC1B is connected to the pin the function of the COM1x1 0 bits is depen dent of the WGM13 0 bits setting Table 13 1 shows the COM1x1 0 bit functionality when the WGM13 0 bits are set to a Normal or a CTC mode non PWM TOVn FPWM and ICFn if used as TOP OCRnx Update at TO...

Page 135: ...r unit are Normal mode counter Clear Timer on Compare match CTC mode and three types of Pulse Width Modulation PWM modes See Section 13 9 on page 125 Table 13 2 Compare Output Mode Fast PWM 1 COM1A1 COM1B1 COM1A0 COM1B0 Description 0 0 Normal port operation OC1A OC1B disconnected 0 1 WGM13 0 14 or 15 Toggle OC1A on Compare Match OC1B disconnected normal port operation For all other WGM1 settings n...

Page 136: ...to the ICES1 setting the counter value is copied into the Input Capture Register ICR1 The event will also set the Input Capture Flag ICF1 and this can be used to cause an Input Capture Interrupt if this interrupt is enabled Table 13 4 Waveform Generation Mode Bit Description 1 Mode WGM13 WGM12 CTC1 WGM11 PWM11 WGM10 PWM10 Timer Counter Mode of Operation TOP Update of OCR1x at TOV1 Flag Set on 0 0 ...

Page 137: ...tput Compare for Channel B The FOC1A FOC1B bits are only active when the WGM13 0 bits specifies a non PWM mode When writing a logical one to the FOC1A FOC1B bit an immediate compare match is forced on the Waveform Generation unit The OC1A OC1B output is changed according to its COM1x1 0 bits setting Note that the FOC1A FOC1B bits are implemented as strobes Therefore it is the value present in the ...

Page 138: ... Compare Register 1 A 13 11 6 OCR1BH and OCR1BL Output Compare Register 1 B The Output Compare Registers contain a 16 bit value that is continuously compared with the counter value TCNT1 A match can be used to generate an Output Compare interrupt or to generate a waveform output on the OC1x pin The Output Compare Registers are 16 bit in size To ensure that both the high and low bytes are written s...

Page 139: ...hese bits are unused bits in the ATmega48P 88P 168P 328P and will always read as zero Bit 2 OCIE1B Timer Counter1 Output Compare B Match Interrupt Enable When this bit is written to one and the I flag in the Status Register is set interrupts globally enabled the Timer Counter1 Output Compare B Match interrupt is enabled The corresponding Interrupt Vector see Interrupts on page 57 is executed when ...

Page 140: ...the OCF1B Flag OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe cuted Alternatively OCF1B can be cleared by writing a logic one to its bit location Bit 1 OCF1A Timer Counter1 Output Compare A Match Flag This flag is set in the timer clock cycle after the counter TCNT1 value matches the Output Compare Register A OCR1A Note that a Forced Output Compare FOC1A str...

Page 141: ...er of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N 1 system clock cycles where N equals the prescaler divisor 8 64 256 or 1024 It is possible to use the prescaler reset for synchronizing the Timer Counter to program execu tion However care must be taken if the other Timer Counter that shares the same prescaler also uses prescaling A prescaler rese...

Page 142: ... a 50 50 duty cycle Since the edge detector uses sampling the maximum frequency of an external clock it can detect is half the sampling fre quency Nyquist sampling theorem However due to variation of the system clock frequency and duty cycle caused by Oscillator source crystal resonator and capacitors tolerances it is recommended that maximum frequency of an external clock source is less than fclk...

Page 143: ...nfigured to the same value without the risk of one of them advancing during configuration When the TSM bit is written to zero the PSRASY and PSRSYNC bits are cleared by hardware and the Timer Counters start counting simultaneously Bit 0 PSRSYNC Prescaler Reset When this bit is one Timer Counter1 and Timer Counter0 prescaler will be Reset This bit is nor mally cleared immediately by hardware except...

Page 144: ...m of the 8 bit Timer Counter is shown in Figure 15 1 For the actual placement of I O pins refer to Pinout ATmega48P 88P 168P 328P on page 2 CPU accessible I O Regis ters including I O bits and I O pins are shown in bold The device specific I O Register and bit locations are listed in the Register Description on page 158 The PRTIM2 bit in Minimizing Power Consumption on page 42 must be written to z...

Page 145: ...2 Definitions Many register and bit references in this document are written in general form A lower case n replaces the Timer Counter number in this case 2 However when using the register or bit defines in a program the precise form must be used i e TCNT2 for accessing Timer Counter2 counter value and so on The definitions in Table 15 1 are also used extensively throughout the section 15 3 Timer C...

Page 146: ...utput Compare outputs OC2A and OC2B For more details about advanced counting sequences and waveform generation see Modes of Operation on page 149 The Timer Counter Overflow Flag TOV2 is set according to the mode of operation selected by the WGM22 0 bits TOV2 can be used for generating a CPU interrupt 15 5 Output Compare Unit The 8 bit comparator continuously compares TCNT2 with the Output Compare ...

Page 147: ... not set the OCF2x Flag or reload clear the timer but the OC2x pin will be updated as if a real compare match had occurred the COM2x1 0 bits settings define whether the OC2x pin is set cleared or toggled 15 5 2 Compare Match Blocking by TCNT2 Write All CPU write operations to the TCNT2 Register will block any compare match that occurs in the next timer clock cycle even when the timer is stopped Th...

Page 148: ... I O pins in the figure are shown in bold Only the parts of the general I O Port Control Registers DDR and PORT that are affected by the COM2x1 0 bits are shown When referring to the OC2x state the reference is for the internal OC2x Register not the OC2x pin Figure 15 4 Compare Match Output Unit Schematic The general I O port function is overridden by the Output Compare OC2x from the Waveform Gene...

Page 149: ...3 15 7 1 Normal Mode The simplest mode of operation is the Normal mode WGM22 0 0 In this mode the counting direction is always up incrementing and no counter clear is performed The counter simply overruns when it passes its maximum 8 bit value TOP 0xFF and then restarts from the bot tom 0x00 In normal operation the Timer Counter Overflow Flag TOV2 will be set in the same timer clock cycle as the T...

Page 150: ... The waveform frequency is defined by the following equation The N variable represents the prescale factor 1 8 32 64 128 256 or 1024 As for the Normal mode of operation the TOV2 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00 15 7 3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode WGM22 0 3 or 7 provides a high fre quency PWM waveform generation opt...

Page 151: ...hen MGM2 0 7 See Table 15 3 on page 158 The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output The PWM wave form is generated by setting or clearing the OC2x Register at the compare match between OCR2x and TCNT2 and clearing or setting the OC2x Register at the timer clock cycle the counter is cleared changes from TOP to BOTTOM The PWM fre...

Page 152: ...symmet ric feature of the dual slope PWM modes these modes are preferred for motor control applications In phase correct PWM mode the counter is incremented until the counter value matches TOP When the counter reaches TOP it changes the count direction The TCNT2 value will be equal to TOP for one timer clock cycle The timing diagram for the phase correct PWM mode is shown on Figure 15 7 The TCNT2 ...

Page 153: ...transition from high to low even though there is no Compare Match The point of this transition is to guarantee symmetry around BOT TOM There are two cases that give a transition without Compare Match OCR2A changes its value from MAX like in Figure 15 7 When the OCR2A value is MAX the OCn pin value is the same as the result of a down counting compare match To ensure symmetry around BOTTOM the OCn v...

Page 154: ... of OCF2A with Prescaler fclk_I O 8 Figure 15 11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode Figure 15 11 Timer Counter Timing Diagram Clear Timer on Compare Match mode with Pres caler fclk_I O 8 TOVn TCNTn MAX 1 MAX BOTTOM BOTTOM 1 clkI O clkTn clkI O 8 OCFnx OCRnx TCNTn OCRnx Value OCRnx 1 OCRnx OCRnx 1 OCRnx 2 clkI O clkTn clkI O 8 OCFnx OCRnx TCNTn CTC TOP TOP 1 TOP BOTTOM...

Page 155: ...This is particularly important if any of the Output Compare2 interrupt is used to wake up the device since the Output Compare function is disabled during writing to OCR2x or TCNT2 If the write cycle is not finished and the MCU enters sleep mode before the corresponding OCR2xUB bit returns to zero the device will never receive a compare match interrupt and the MCU will not wake up If Timer Counter2...

Page 156: ...clock after waking up from Power save mode is essentially unpredictable as it depends on the wake up time The recommended procedure for reading TCNT2 is thus as follows a Write any value to either of the registers OCR2x or TCCR2x b Wait for the corresponding Update Busy Flag to be cleared c Read TCNT2 During asynchronous operation the synchronization of the Interrupt Flags for the asynchronous tim...

Page 157: ...ndependent clock source for Timer Counter2 The Oscillator is optimized for use with a 32 768 kHz crystal For Timer Counter2 the possible prescaled selections are clkT2S 8 clkT2S 32 clkT2S 64 clkT2S 128 clkT2S 256 and clkT2S 1024 Additionally clkT2S as well as 0 stop may be selected Setting the PSRASY bit in GTCCR resets the prescaler This allows the user to operate with a predictable prescaler ...

Page 158: ...nality when the WGM21 0 bits are set to fast PWM mode Note 1 A special case occurs when OCR2A equals TOP and COM2A1 is set In this case the Com pare Match is ignored but the set or clear is done at BOTTOM See Fast PWM Mode on page 150 for more details Bit 7 6 5 4 3 2 1 0 0xB0 COM2A1 COM2A0 COM2B1 COM2B0 WGM21 WGM20 TCCR2A Read Write R W R W R W R W R R R W R W Initial Value 0 0 0 0 0 0 0 0 Table 1...

Page 159: ...0 bit functionality when the WGM22 0 bits are set to a normal or CTC mode non PWM Table 15 6 shows the COM2B1 0 bit functionality when the WGM22 0 bits are set to fast PWM mode Table 15 4 Compare Output Mode Phase Correct PWM Mode 1 COM2A1 COM2A0 Description 0 0 Normal port operation OC2A disconnected 0 1 WGM22 0 Normal Port Operation OC2A Disconnected WGM22 1 Toggle OC2A on Compare Match 1 0 Clea...

Page 160: ...r maximum TOP counter value and what type of wave form generation to be used see Table 15 8 Modes of operation supported by the Timer Counter unit are Normal mode counter Clear Timer on Compare Match CTC mode and two types of Pulse Width Modulation PWM modes see Modes of Operation on page 149 Notes 1 MAX 0xFF 2 BOTTOM 0x00 Table 15 7 Compare Output Mode Phase Correct PWM Mode 1 COM2B1 COM2B0 Descr...

Page 161: ...e However for ensuring compatibility with future devices this bit must be set to zero when TCCR2B is written when operating in PWM mode When writing a logical one to the FOC2B bit an immediate Compare Match is forced on the Waveform Generation unit The OC2B output is changed according to its COM2B1 0 bits setting Note that the FOC2B bit is implemented as a strobe Therefore it is the value present ...

Page 162: ...nerate an Output Compare interrupt or to generate a waveform output on the OC2A pin 15 11 5 OCR2B Output Compare Register B The Output Compare Register B contains an 8 bit value that is continuously compared with the counter value TCNT2 A match can be used to generate an Output Compare interrupt or to generate a waveform output on the OC2B pin Table 15 9 Clock Select Bit Description CS22 CS21 CS20...

Page 163: ...he Timer Counter2 and the data in OCR2B Output Compare Register2 OCF2B is cleared by hardware when executing the corresponding interrupt handling vector Alternatively OCF2B is cleared by writing a logic one to the flag When the I bit in SREG OCIE2B Timer Counter2 Compare match Interrupt Enable and OCF2B are set one the Timer Counter2 Compare match Interrupt is executed Bit 1 OCF2A Output Compare F...

Page 164: ...en this bit becomes set When OCR2A has been updated from the temporary storage register this bit is cleared by hard ware A logical zero in this bit indicates that OCR2A is ready to be updated with a new value Bit 2 OCR2BUB Output Compare Register2 Update Busy When Timer Counter2 operates asynchronously and OCR2B is written this bit becomes set When OCR2B has been updated from the temporary storage...

Page 165: ...s bit is one the Timer Counter2 prescaler will be reset This bit is normally cleared immediately by hardware If the bit is written when Timer Counter2 is operating in asynchronous mode the bit will remain one until the prescaler has been reset The bit will not be cleared by hardware if the TSM bit is set Refer to the description of the Bit 7 TSM Timer Counter Syn chronization Mode on page 143 for ...

Page 166: ... 2 Master SPI Mode 16 2 Overview The Serial Peripheral Interface SPI allows high speed synchronous data transfer between the ATmega48P 88P 168P 328P and peripheral devices or between several AVR devices The USART can also be used in Master SPI mode see USART in SPI Mode on page 204 The PRSPI bit in Minimizing Power Consumption on page 42 must be written to zero to enable SPI module Figure 16 1 SPI...

Page 167: ...e end of packet by pulling high the Slave Select SS line The last incoming byte will be kept in the Buffer Register for later use When configured as a Slave the SPI interface will remain sleeping with MISO tri stated as long as the SS pin is driven high In this state software may update the contents of the SPI Data Register SPDR but the data will not be shifted out by incoming clock pulses on the ...

Page 168: ...r defined SPI pins The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins DD_MOSI DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins E g if MOSI is placed on pin PB5 replace DD_MOSI with DDB5 and DDR_SPI w...

Page 169: ...SPR0 out SPCR r17 ret SPI_MasterTransmit Start transmission of data r16 out SPDR r16 Wait_Transmit Wait for transmission complete in r16 SPSR sbrsr16 SPIF rjmp Wait_Transmit ret C Code Example 1 void SPI_MasterInit void Set MOSI and SCK output all others input DDR_SPI 1 DD_MOSI 1 DD_SCK Enable SPI Master set clock rate fck 16 SPCR 1 SPE 1 MSTR 1 SPR0 void SPI_MasterTransmit char cData Start transm...

Page 170: ... all others input ldi r17 1 DD_MISO out DDR_SPI r17 Enable SPI ldi r17 1 SPE out SPCR r17 ret SPI_SlaveReceive Wait for reception complete sbis SPSR SPIF rjmp SPI_SlaveReceive Read received data and return in r16 SPDR ret C Code Example 1 void SPI_SlaveInit void Set MISO output all others input DDR_SPI 1 DD_MISO Enable SPI SPCR 1 SPE char SPI_SlaveReceive void Wait for reception complete while SPS...

Page 171: ...e SPI system interprets this as another master selecting the SPI as a slave and starting to send data to it To avoid bus contention the SPI system takes the following actions 1 The MSTR bit in SPCR is cleared and the SPI system becomes a Slave As a result of the SPI becoming a Slave the MOSI and SCK pins become inputs 2 The SPIF Flag in SPSR is set and if the SPI interrupt is enabled and the I bit...

Page 172: ...SI MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SCK CPOL 1 mode 2 SS MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 MSB first DORD 0 LSB first DORD 1 SCK CPOL 0 mode 1 SAMPLE I MOSI MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SCK CPOL 1 mode 3 SS MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB MSB first DORD 0 LSB first DORD 1 ...

Page 173: ...and is driven low while MSTR is set MSTR will be cleared and SPIF in SPSR will become set The user will then have to set MSTR to re enable SPI Mas ter mode Bit 3 CPOL Clock Polarity When this bit is written to one SCK is high when idle When CPOL is written to zero SCK is low when idle Refer to Figure 16 3 and Figure 16 4 for an example The CPOL functionality is sum marized below Bit 2 CPHA Clock P...

Page 174: ...Register SPDR is written during a data transfer The WCOL bit and the SPIF bit are cleared by first reading the SPI Status Register with WCOL set and then accessing the SPI Data Register Bit 5 1 Res Reserved Bits These bits are reserved bits in the ATmega48P 88P 168P 328P and will always read as zero Bit 0 SPI2X Double SPI Speed Bit When this bit is written logic one the SPI speed SCK Frequency wil...

Page 175: ...ed for data transfer between the Register File and the SPI Shift Register Writing to the register initiates data transmission Reading the regis ter causes the Shift Register Receive buffer to be read Bit 7 6 5 4 3 2 1 0 0x2E 0x4E MSB LSB SPDR Read Write R W R W R W R W R W R W R W R W Initial Value X X X X X X X X Undefined ...

Page 176: ...ical zero to it A simplified block diagram of the USART Transmitter is shown in Figure 17 1 on page 177 CPU accessible I O Registers and I O pins are shown in bold The dashed boxes in the block diagram separate the three main parts of the USART listed from the top Clock Generator Transmitter and Receiver Control Registers are shared by all units The Clock Generation logic consists of synchronizati...

Page 177: ...between asynchronous and synchronous operation Double Speed asynchronous mode only is controlled by the U2Xn found in the UCSRnA Register When using synchronous mode UMSELn 1 the Data Direction Register for the XCKn pin DDR_XCKn controls whether the clock source is internal Master mode or external Slave mode The XCKn pin is only active when using synchronous mode PARITY GENERATOR UBRRn H L UDRn Tr...

Page 178: ...ister UBRRn and the down counter connected to it function as a programmable prescaler or baud rate generator The down counter running at system clock fosc is loaded with the UBRRn value each time the counter has counted down to zero or when the UBRRnL Register is written A clock is generated each time the counter reaches zero This clock is the baud rate generator clock output fosc UBRRn 1 The Tran...

Page 179: ... the asynchronous operation Set this bit to zero when using synchronous operation Setting this bit will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication Note however that the Receiver will in this case only use half the number of samples reduced from 16 to 8 for data sampling and clock recovery and therefore a more accur...

Page 180: ...1 the XCKn pin will be used as either clock input Slave or clock output Master The dependency between the clock edges and data sampling or data change is the same The basic principle is that data input on RxDn is sampled at the opposite XCKn clock edge of the edge the data output TxDn is changed Figure 17 3 Synchronous Mode XCKn Timing The UCPOLn bit UCRSC selects which XCKn clock edge is used for...

Page 181: ...ransmitter use the same setting Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter The USART Character SiZe UCSZn2 0 bits select the number of data bits in the frame The USART Parity mode UPMn1 0 bits enable and set the type of parity bit The selection between one or two stop bits is done by the USART Stop Bit Select USB...

Page 182: ...ed baud rate or frame format be sure that there are no ongoing transmissions during the period the registers are changed The TXCn Flag can be used to check that the Transmitter has completed all transfers and the RXC Flag can be used to check that there are no unread data in the receive buffer Note that the TXCn Flag must be cleared before each transmission before UDRn is written if it is used for...

Page 183: ...in the UCSRnB Register When the Transmitter is enabled the normal port operation of the TxDn pin is overrid den by the USART and given the function as the Transmitter s serial output The baud rate mode of operation and frame format must be set up once before doing any transmissions If syn Assembly Code Example 1 USART_Init Set baud rate out UBRRnH r17 out UBRRnL r16 Enable receiver and transmitter...

Page 184: ...polling of the Data Register Empty UDREn Flag When using frames with less than eight bits the most sig nificant bits written to the UDRn are ignored The USART has to be initialized before the function can be used For the assembly code the data to be sent is assumed to be stored in Register R16 Note 1 See Code Examples on page 7 The function simply waits for the transmit buffer to be empty by check...

Page 185: ...data This bit is set when the transmit buffer is empty and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register For compat ibility with future devices always write this bit to zero when writing the UCSRnA Register When the Data Register Empty Interrupt Enable UDRIEn bit in UCSRnB is written to one the USART Data Register Empty Interru...

Page 186: ... Disabling the Transmitter The disabling of the Transmitter setting the TXEN to zero will not become effective until ongo ing and pending transmissions are completed i e when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted When disabled the Transmitter will no longer override the TxDn pin 17 7 Data Reception The USART Receiver The USART Receiver is en...

Page 187: ...e used UCSZn 7 the ninth bit must be read from the RXB8n bit in UCSRnB before reading the low bits from the UDRn This rule applies to the FEn DORn and UPEn Status Flags as well Read status from UCSRnA then data from UDRn Reading the UDRn I O location will change the state of the receive buffer FIFO and consequently the TXB8n FEn DORn and UPEn bits which all are stored in the FIFO will change The f...

Page 188: ...s early as possible Assembly Code Example 1 USART_Receive Wait for data to be received sbis UCSRnA RXCn rjmp USART_Receive Get status and 9th bit then data from buffer in r18 UCSRnA in r17 UCSRnB in r16 UDRn If error return 1 andi r18 1 FEn 1 DORn 1 UPEn breq USART_ReceiveNoError ldi r17 HIGH 1 ldi r16 LOW 1 USART_ReceiveNoError Filter the 9th bit then return lsr r17 andi r17 0x01 ret C Code Examp...

Page 189: ...stored in the receive buffer The FEn Flag is zero when the stop bit was correctly read as one and the FEn Flag will be one when the stop bit was incorrect zero This flag can be used for detecting out of sync conditions detecting break conditions and protocol handling The FEn Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all except for the first stop bits...

Page 190: ...allow access to extended I O Typically LDS and STS combined with SBRS SBRC SBR and CBR 17 8 Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxDn pin The data recovery logic sam...

Page 191: ...n Double Speed mode Figure 17 6 shows the sampling of the data bits and the parity bit Each of the samples is given a number that is equal to the state of the recovery unit Figure 17 6 Sampling of Data and Parity Bit The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three samples in the center of the received bit The center samples ar...

Page 192: ...ud rate of the Receiver does not have a similar see Table 17 2 on page 193 base frequency the Receiver will not be able to synchronize the frames to the start bit The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate D Sum of character size and parity size D 5 to 10 bit S Samples per bit S 16 for Normal Speed mode and S 8 for Double Sp...

Page 193: ...rmation will be ignored and not put into the receive buffer This effectively reduces the number of incoming frames that has to be handled by the CPU in a system with multiple MCUs that communicate via the same serial bus The Transmitter is unaffected by the MPCMn setting but has to be used differently when it is a part of a system utilizing the Multi processor Communication mode If the Receiver is...

Page 194: ...set 2 The Master MCU sends an address frame and all slaves receive and read this frame In the Slave MCUs the RXCn Flag in UCSRnA will be set as normal 3 Each Slave MCU reads the UDRn Register and determines if it has been selected If so it clears the MPCMn bit in UCSRnA otherwise it waits for the next address byte and keeps the MPCMn setting 4 The addressed MCU will receive all data frames until a...

Page 195: ...g bit test instructions SBIC and SBIS since these also will change the state of the FIFO 17 10 2 UCSRnA USART Control and Status Register n A Bit 7 RXCn USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty i e does not contain any unread data If the Receiver is disabled the receive buffer will be flushed and conse...

Page 196: ... This bit only has effect for the asynchronous operation Write this bit to zero when using syn chronous operation Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou bling the transfer rate for asynchronous communication Bit 0 MPCMn Multi processor Communication Mode This bit enables the Multi processor Communication mode When the MPCMn bit is writ...

Page 197: ...itted When disabled the Transmitter will no longer override the TxDn port Bit 2 UCSZn2 Character Size n The UCSZn2 bits combined with the UCSZn1 0 bit in UCSRnC sets the number of data bits Character SiZe in a frame the Receiver and Transmitter use Bit 1 RXB8n Receive Data Bit 8 n RXB8n is the ninth data bit of the received character when operating with serial frames with nine data bits Must be re...

Page 198: ...Zn1 0 Character Size The UCSZn1 0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits Character SiZe in a frame the Receiver and Transmitter use Bit 0 UCPOLn Clock Polarity This bit is used for synchronous mode only Write this bit to zero when asynchronous mode is used The UCPOLn bit sets the relationship between data output change and data input sample and the synchronous clo...

Page 199: ...requencies the most commonly used baud rates for asyn chronous operation can be generated by using the UBRRn settings in Table 17 9 UBRRn values which yield an actual baud rate differing less than 0 5 from the target baud rate are bold in the table Higher error ratings are acceptable but the Receiver will have less noise resis tance when the error ratings are high especially for large serial frame...

Page 200: ...or 2400 25 0 2 51 0 2 47 0 0 95 0 0 51 0 2 103 0 2 4800 12 0 2 25 0 2 23 0 0 47 0 0 25 0 2 51 0 2 9600 6 7 0 12 0 2 11 0 0 23 0 0 12 0 2 25 0 2 14 4k 3 8 5 8 3 5 7 0 0 15 0 0 8 3 5 16 2 1 19 2k 2 8 5 6 7 0 5 0 0 11 0 0 6 7 0 12 0 2 28 8k 1 8 5 3 8 5 3 0 0 7 0 0 3 8 5 8 3 5 38 4k 1 18 6 2 8 5 2 0 0 5 0 0 2 8 5 6 7 0 57 6k 0 8 5 1 8 5 1 0 0 3 0 0 1 8 5 3 8 5 76 8k 1 18 6 1 25 0 2 0 0 1 18 6 2 8 5 11...

Page 201: ... 0 2 95 0 0 191 0 0 9600 23 0 0 47 0 0 25 0 2 51 0 2 47 0 0 95 0 0 14 4k 15 0 0 31 0 0 16 2 1 34 0 8 31 0 0 63 0 0 19 2k 11 0 0 23 0 0 12 0 2 25 0 2 23 0 0 47 0 0 28 8k 7 0 0 15 0 0 8 3 5 16 2 1 15 0 0 31 0 0 38 4k 5 0 0 11 0 0 6 7 0 12 0 2 11 0 0 23 0 0 57 6k 3 0 0 7 0 0 3 8 5 8 3 5 7 0 0 15 0 0 76 8k 2 0 0 5 0 0 2 8 5 6 7 0 5 0 0 11 0 0 115 2k 1 0 0 3 0 0 1 8 5 3 8 5 3 0 0 7 0 0 230 4k 0 0 0 1 0...

Page 202: ...3 0 0 9600 51 0 2 103 0 2 71 0 0 143 0 0 95 0 0 191 0 0 14 4k 34 0 8 68 0 6 47 0 0 95 0 0 63 0 0 127 0 0 19 2k 25 0 2 51 0 2 35 0 0 71 0 0 47 0 0 95 0 0 28 8k 16 2 1 34 0 8 23 0 0 47 0 0 31 0 0 63 0 0 38 4k 12 0 2 25 0 2 17 0 0 35 0 0 23 0 0 47 0 0 57 6k 8 3 5 16 2 1 11 0 0 23 0 0 15 0 0 31 0 0 76 8k 6 7 0 12 0 2 8 0 0 17 0 0 11 0 0 23 0 0 115 2k 3 8 5 8 3 5 5 0 0 11 0 0 7 0 0 15 0 0 230 4k 1 8 5 ...

Page 203: ... 520 0 0 9600 103 0 2 207 0 2 119 0 0 239 0 0 129 0 2 259 0 2 14 4k 68 0 6 138 0 1 79 0 0 159 0 0 86 0 2 173 0 2 19 2k 51 0 2 103 0 2 59 0 0 119 0 0 64 0 2 129 0 2 28 8k 34 0 8 68 0 6 39 0 0 79 0 0 42 0 9 86 0 2 38 4k 25 0 2 51 0 2 29 0 0 59 0 0 32 1 4 64 0 2 57 6k 16 2 1 34 0 8 19 0 0 39 0 0 21 1 4 42 0 9 76 8k 12 0 2 25 0 2 14 0 0 29 0 0 15 1 7 32 1 4 115 2k 8 3 5 16 2 1 9 0 0 19 0 0 10 1 4 21 1...

Page 204: ...the data and clock recovery logic and the RX and TX control logic is disabled The USART RX and TX control logic is replaced by a common SPI transfer control logic However the pin control logic and interrupt generation logic is identical in both modes of operation The I O register locations are the same in both modes However some of the functionality of the control registers changes when using MSPI...

Page 205: ...on opposite edges of the XCKn signal ensuring sufficient time for data signals to stabilize The UCPOLn and UCPHAn function ality is summarized in Table 18 2 Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter Table 18 1 Equations for Calculating Baud Rate Register Setting Operating Mode Equation for Calculating Baud Rate ...

Page 206: ...cation can take place The initialization process normally consists of setting the baud rate setting master mode of operation by setting DDR_XCKn to one setting frame format and enabling the Transmitter and the Receiver Only the transmitter can operate independently For interrupt driven USART opera tion the Global Interrupt Flag should be cleared and thus interrupts globally disabled when doing the...

Page 207: ...Example 1 USART_Init clr r18 out UBRRnH r18 out UBRRnL r18 Setting the XCKn port pin as output enables master mode sbi XCKn_DDR XCKn Set MSPI mode of operation and SPI data mode 0 ldi r18 1 UMSELn1 1 UMSELn0 0 UCPHAn 0 UCPOLn out UCSRnC r18 Enable receiver and transmitter ldi r18 1 RXENn 1 TXENn out UCSRnB r18 Set baud rate IMPORTANT The Baud Rate must be set after the transmitter is enabled out U...

Page 208: ...rame Note To keep the input buffer in sync with the number of data bytes transmitted the UDRn register must be read once for each byte transmitted The input buffer operation is identical to normal USART mode i e if an overflow occurs the character last received will be lost not the first data in the buf fer This means that if four bytes are transferred byte 1 first then byte 2 3 and 4 and the UDRn...

Page 209: ...er in USART in MSPIM mode is identical in function to the normal USART operation Assembly Code Example 1 USART_MSPIM_Transfer Wait for empty transmit buffer sbis UCSRnA UDREn rjmp USART_MSPIM_Transfer Put data r16 into buffer sends the data out UDRn r16 Wait for data to be received USART_MSPIM_Wait_RXCn sbis UCSRnA RXCn rjmp USART_MSPIM_Wait_RXCn Get and return received data from buffer in r16 UDR...

Page 210: ...PIM mode the following features differ between the two modules The USART in MSPIM mode includes double buffering of the transmitter The SPI has no buffer The USART in MSPIM mode receiver includes an additional buffer level The SPI WCOL Write Collision bit is not included in USART in MSPIM mode The SPI double speed mode SPI2X bit is not included However the same effect is achieved by setting UBRRn ...

Page 211: ...plete interrupt is executed or it can be cleared by writing a one to its bit location The TXCn Flag can generate a Transmit Complete interrupt see description of the TXCIEn bit Bit 5 UDREn USART Data Register Empty The UDREn Flag indicates if the transmit buffer UDRn is ready to receive new data If UDREn is one the buffer is empty and therefore ready to be written The UDREn Flag can generate a Dat...

Page 212: ...he USART Transmitter The Transmitter will override normal port operation for the TxDn pin when enabled The disabling of the Transmitter writing TXENn to zero will not become effective until ongoing and pending transmissions are completed i e when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans mitted When disabled the Transmitter will no longer override the...

Page 213: ...ock Phase The UCPHAn bit setting determine if data is sampled on the leasing edge first or tailing last edge of XCKn Refer to the SPI Data Modes and Timing section page 4 for details Bit 0 UCPOLn Clock Polarity The UCPOLn bit sets the polarity of the XCKn clock The combination of the UCPOLn and UCPHAn bit settings determine the timing of the data transfer Refer to the SPI Data Modes and Timing sec...

Page 214: ...ress Recognition Causes Wake up When AVR is in Sleep Mode Compatible with Philips I2 C protocol 19 2 2 wire Serial Interface Bus Definition The 2 wire Serial Interface TWI is ideally suited for typical microcontroller applications The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi directional bus lines one for clock SCL and one for data SDA T...

Page 215: ...WI devices tri state their outputs allowing the pull up resistors to pull the line high Note that all AVR devices connected to the TWI bus must be powered in order to allow any bus operation The number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400 pF and the 7 bit slave address space A detailed specification of the electrical char acteristics of th...

Page 216: ...e bus is considered busy and no other master should try to seize control of the bus A special case occurs when a new START condition is issued between a START and STOP condition This is referred to as a REPEATED START condition and is used when the Master wishes to initiate a new transfer without relin quishing control of the bus After a REPEATED START the bus is considered busy until the next STO...

Page 217: ...ansmit the same message to several slaves in the system When the general call address followed by a Write bit is transmitted on the bus all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle The following data packets will then be received by all the slaves that acknowledged the general call Note that transmitting the general call address followed by a Read b...

Page 218: ... SLA R W and the STOP condition depending on the software protocol imple mented by the application software Figure 19 6 Typical Data Transmission 19 4 Multi master Bus Systems Arbitration and Synchronization The TWI protocol allows bus systems with several masters Special concerns have been taken in order to ensure that transmissions will proceed as normal even if two or more masters initiate a tr...

Page 219: ... high and low time out periods when the combined SCL line goes high or low respectively Figure 19 7 SCL Synchronization Between Multiple Masters Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data If the value read from the SDA line does not match the value the Master had output it has lost the arbitration Note that a Master can only lose arbitratio...

Page 220: ... user software s responsibility to ensure that these illegal arbitration conditions never occur This implies that in multi master systems all data transfers must use the same composi tion of SLA R W and data packets In other words All transmissions must contain the same number of data packets otherwise the result of the arbitration is undefined SDA from Master A SDA from Master B SDA Line Synchron...

Page 221: ...ort section The internal pull ups can in some systems eliminate the need for external ones 19 5 2 Bit Rate Generator Unit This unit controls the period of SCL when operating in a Master mode The SCL period is con trolled by settings in the TWI Bit Rate Register TWBR and the Prescaler bits in the TWI Status Register TWSR Slave operation does not depend on Bit Rate or Prescaler settings but the CPU ...

Page 222: ...ne if arbitration is in process If the TWI has lost an arbitration the Control Unit is informed Correct action can then be taken and appropriate status codes generated 19 5 4 Address Match Unit The Address Match unit checks if received address bytes match the seven bit address in the TWI Address Register TWAR If the TWI General Call Recognition Enable TWGCE bit in the TWAR is written to one all in...

Page 223: ...interrupt based the application software is free to carry on other operations during a TWI byte transfer Note that the TWI Interrupt Enable TWIE bit in TWCR together with the Global Interrupt Enable bit in SREG allow the application to decide whether or not assertion of the TWINT Flag should gener ate an interrupt request If the TWIE bit is cleared the application must poll the TWINT Flag in order...

Page 224: ...the TWI will initiate transmission of the address packet 4 When the address packet has been transmitted the TWINT Flag in TWCR is set and TWSR is updated with a status code indicating that the address packet has successfully been sent The status code will also reflect whether a Slave acknowledged the packet or not 5 The application software should now examine the value of TWSR to make sure that th...

Page 225: ...ing a one to TWINT clears the flag The TWI will not start any operation as long as the TWINT bit in TWCR is set Immediately after the application has cleared TWINT the TWI will initiate transmission of the STOP condi tion Note that TWINT is NOT set after a STOP condition has been sent Even though this example is simple it shows the principles involved in all TWI transmissions These can be summariz...

Page 226: ...CR 1 TWINT Wait for TWINT Flag set This indicates that the SLA W has been transmitted and ACK NACK has been received 5 in r16 TWSR andi r16 0xF8 cpi r16 MT_SLA_ACK brne ERROR if TWSR 0xF8 MT_SLA_ACK ERROR Check value of TWI Status Register Mask prescaler bits If status different from MT_SLA_ACK go to ERROR ldi r16 DATA out TWDR r16 ldi r16 1 TWINT 1 TWEN out TWCR r16 TWDR DATA TWCR 1 TWINT 1 TWEN ...

Page 227: ... Slave Address In Figure 19 12 to Figure 19 18 circles are used to indicate that the TWINT Flag is set The numbers in the circles show the status code held in TWSR with the prescaler bits masked to zero At these points actions must be taken by the application to continue or complete the TWI transfer The TWI transfer is suspended until the TWINT Flag is cleared by software When the TWINT Flag is se...

Page 228: ... appropriate action to be taken for each of these status codes is detailed in Table 19 2 When SLA W has been successfully transmitted a data packet should be transmitted This is done by writing the data byte to TWDR TWDR must only be written when TWINT is high If not the access will be discarded and the Write Collision bit TWWC will be set in the TWCR Regis ter After updating TWDR the TWINT bit sh...

Page 229: ...nsmitted and TWSTO Flag will be reset 0x20 SLA W has been transmitted NOT ACK has been received Load data byte or No TWDR action or No TWDR action or No TWDR action 0 1 0 1 0 0 1 1 1 1 1 1 X X X X Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO Flag will be reset STOP condition followed by a START con...

Page 230: ... that the prescaler bits are zero or are masked to zero S SLA W A DATA A P 08 18 28 R SLA W 10 A P 20 P 30 A or A 38 A Other master continues A or A 38 Other master continues R A 68 Other master continues 78 B0 To corresponding states in slave mode MT MR Successfull transmission to a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave addre...

Page 231: ...tatus codes in Master mode are 0x38 0x40 or 0x48 The appropriate action to be taken for each of these status codes is detailed in Table 19 3 Received data can be read from the TWDR Register when the TWINT Flag is set high by hardware This scheme is repeated until the last byte has been received After the last byte has been received the MR should inform the ST by sending a NACK after the last recei...

Page 232: ...ered A START condition will be transmitted when the bus becomes free 0x40 SLA R has been transmitted ACK has been received No TWDR action or No TWDR action 0 0 0 0 1 1 0 1 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned 0x48 SLA R has been transmitted NOT ACK has been received No TWDR action or No TWDR action or No TWDR action 1 0 1 0 1 1...

Page 233: ...master continues W A 68 Other master continues 78 B0 To corresponding states in slave mode MR MT Successfull reception from a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or data byte Arbitration lost and addressed as slave DATA A n From master to slave From slave to master Any number of data...

Page 234: ...e states 0x68 and 0x78 If the TWEA bit is reset during a transfer the TWI will return a Not Acknowledge 1 to SDA after the next received data byte This can be used to indicate that the Slave is not able to receive any more bytes While TWEA is zero the TWI does not acknowledge its own slave address However the 2 wire Serial Bus is still monitored and address recognition may resume at any time by se...

Page 235: ...or GCA Switched to the not addressed Slave mode own SLA will be recognized GCA will be recognized if TWGCE 1 Switched to the not addressed Slave mode no recognition of own SLA or GCA a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode own SLA will be recognized GCA will be recognized if TWGCE 1 a START condition will be transmitted when the bus ...

Page 236: ...knowledged Last data byte received is not acknowledged Arbitration lost as master and addressed as slave Reception of the general call address and one or more data bytes Last data byte received is not acknowledged n From master to slave From slave to master Any number of data bytes and their associated acknowledge bits This number contained in TWSR corresponds to a defined state of the 2 Wire Seri...

Page 237: ... the Master Receiver transmits a NACK or ACK after the final byte The TWI is switched to the not addressed Slave mode and will ignore the Master if it continues the transfer Thus the Master Receiver receives all 1 as serial data State 0xC8 is entered if the Master demands additional data bytes by transmitting ACK even though the Slave has transmitted the last byte TWEA zero and expect ing NACK fro...

Page 238: ...ransmitted NOT ACK has been received No TWDR action or No TWDR action or No TWDR action or No TWDR action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 Switched to the not addressed Slave mode no recognition of own SLA or GCA Switched to the not addressed Slave mode own SLA will be recognized GCA will be recognized if TWGCE 1 Switched to the not addressed Slave mode no recognition of own SLA or GCA a START cond...

Page 239: ...lete the desired action Consider for example reading data from a serial EEPROM Typically such a transfer involves the following steps 1 The transfer must be initiated 2 The EEPROM must be instructed what location should be read 3 The reading must be performed 4 The transfer must be finished S SLA R A DATA A A8 B8 A B0 Reception of the own slave address and one or more data bytes Last data byte tra...

Page 240: ...ne or more of them The TWI standard ensures that such situations are handled in such a way that one of the masters will be allowed to proceed with the transfer and that no data will be lost in the process An example of an arbitration situation is depicted below where two masters are trying to transmit data to a Slave Receiver Figure 19 20 An Arbitration Example Several different scenarios may aris...

Page 241: ...for calculating bit rates 19 9 2 TWCR TWI Control Register The TWCR is used to control the operation of the TWI It is used to enable the TWI to initiate a Master access by applying a START condition to the bus to generate a Receiver acknowledge to generate a stop condition and to control halting of the bus while the data to be written to the bus are written to the TWDR It also indicates a write co...

Page 242: ...he application writes the TWSTA bit to one when it desires to become a Master on the 2 wire Serial Bus The TWI hardware checks if the bus is available and generates a START condition on the bus if it is free However if the bus is not free the TWI waits until a STOP condition is detected and then generates a new START condition to claim the bus Master status TWSTA must be cleared by software when t...

Page 243: ...tes see Bit Rate Generator Unit on page 221 The value of TWPS1 0 is used in the equation 19 9 4 TWDR TWI Data Register In Transmit mode TWDR contains the next byte to be transmitted In Receive mode the TWDR contains the last byte received It is writable while the TWI is not in the process of shifting a byte This occurs when the TWI Interrupt Flag TWINT is set by hardware Note that the Data Regis t...

Page 244: ...for the slave address or general call address if enabled in the received serial address If a match is found an interrupt request is generated Bits 7 1 TWA TWI Slave Address Register These seven bits constitute the slave address of the TWI unit Bit 0 TWGCE TWI General Call Recognition Enable Bit If set this bit enables the recognition of a General Call given over the 2 wire Serial Bus 19 9 6 TWAMR ...

Page 245: ...ure 19 22 TWI Address Match Logic Block Diagram Bit 0 Res Reserved Bit This bit is an unused bit in the ATmega48P 88P 168P 328P and will always read as zero Address Match Address Bit Comparator 0 Address Bit Comparator 6 1 TWAR0 TWAMR0 Address Bit 0 ...

Page 246: ...on on page 42 must be disabled by writing a logical zero to be able to use the ADC input MUX Figure 20 1 Analog Comparator Block Diagram 2 Notes 1 See Table 20 1 on page 247 2 Refer to Figure 1 1 on page 2 and Table 11 9 on page 88 for Analog Comparator pin placement 20 2 Analog Comparator Multiplexed Input It is possible to select any of the ADC7 0 pins to replace the negative input to the Analog...

Page 247: ...tive and Idle mode When changing the ACD bit the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR Otherwise an interrupt can occur when the bit is changed Bit 6 ACBG Analog Comparator Bandgap Select When this bit is set a fixed bandgap reference voltage replaces the positive input to the Analog Comparator When this bit is cleared AIN0 is applied to the positive input o...

Page 248: ...omparator Input Capture Enable When written logic one this bit enables the input capture function in Timer Counter1 to be trig gered by the Analog Comparator The comparator output is in this case directly connected to the input capture front end logic making the comparator utilize the noise canceler and edge select features of the Timer Counter1 Input Capture interrupt When written logic zero no c...

Page 249: ...is bit is written logic one the digital input buffer on the AIN1 0 pin is disabled The corre sponding PIN Register bit will always read as zero when this bit is set When an analog signal is applied to the AIN1 0 pin and the digital input from this pin is not needed this bit should be writ ten logic one to reduce power consumption in the digital input buffer Bit 7 6 5 4 3 2 1 0 0x7F AIN1D AIN0D DID...

Page 250: ...circuit which ensures that the input voltage to the ADC is held at a constant level during conversion A block diagram of the ADC is shown in Figure 21 1 on page 251 The ADC has a separate analog supply voltage pin AVCC AVCC must not differ more than 0 3V from VCC See the paragraph ADC Noise Canceler on page 256 on how to connect this pin Internal reference voltages of nominally 1 1V or AVCC are pr...

Page 251: ...right adjusted but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX If the result is left adjusted and no more than 8 bit precision is required it is sufficient to read ADCH Otherwise ADCL must be read first then ADCH to ensure that the content of the Data Registers belongs to the same conversion Once ADCL is read ADC access to Data Registers is blocked This means that i...

Page 252: ...elect bits ADTS in ADCSRB See description of the ADTS bits for a list of the trigger sources When a positive edge occurs on the selected trigger signal the ADC prescaler is reset and a conversion is started This provides a method of starting con versions at fixed intervals If the trigger signal still is set when the conversion completes a new conversion will not be started If another positive edge...

Page 253: ...at the following rising edge of the ADC clock cycle A normal conversion takes 13 ADC clock cycles The first conversion after the ADC is switched on ADEN in ADCSRA is set takes 25 ADC clock cycles in order to initialize the analog circuitry When the bandgap reference voltage is used as input to the ADC it will take a certain time for the voltage to stabilize If not stabilized the first value read a...

Page 254: ...C Sample Hold ADIF ADCH ADCL Cycle Number ADEN 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 First Conversion Next Conversion 3 MUX and REFS Update MUX and REFS Update Conversion Complete 1 2 3 4 5 6 7 8 9 10 11 12 13 Sign and MSB of Result LSB of Result ADC Clock ADSC ADIF ADCH ADCL Cycle Number 1 2 One Conversion Next Conversion 3 Sample Hold MUX and REFS Update Conversion Complete MUX and R...

Page 255: ...Triggering is used the exact time of the triggering event can be indeterministic Special care must be taken when updating the ADMUX Register in order to control which conversion will be affected by the new settings If both ADATE and ADEN is written to one an interrupt event can occur at any time If the ADMUX Register is changed in this period the user cannot tell if the next conversion is based on...

Page 256: ...nce voltmeter Note that VREF is a high impedance source and only a capacitive load should be connected in a system If the user has a fixed voltage source connected to the AREF pin the user may not use the other reference voltage options in the application as they will be shorted to the external voltage If no external voltage is applied to the AREF pin the user may switch between AVCC and 1 1V as r...

Page 257: ... higher than the Nyquist frequency fADC 2 should not be present for either kind of channels to avoid distortion from unpredictable signal convolution The user is advised to remove high frequency components with a low pass filter before applying the signals as inputs to the ADC Figure 21 8 Analog Input Circuitry 21 6 2 Analog Noise Canceling Techniques Digital circuitry inside and outside the devic...

Page 258: ...voltage linearly between GND and VREF in 2n steps LSBs The lowest code is read as 0 and the highest code is read as 2n 1 Several parameters describe the deviation from the ideal behavior Offset The deviation of the first transition 0x000 to 0x001 compared to the ideal transition at 0 5 LSB Ideal value 0 LSB GND VCC PC5 ADC5 SCL PC4 ADC4 SDA PC3 ADC3 PC2 ADC2 PC1 ADC1 PC0 ADC0 ADC7 GND AREF AVCC AD...

Page 259: ...e ideal transition at 1 5 LSB below maximum Ideal value 0 LSB Figure 21 11 Gain Error Integral Non linearity INL After adjusting for offset and gain error the INL is the maximum deviation of an actual transition compared to an ideal transition for any code Ideal value 0 LSB Output Code VREF Input Voltage Ideal ADC Actual ADC Offset Error Output Code VREF Input Voltage Ideal ADC Actual ADC Gain Err...

Page 260: ...Error Due to the quantization of the input voltage into a finite number of codes a range of input voltages 1 LSB wide will code to the same value Always 0 5 LSB Absolute accuracy The maximum deviation of an actual unadjusted transition compared to an ideal transition for any code This is the compound effect of offset gain error differential error non linearity and quantization error Ideal value 0 ...

Page 261: ... can be used in single conversion mode to measure the voltage over the temperature sensor The measured voltage has a linear relationship to the temperature as described in Table 21 2 The voltage sensitivity is approximately 1 mV C and the accuracy of the temperature measure ment is 10 C The values described in Table 21 2 are typical values However due to the process variation the temperature senso...

Page 262: ...DC Data Register immediately regardless of any ongoing conver sions For a complete description of this bit see ADCL and ADCH The ADC Data Register on page 265 Bit 4 Res Reserved Bit This bit is an unused bit in the ATmega48P 88P 168P 328P and will always read as zero Bits 3 0 MUX3 0 Analog Channel Selection Bits The value of these bits selects which analog inputs are connected to the ADC See Table...

Page 263: ...the ADC has been enabled or if ADSC is written at the same time as the ADC is enabled will take 25 ADC clock cycles instead of the normal 13 This first conversion performs initializa tion of the ADC ADSC will read as one as long as a conversion is in progress When the conversion is complete it returns to zero Writing zero to this bit has no effect Table 21 4 Input Channel Selections MUX3 0 Single ...

Page 264: ...IF is cleared by hardware when executing the corresponding interrupt handling vector Alter natively ADIF is cleared by writing a logical one to the flag Beware that if doing a Read Modify Write on ADCSRA a pending interrupt can be disabled This also applies if the SBI and CBI instructions are used Bit 3 ADIE ADC Interrupt Enable When this bit is written to one and the I bit in SREG is set the ADC ...

Page 265: ...rved for future use To ensure compatibility with future devices these bist must be written to zero when ADCSRB is written Bit 2 0 ADTS2 0 ADC Auto Trigger Source If ADATE in ADCSRA is written to one the value of these bits selects which source will trigger an ADC conversion If ADATE is cleared the ADTS2 0 settings will have no effect A conversion will be triggered by the rising edge of the selecte...

Page 266: ...ll always read as zero when this bit is set When an analog signal is applied to the ADC5 0 pin and the digital input from this pin is not needed this bit should be written logic one to reduce power consumption in the digital input buffer Note that ADC pins ADC7 and ADC6 do not have digital input buffers and therefore do not require Digital Input Disable bits Table 21 6 ADC Auto Trigger Source Sele...

Page 267: ...ebug system uses a One wire bi directional interface to control the program flow execute AVR instructions in the CPU and to program the different non volatile memories 22 3 Physical Interface When the debugWIRE Enable DWEN Fuse is programmed and Lock bits are unprogrammed the debugWIRE system within the target device is activated The RESET port pin is configured as a wire AND open drain bi directi...

Page 268: ...mmed each time a Break Point is changed This is automatically handled by AVR Studio through the debugWIRE interface The use of Break Points will therefore reduce the Flash Data retention Devices used for debugging purposes should not be shipped to end customers 22 5 Limitations of debugWIRE The debugWIRE communication pin dW is physically located on the same pin as External Reset RESET An External...

Page 269: ...ng alternative 1 the Boot Loader provides an effective Read Modify Write feature which allows the user software to first read the page do the necessary changes and then write back the modified data If alter native 2 is used it is not possible to read the old data while loading since the page is already erased The temporary page buffer can be accessed in a random sequence It is essential that the p...

Page 270: ...east significant bits is addressing the words within a page while the most significant bits are addressing the pages This is shown in Figure 24 3 on page 282 Note that the Page Erase and Page Write operations are addressed independently Therefore it is of major importance that the software addresses the same page in both the Page Erase and Page Write operation The LPM instruction uses the Z pointe...

Page 271: ...yte load the Z pointer with 0x0000 and set the BLBSET and SELFPRGEN bits in SPMCSR When an LPM instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the SPMCSR the value of the Fuse Low byte FLB will be loaded in the destination register as shown below See Table 25 5 on page 296 for a detailed description and mapping of the Fuse Low byte Similarly when reading ...

Page 272: ...ower supply voltage This can be done by enabling the internal Brown out Detector BOD if the operating volt age matches the detection level If not an external low VCC reset protection circuit can be used If a reset occurs while a write operation is in progress the write operation will be completed provided that the power supply voltage is sufficient 2 Keep the AVR core in Power down sleep mode duri...

Page 273: ... optimized at the expense of code size It is assumed that either the interrupt table is moved to the Boot loader section or that the interrupts are disabled equ PAGESIZEB PAGESIZE 2 PAGESIZEB is page size in BYTES not words org SMALLBOOTSTART Write_page Page Erase ldi spmcrval 1 PGERS 1 SELFPRGEN rcallDo_spm re enable the RWW section ldi spmcrval 1 RWWSRE 1 SELFPRGEN rcallDo_spm transfer data from...

Page 274: ...ion is not ready yet ret re enable the RWW section ldi spmcrval 1 RWWSRE 1 SELFPRGEN rcallDo_spm rjmp Return Do_spm check for previous SPM complete Wait_spm in temp1 SPMCSR sbrc temp1 SELFPRGEN rjmp Wait_spm input spmcrval determines SPM action disable interrupts if enabled store status in temp2 SREG cli check that no EEPROM write access is present Wait_ee sbic EECR EEPE rjmp Wait_ee SPM timed seq...

Page 275: ...mega48P is a subset of the functionality in ATmega88P 168P An LPM instruction within three cycles after BLBSET and SELFPRGEN are set in the SPMCSR Register will read either the Lock bits or the Fuse bits depending on Z0 in the Z pointer into the destination register See Reading the Fuse and Lock Bits from Software on page 271 for details Bit 2 PGWRT Page Write If this bit is written to one at the ...

Page 276: ...LFPRGEN is written the following SPM instruction will store the value in R1 R0 in the temporary page buffer addressed by the Z pointer The LSB of the Z pointer is ignored The SELFPRGEN bit will auto clear upon completion of an SPM instruction or if no SPM instruction is executed within four clock cycles During Page Erase and Page Write the SELFPRGEN bit remains high until the operation is complete...

Page 277: ...re is not needed anymore The size of the Boot Loader memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock bits which can be set independently This gives the user a unique flexibility to select different levels of protection 24 3 Application and Boot Loader Flash Sections The Flash memory is organized in two main sections the Application section and the Boot Load...

Page 278: ... programming a page inside the RWW section it is possible to read code from the Flash but only code that is located in the NRWW section During an on going programming the software must ensure that the RWW section never is being read If the user software is trying to read code that is located inside the RWW section i e by a call jmp lpm or an interrupt during programming the software might end up i...

Page 279: ...d While Write vs No Read While Write Read While Write RWW Section No Read While Write NRWW Section Z pointer Addresses RWW Section Z pointer Addresses NRWW Section CPU is Halted During the Operation Code Located in NRWW Section Can be Read During the Operation ...

Page 280: ...y The general Write Lock Lock Bit mode 2 does not control the programming of the Flash memory by SPM instruction Similarly the general Read Write Lock Lock Bit mode 1 does not control reading nor writing by LPM SPM if it is attempted 0x0000 Flashend Program Memory BOOTSZ 11 Application Flash Section Boot Loader Flash Section Flashend Program Memory BOOTSZ 10 0x0000 Program Memory BOOTSZ 01 Program...

Page 281: ...write to the Application section and LPM executing from the Boot Loader section is not allowed to read from the Application section If Interrupt Vectors are placed in the Boot Loader section interrupts are disabled while executing from the Application section 4 0 1 LPM executing from the Boot Loader section is not allowed to read from the Application section If Interrupt Vectors are placed in the ...

Page 282: ... The content of the Z pointer is ignored and will have no effect on the operation The LPM instruction does also use the Z pointer to store the address Since this instruction addresses the Flash byte by byte also the LSB bit Z0 of the Z pointer is used Figure 24 3 Addressing the Flash During SPM 1 Note 1 The different variables used in Figure 24 3 are listed in Table 24 9 on page 289 24 8 Self Prog...

Page 283: ...nd R0 is ignored The page address must be written to PCPAGE in the Z register Other bits in the Z pointer will be ignored during this operation Page Erase to the RWW section The NRWW section can be read during the Page Erase Page Erase to the NRWW section The CPU is halted during the operation 24 8 2 Filling the Temporary Buffer Page Loading To write an instruction word set up the address in the Z...

Page 284: ... the RWW section after the programming is completed the user software must clear the RWWSB by writing the RWWSRE See Simple Assembly Code Example for a Boot Loader on page 286 for an example 24 8 7 Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits and general Lock Bits write the desired data to R0 write X0001001 to SPMCSR and execute SPM within four clock cycles after writi...

Page 285: ...ination register as shown below Refer to Table 25 7 on page 297 for detailed description and mapping of the Fuse High byte When reading the Extended Fuse byte load 0x0002 in the Z pointer When an LPM instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the SPMCSR the value of the Extended Fuse byte EFB will be loaded in the destination register as shown below ...

Page 286: ...l If not an external low VCC reset protection circuit can be used If a reset occurs while a write operation is in progress the write operation will be completed provided that the power supply voltage is sufficient 3 Keep the AVR core in Power down sleep mode during periods of low VCC This will pre vent the CPU from attempting to decode and execute instructions effectively protecting the SPMCSR Reg...

Page 287: ...crval 1 RWWSRE 1 SELFPRGEN call Do_spm transfer data from RAM to Flash page buffer ldi looplo low PAGESIZEB init loop variable ldi loophi high PAGESIZEB not required for PAGESIZEB 256 Wrloop ld r0 Y ld r1 Y ldi spmcrval 1 SELFPRGEN call Do_spm adiw ZH ZL 2 sbiw loophi looplo 2 use subi for PAGESIZEB 256 brne Wrloop execute Page Write subi ZL low PAGESIZEB restore pointer sbci ZH high PAGESIZEB not...

Page 288: ...n Do_spm check for previous SPM complete Wait_spm in temp1 SPMCSR sbrc temp1 SELFPRGEN rjmp Wait_spm input spmcrval determines SPM action disable interrupts if enabled store status in temp2 SREG cli check that no EEPROM write access is present Wait_ee sbic EECR EEPE rjmp Wait_ee SPM timed sequence out SPMCSR spmcrval spm restore SREG to enable interrupts if originally enabled out SREG temp2 ret ...

Page 289: ...000 0xEFF 0xF00 0xFFF 0xEFF 0xF00 0 1 512 words 16 0x000 0xDFF 0xE00 0xFFF 0xDFF 0xE00 0 0 1024 words 32 0x000 0xBFF 0xC00 0xFFF 0xBFF 0xC00 Table 24 8 Read While Write Limit ATmega88P Section Pages Address Read While Write section RWW 96 0x000 0xBFF No Read While Write section NRWW 32 0xC00 0xFFF Table 24 9 Explanation of Different Variables used in Figure 24 3 and the Mapping to the Z pointer AT...

Page 290: ...EFF 0x1F00 0x1FFF 0x1EFF 0x1F00 0 1 512 words 8 0x0000 0x1DFF 0x1E00 0x1FFF 0x1DFF 0x1E00 0 0 1024 words 16 0x0000 0x1BFF 0x1C00 0x1FFF 0x1BFF 0x1C00 Table 24 11 Read While Write Limit ATmega168P Section Pages Address Read While Write section RWW 112 0x0000 0x1BFF No Read While Write section NRWW 16 0x1C00 0x1FFF Table 24 12 Explanation of Different Variables used in Figure 24 3 and the Mapping to...

Page 291: ... 0x3E00 0x3FFF 0x3DFF 0x3E00 0 1 1024 words 16 0x0000 0x3BFF 0x3C00 0x3FFF 0x3BFF 0x3C00 0 0 2048 words 32 0x0000 0x37FF 0x3800 0x3FFF 0x37FF 0x3800 Table 24 14 Read While Write Limit ATmega328P Section Pages Address Read While Write section RWW 224 0x0000 0x37FF No Read While Write section NRWW 32 0x3800 0x3FFF Table 24 15 Explanation of Different Variables used in Figure 24 3 and the Mapping to ...

Page 292: ...EN will be cleared Then if the RWWSRE bit is written to one at the same time as SELFPRGEN the next SPM instruction within four clock cycles re enables the RWW section The RWW section cannot be re enabled while the Flash is busy with a Page Erase or a Page Write SELFPRGEN is set If the RWWSRE bit is written while the Flash is being loaded the Flash load operation will abort and the data loaded will...

Page 293: ... ing the entire Page Write operation if the NRWW section is addressed Bit 0 SELFPRGEN Self Programming Enable This bit enables the SPM instruction for the next four clock cycles If written to one together with either RWWSRE BLBSET PGWRT or PGERS the following SPM instruction will have a spe cial meaning see description above If only SELFPRGEN is written the following SPM instruction will store the...

Page 294: ...unprogrammed 0 means programmed Table 25 1 Lock Bit Byte 1 Lock Bit Byte Bit No Description Default Value 7 1 unprogrammed 6 1 unprogrammed BLB12 2 5 Boot Lock bit 1 unprogrammed BLB11 2 4 Boot Lock bit 1 unprogrammed BLB02 2 3 Boot Lock bit 1 unprogrammed BLB01 2 2 Boot Lock bit 1 unprogrammed LB2 1 Lock bit 1 unprogrammed LB1 0 Lock bit 1 unprogrammed Table 25 2 Lock Bit Protection Modes 1 2 Mem...

Page 295: ...from the Application section 4 0 1 LPM executing from the Boot Loader section is not allowed to read from the Application section If Interrupt Vectors are placed in the Boot Loader section interrupts are disabled while executing from the Application section BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section 2 1 0 SPM is not allowed to write to the Boot Loa...

Page 296: ...on page 289 Table 24 10 on page 290 and Table 24 13 on page 291 for details 0 programmed 1 BOOTSZ0 1 Select Boot Size see Table 24 7 on page 289 Table 24 10 on page 290 and Table 24 13 on page 291 for details 0 programmed 1 BOOTRST 0 Select Reset Vector 1 unprogrammed Table 25 6 Extended Fuse Byte for ATmega328P Extended Fuse Byte Bit No Description Default Value 7 1 6 1 5 1 4 1 3 1 BODLEVEL2 1 2 ...

Page 297: ...through the Chip Erase 1 unprogrammed EEPROM not reserved BODLEVEL2 4 2 Brown out Detector trigger level 1 unprogrammed BODLEVEL1 4 1 Brown out Detector trigger level 1 unprogrammed BODLEVEL0 4 0 Brown out Detector trigger level 1 unprogrammed Table 25 8 Fuse High Byte for ATmega328P High Fuse Byte Bit No Description Default Value RSTDISBL 1 7 External Reset Disable 1 unprogrammed DWEN 6 debugWIRE...

Page 298: ...g mode and changes of the fuse values will have no effect until the part leaves Programming mode This does not apply to the EESAVE Fuse which will take effect once it is programmed The fuses are also latched on Power up in Normal mode 25 3 Signature Bytes All Atmel microcontrollers have a three byte signature code which identifies the device This code can be read in both serial and parallel mode a...

Page 299: ...see Figure 25 1 and Table 25 13 Pins not described in the following table are referenced by pin names The XA1 XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse The bit coding is shown in Table 25 15 When pulsing WR or OE the command loaded determines the action executed The different Commands are shown in Table 25 16 Table 25 11 No of Words in a Page and No of Pag...

Page 300: ... Byte Select 1 0 selects Low byte 1 selects High byte XA0 PD5 I XTAL Action Bit 0 XA1 PD6 I XTAL Action Bit 1 PAGEL PD7 I Program memory and EEPROM Data Page Load BS2 PC2 I Byte Select 2 0 selects Low byte 1 selects 2 nd High byte DATA PC 1 0 PB 5 0 I O Bi directional Data bus Output when OE is low Table 25 14 Pin Values Used to Enter Programming Mode Pin Symbol Value PAGEL Prog_enable 3 0 XA1 Pro...

Page 301: ...ESET pin to 0V If the rise time of the VCC is unable to fulfill the requirements listed above the following alterna tive algorithm can be used 1 Set Prog_enable pins listed in Table 25 14 on page 300 to 0000 RESET pin to 0V and VCC to 0V 2 Apply 4 5 5 5V between VCC and GND 3 Monitor VCC and as soon as VCC reaches 0 9 1 1V apply 11 5 12 5V to RESET Table 25 15 XA1 and XA0 Coding XA1 XA0 Action whe...

Page 302: ...its are not reset until the program memory has been completely erased The Fuse bits are not changed A Chip Erase must be performed before the Flash and or EEPROM are reprogrammed Note 1 The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed Load Command Chip Erase 1 Set XA1 XA0 to 10 This enables command loading 2 Set BS1 to 0 3 Set DATA to 1000 0000 This is the command...

Page 303: ...ts address the pages within the FLASH This is illustrated in Figure 25 2 on page 304 Note that if less than eight bits are required to address words in the page pagesize 256 the most significant bit s in the address low byte are used to address the page when performing a Page Write G Load Address High byte 1 Set XA1 XA0 to 00 This enables address loading 2 Set BS1 to 1 This selects high address 3 ...

Page 304: ...ws one page of data to be programmed simultaneously The programming algorithm for the EEPROM data memory is as follows refer to Programming the Flash on page 302 for details on Command Address and Data loading 1 A Load Command 0001 0001 2 G Load Address High Byte 0x00 0xFF 3 B Load Address Low Byte 0x00 0xFF 4 C Load Data 0x00 0xFF PROGRAM MEMORY WORD ADDRESS WITHIN A PAGE PAGE ADDRESS WITHIN THE ...

Page 305: ...mand and Address loading 1 A Load Command 0000 0010 2 G Load Address High Byte 0x00 0xFF 3 B Load Address Low Byte 0x00 0xFF 4 Set OE to 0 and BS1 to 0 The Flash word low byte can now be read at DATA 5 Set BS1 to 1 The Flash word high byte can now be read at DATA 6 Set OE to 1 25 7 7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows refer to Programming the Flash on page...

Page 306: ...tive pulse and wait for RDY BSY to go high 5 Set BS1 to 0 This selects low data byte 25 7 10 Programming the Extended Fuse Bits The algorithm for programming the Extended Fuse bits is as follows refer to Programming the Flash on page 302 for details on Command and Data loading 1 1 A Load Command 0100 0000 2 2 C Load Data Low Byte Bit n 0 programs and bit n 1 erases the Fuse bit 3 3 Set BS1 to 0 an...

Page 307: ...TA 0 means programmed 3 Set OE to 0 BS2 to 1 and BS1 to 1 The status of the Fuse High bits can now be read at DATA 0 means programmed 4 Set OE to 0 BS2 to 1 and BS1 to 0 The status of the Extended Fuse bits can now be read at DATA 0 means programmed 5 Set OE to 0 BS2 to 0 and BS1 to 1 The status of the Lock bits can now be read at DATA 0 means programmed 6 Set OE to 1 Figure 25 6 Mapping Between B...

Page 308: ... be executed NOTE in Table 25 17 on page 309 the pin mapping for SPI programming is listed Not all parts use the SPI pins dedicated for the internal SPI interface Figure 25 7 Serial Programming and Verify 1 Notes 1 If the device is clocked by the internal Oscillator it is no need to connect a clock source to the XTAL1 pin 2 VCC 0 3V AVCC VCC 0 3V however AVCC should always be within 1 8 5 5V When ...

Page 309: ...t a time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction To ensure correct loading of the page the data low byte must be loaded before data high byte is applied for a given address The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of the address If polling RDY BSY is not used the user must wai...

Page 310: ... ms Table 25 19 Serial Programming Instruction Set Hexadecimal values Instruction Operation Instruction Format Byte 1 Byte 2 Byte 3 Byte4 Programming Enable AC 53 00 00 Chip Erase Program Memory EEPROM AC 80 00 00 Poll RDY BSY F0 00 00 data byte out Load Instructions Load Extended Address byte 1 4D 00 Extended adr 00 Load Program Memory Page High byte 48 00 adr LSB high data byte in Load Program M...

Page 311: ...programming operation is still pending Wait until this bit returns 0 before the next instruction is carried out Within the same page the low data byte must be loaded prior to the high data byte After data is loaded to the page buffer program the EEPROM page see Figure 25 8 on page 312 Write Instructions 6 Write Program Memory Page 4C adr MSB adr LSB 00 Write EEPROM Memory C0 0000 00aa aaaa aaaa da...

Page 312: ...te 1 Byte 2 Byte 3 Byte 4 Adr LSB Bit 15 B 0 Serial Programming Instruction Program Memory EEPROM Memory Page 0 Page 1 Page 2 Page N 1 Page Buffer Write Program Memory Page Write EEPROM Memory Page Load Program Memory Page High Low Byte Load EEPROM Memory Page page access Byte 1 Byte 2 Byte 3 Byte 4 Bit 15 B 0 Adr MSB Page Offset Page Number Adr M MS SB A A Adr r L LSB B MSB MSB LSB LSB SERIAL CLO...

Page 313: ... Symbol Parameter Condition Min Typ Max Units VIL Input Low Voltage except XTAL1 and RESET pin VCC 1 8V 2 4V VCC 2 4V 5 5V 0 5 0 5 0 2VCC 1 0 3VCC 1 V VIH Input High Voltage except XTAL1 and RESET pins VCC 1 8V 2 4V VCC 2 4V 5 5V 0 7VCC 2 0 6VCC 2 VCC 0 5 VCC 0 5 V VIL1 Input Low Voltage XTAL1 pin VCC 1 8V 5 5V 0 5 0 1VCC 1 V VIH1 Input High Voltage XTAL1 pin VCC 1 8V 2 4V VCC 2 4V 5 5V 0 8VCC 2 0...

Page 314: ...TAL2 should not exceed 150 mA If IIOH exceeds the test condition VOH may exceed the related specification Pins are not guaranteed to source current greater than the listed test condition 26 2 1 ATmega48P DC Characteristics Notes 1 Values with Minimizing Power Consumption enabled 0xFF 2 Typical values at 25 C Maximum values are test limits in production 3 The current consumption values include inpu...

Page 315: ...in Typ 2 Max Units ICC Power Supply Current 1 Active 1 MHz VCC 2V 0 3 0 5 mA Active 4 MHz VCC 3V 1 7 2 5 mA Active 8 MHz VCC 5V 6 3 9 mA Idle 1 MHz VCC 2V 0 05 0 15 mA Idle 4 MHz VCC 3V 0 3 0 7 mA Idle 8 MHz VCC 5V 1 4 2 7 mA Power save mode 3 4 32 kHz TOSC enabled VCC 1 8V 0 72 1 6 µA 32 kHz TOSC enabled VCC 3V 0 9 2 6 µA Power down mode 3 WDT enabled VCC 3V 4 4 8 µA WDT disabled VCC 3V 0 2 2 µA ...

Page 316: ...roduction 26 3 Speed Grades Maximum frequency is dependent on VCC As shown in Figure 26 1 and Figure 26 2 the Maxi mum Frequency vs VCC curve is linear between 1 8V VCC 2 7V and between 2 7V VCC 4 5V TA 40 C to 85 C VCC 1 8V to 5 5V unless otherwise noted Symbol Parameter Condition Min Typ 2 Max Units ICC Power Supply Current 1 Active 1 MHz VCC 2V 0 3 0 5 mA Active 4 MHz VCC 3V 1 7 2 5 mA Active 8...

Page 317: ...P 328P Figure 26 1 Maximum Frequency vs VCC ATmega48P 88P 168PV Figure 26 2 Maximum Frequency vs VCC ATmega48P 88P 168P 4 MHz 1 8V 2 7V 4 5V 10 MHz 20 MHz 5 5V Safe Operating Area 4 MHz 1 8V 2 7V 4 5V 10 MHz 20 MHz 5 5V Safe Operating Area ...

Page 318: ...318 8025I AVR 02 09 ATmega48P 88P 168P 328P Figure 26 3 Maximum Frequency vs VCC ATmega328P 4 MHz 1 8V 2 7V 4 5V 10 MHz 20 MHz 5 5V Safe Operating Area ...

Page 319: ...ues are preliminary values representing design targets and will be updated after characterization of actual silicon Table 26 1 Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Calibration Accuracy Factory Calibration 8 0 MHz 3V 25 C 10 User Calibration 7 3 8 1 MHz 1 8V 5 5V 1 2 7V 5 5V 2 40 C 85 C 1 VIL1 VIH1 Table 26 2 External Clock Drive Symbol Parameter VCC 1 8 5 5V VCC...

Page 320: ...1 and BODLEVEL 100 for ATmega48P 88P 168P 328P Table 26 3 Reset Brown out and Internal Voltage Characteristics 1 Symbol Parameter Min Typ Max Units VPOT Power on Reset Threshold Voltage rising 1 1 1 4 1 6 V Power on Reset Threshold Voltage falling 2 0 6 1 3 1 6 V SRON Power on Slope Rate 0 01 10 V ms VRST RESET Pin Threshold Voltage 0 2 VCC 0 9 VCC V tRST Minimum pulse width on RESET Pin 2 5 µs VH...

Page 321: ...ry values representing design targets and will be updated after character ization of actual silicon Table 26 5 SPI Timing Parameters Description Mode Min Typ Max 1 SCK period Master See Table 16 5 ns 2 SCK high low Master 50 duty cycle 3 Rise Fall time Master 3 6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0 5 tsck 7 SCK to out Master 10 8 SCK to out high Master 10 9 SS low to out Slave...

Page 322: ...Requirements Master Mode Figure 26 6 SPI Interface Timing Requirements Slave Mode MOSI Data Output SCK CPOL 1 MISO Data Input SCK CPOL 0 SS MSB LSB LSB MSB 6 1 2 2 3 4 5 8 7 MISO Data Output SCK CPOL 1 MOSI Data Input SCK CPOL 0 SS MSB LSB LSB MSB 10 11 11 12 13 14 17 15 9 X 16 ...

Page 323: ...om VIHmin to VILmax 10 pF Cb 400 pF 3 20 0 1Cb 3 2 250 ns tSP 1 Spikes Suppressed by Input Filter 0 50 2 ns Ii Input Current each I O Pin 0 1VCC Vi 0 9VCC 10 10 µA Ci 1 Capacitance for each I O Pin 10 pF fSCL SCL Clock Frequency fCK 4 max 16fSCL 250kHz 5 0 400 kHz Rp Value of Pull up resistor fSCL 100 kHz fSCL 100 kHz tHD STA Hold Time repeated START Condition fSCL 100 kHz 4 0 µs fSCL 100 kHz 0 6 ...

Page 324: ...quency 5 This requirement applies to all ATmega48P 88P 168P 328P 2 wire Serial Interface operation Other devices connected to the 2 wire Serial Bus need only obey the general fSCL requirement Figure 26 7 2 wire Serial Bus Timing tSU STA tLOW tHIGH tLOW tof tHD STA tHD DAT tSU DAT tSU STO tBUF SCL SDA tr ...

Page 325: ... VREF 4V VCC 4V ADC clock 1 MHz Noise Reduction Mode 4 5 LSB Integral Non Linearity INL VREF 4V VCC 4V ADC clock 200 kHz 0 5 LSB Differential Non Linearity DNL VREF 4V VCC 4V ADC clock 200 kHz 0 25 LSB Gain Error VREF 4V VCC 4V ADC clock 200 kHz 2 LSB Offset Error VREF 4V VCC 4V ADC clock 200 kHz 2 LSB Conversion Time Free Running Conversion 13 260 µs Clock Frequency 50 1000 kHz AVCC 1 Analog Supp...

Page 326: ...XTAL1 Pulse Width High 150 ns tXLDX Data and Control Hold after XTAL1 Low 67 ns tXLWL XTAL1 Low to WR Low 0 ns tXLPH XTAL1 Low to PAGEL high 0 ns tPLXH PAGEL low to XTAL1 high 150 ns tBVPH BS1 Valid before PAGEL High 67 ns tPHPL PAGEL Pulse Width High 150 ns tPLBX BS1 Hold after PAGEL Low 67 ns tWLBX BS2 1 Hold after WR Low 67 ns tPLWL PAGEL Low to WR Low 67 ns tBVWL BS1 Valid to WR Low 67 ns tWLW...

Page 327: ...te 1 The timing requirements shown in Figure 26 8 i e tDVXH tXHXL and tXLDX also apply to read ing operation Data Contol DATA XA0 1 BS1 BS2 XTAL1 tXHXL tWLWH tDVXH tXLDX tPLWL tWLRH WR RDY BSY PAGEL tPHPL tPLBX tBVPH tXLWL tWLBX tBVWL WLRL XTAL1 PAGEL tPLXH XLXH t tXLPH ADDR0 Low Byte DATA Low Byte DATA High Byte ADDR1 Low Byte DATA BS1 XA0 XA1 LOAD ADDRESS LOW BYTE LOAD DATA LOW BYTE LOAD DATA HI...

Page 328: ... by the Power Reduction Register See Power Reduction Register on page 42 for details The power consumption in Power down mode is independent of clock selection The current consumption is a function of several factors such as operating voltage operating frequency loading of I O pins switching rate of I O pins code executed and ambient tempera ture The dominating factors are operating voltage and fr...

Page 329: ... 27 2 Active Supply Current vs Frequency 1 20 MHz ACTIVE SUPPLY CURRENT vs LOW FREQUENCY 0 1 1 0 MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 2 0 4 0 6 0 8 1 1 2 1 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ACTIVE SUPPLY CURRENT vs FREQUENCY 1 20 MHz 5 5 V 5 0 V 4 5 V 0 4 8 12 16 20 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V ...

Page 330: ...vs VCC Internal RC Oscillator 1 MHz ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 128 KHz 85 C 25 C 40 C 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 0 18 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 1 MHz 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 331: ... Current vs Low Frequency 0 1 1 0 MHz ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 8 MHz 85 C 25 C 40 C 0 1 2 3 4 5 6 7 8 9 10 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA IDLE SUPPLY CURRENT vs LOW FREQUENCY 0 1 1 0 MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 0 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ...

Page 332: ...t vs VCC Internal RC Oscillator 128 kHz IDLE SUPPLY CURRENT vs FREQUENCY 1 20 MHz 5 5 V 5 0 V 4 5 V 0 1 2 3 4 5 6 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8V 2 7V 3 3V 4 0V IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 128 KHz 85 C 25 C 40 C 0 0 01 0 02 0 03 0 04 0 05 0 06 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 333: ...upply Current vs Vcc Internal RC Oscillator 8 MHz IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 1 MHz 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 8 MHz 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 334: ...page 331 we find that the idle current consumption is 0 055 mA at VCC 2 0V and F 1MHz The total current consumption in idle mode with TIMER1 ADC and SPI enabled gives Table 27 1 Additional Current Consumption for the different I O modules absolute values PRR bit Typical numbers VCC 2V F 1MHz VCC 3V F 4MHz VCC 5V F 8MHz PRUSART0 5 58 uA 35 6 uA 136 5 uA PRTWI 8 97 uA 57 0 uA 231 5 uA PRTIM2 9 84 uA...

Page 335: ...re 27 12 Power Down Supply Current vs VCC Watchdog Timer Enabled POWER DOWN SUPPLY CURRENT vs VCC WATCHDOG TIMER DISABLED 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA POWER DOWN SUPPLY CURRENT vs VCC WATCHDOG TIMER ENABLED 85 C 25 C 40 C 0 2 4 6 8 10 12 14 16 18 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 336: ...y Current vs Vcc Watchdog Timer Disabled POWER SAVE SUPPLY CURRENT vs VCC WATCHDOG TIMER DISABLED and 32 kHz CRYSTAL OSCILLATOR RUNNING 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 3 2 8 3 3 3 8 4 3 4 8 5 3 5 8 VCC V I CC uA 25 C STANDBY SUPPLY CURRENT vs VCC WATCHDOG TIMER DISABLED 6MHz_xtal 6MHz_res 4MHz_xtal 4MHz_res 450kHz_res 2MHz_xtal 2MHz_res 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 0 18 0 2 1 8 2...

Page 337: ...e 27 16 I O Pin Pull up Resistor Current vs Input Voltage VCC 2 7 V I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE Vcc 1 8 V 0 10 20 30 40 50 60 70 80 90 0 0 5 1 1 5 2 2 5 3 VOP V I OP uA 85 C 25 C 40 C I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE Vcc 2 7 V 0 10 20 30 40 50 60 70 80 90 0 0 5 1 1 5 2 2 5 3 VOP V I OP uA 85 C 25 C 40 C ...

Page 338: ...Resistor Current vs Reset Pin Voltage VCC 1 8 V I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE Vcc 5 V 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 VOP V I OP uA 85 C 25 C 40 C RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE VCC 1 8 V 85 C 25 C 40 C 5 0 5 10 15 20 25 30 35 40 45 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 VRESET V I RESET uA ...

Page 339: ...et Pull up Resistor Current vs Reset Pin Voltage VCC 5 V RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE VCC 2 7 V 85 C 25 C 40 C 10 0 10 20 30 40 50 60 70 0 0 5 1 1 5 2 2 5 3 VRESET V I RESET uA RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE VCC 5 V 85 C 25 C 40 C 20 0 20 40 60 80 100 120 140 0 1 2 3 4 5 6 VRESET V I RESET uA ...

Page 340: ...k Current VCC 3 V Figure 27 22 I O Pin Output Voltage vs Sink Current VCC 5 V I O PIN OUTPUT VOLTAGE vs SINK CURRENT VCC 3 V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 IOL mA V OL V I O PIN OUTPUT VOLTAGE vs SINK CURRENT VCC 5 V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 5 10 15 20 25 IOL mA V OL V ...

Page 341: ...Figure 27 24 I O Pin Output Voltage vs Source Current VCC 5 V I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT VCC 3 V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 0 5 10 15 20 25 IOH mA V OH V I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT VCC 5 V 85 C 25 C 40 C 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 5 1 0 5 10 15 20 25 IOH mA V OH V ...

Page 342: ... Figure 27 26 I O Pin Input Threshold Voltage vs VCC VIL I O Pin read as 0 I O PIN INPUT THRESHOLD VOLTAGE vs VCC VIH IO PIN READ AS 1 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V I O PIN INPUT THRESHOLD VOLTAGE vs VCC VIL IO PIN READ AS 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 343: ...ut Threshold Voltage vs VCC VIH I O Pin read as 1 I O PIN INPUT HYSTERESIS vs VCC 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis mV RESET INPUT THRESHOLD VOLTAGE vs VCC VIH IO PIN READ AS 1 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 344: ... Figure 27 30 Reset Pin Input Hysteresis vs VCC RESET INPUT THRESHOLD VOLTAGE vs VCC VIL IO PIN READ AS 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V RESET PIN INPUT HYSTERESIS vs VCC 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis mV ...

Page 345: ...ODLEVEL is 2 7 V BOD THRESHOLDS vs TEMPERATURE Vcc 1 8 V 1 7 1 72 1 74 1 76 1 78 1 8 1 82 1 84 1 86 1 88 1 9 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature C Threshold V Rising Vcc Falling Vcc BOD THRESHOLDS vs TEMPERATURE Vcc 2 7 V 2 6 2 65 2 7 2 75 2 8 2 85 2 9 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature C Threshold V Rising Vcc Falling Vcc ...

Page 346: ...equency vs Temperature BOD THRESHOLDS vs TEMPERATURE Vcc 4 3V 4 2 4 25 4 3 4 35 4 4 4 45 4 5 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature C Threshold V Rising Vcc Falling Vcc WATCHDOG OSCILLATOR FREQUENCY vs TEMPERATURE 5 5 V 4 5 V 4 0 V 3 3 V 2 7 V 103 104 105 106 107 108 109 110 111 112 113 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature F RC kHz ...

Page 347: ...ated 8 MHz RC Oscillator Frequency vs VCC WATCHDOG OSCILLATOR FREQUENCY vs VCC 85 C 25 C 40 C 103 104 105 106 107 108 109 110 111 112 113 114 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC kHz CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs VCC 85 C 25 C 40 C 7 6 7 7 7 8 7 9 8 8 1 8 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC MHz ...

Page 348: ...uency vs OSCCAL Value CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs TEMPERATURE 5 0 V 3 0 V 7 8 7 85 7 9 7 95 8 8 05 8 1 8 15 8 2 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature F RC MHz CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs OSCCAL VALUE 85 C 25 C 40 C 0 2 4 6 8 10 12 14 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL X1 F RC MHz ...

Page 349: ...urrent vs VCC AREF AVCC Figure 27 40 Analog Comparator Current vs VCC ADC CURRENT vs VCC AREF AVCC 85 C 25 C 40 C 0 50 100 150 200 250 300 350 400 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ANALOG COMPARATOR CURRENT vs VCC 85 C 25 C 40 C 0 10 20 30 40 50 60 70 80 90 100 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 350: ... VCC Figure 27 42 Brownout Detector Current vs VCC AREF EXTERNAL REFERENCE CURRENT vs VCC 85 C 25 C 40 C 0 20 40 60 80 100 120 140 160 180 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA BROWNOUT DETECTOR CURRENT vs VCC 85 C 25 C 40 C 0 10 20 30 40 50 60 70 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 351: ...idth Figure 27 44 Reset Supply Current vs Low Frequency 0 1 1 0 MHz PROGRAMMING CURRENT vs VCC 85 C 25 C 40 C 0 1 2 3 4 5 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA RESET SUPPLY CURRENT vs LOW FREQUENCY 0 1 1 0 MHz 5 5 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 05 0 1 0 15 0 2 0 25 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ...

Page 352: ...Reset Pulse width vs VCC RESET SUPPLY CURRENT vs FREQUENCY 1 20 MHz 5 5 V 4 5 V 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 4 0 V 3 3 V 2 7 V 1 8 V MINIMUM RESET PULSE WIDTH vs VCC 85 C 25 C 40 C 0 200 400 600 800 1000 1200 1400 1600 1800 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Pulsewidth ns ...

Page 353: ...re 27 48 Active Supply Current vs Frequency 1 20 MHz ACTIVE SUPPLY CURRENT vs LOW FREQUENCY 0 1 1 0 MHz 5 5 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 2 0 4 0 6 0 8 1 1 2 1 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ACTIVE SUPPLY CURRENT vs FREQUENCY 1 20 MHz 5 5 V 4 5 V 0 2 4 6 8 10 12 14 16 18 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 4 V 3 3 V 2 7 V 1 8 V ...

Page 354: ...ply Current vs VCC Internal RC Oscillator 1 MHz ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 128 KHz 85 C 25 C 40 C 0 0 05 0 1 0 15 0 2 0 25 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 1 MHz 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 355: ... Supply Current vs Low Frequency 0 1 1 0 MHz ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 8 MHz 85 C 25 C 40 C 0 1 2 3 4 5 6 7 8 9 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA IDLE SUPPLY CURRENT vs LOW FREQUENCY 0 1 1 0 MHz 5 5 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ...

Page 356: ...C Oscillator 128 kHz IDLE SUPPLY CURRENT vs FREQUENCY 1 20 MHz 5 5 V 4 5 V 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 4 V 3 3 V 2 7 V 1 8 V IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 128 KHz 85 C 25 C 40 C 0 0 005 0 01 0 015 0 02 0 025 0 03 0 035 0 04 0 045 0 05 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 357: ...Idle Supply Current vs Vcc Internal RC Oscillator 8 MHz IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 1 MHz 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 8 MHz 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 358: ...age 355 we find that the idle current consumption is 0 055 mA at VCC 2 0V and F 1MHz The total current consumption in idle mode with TIMER1 ADC and SPI enabled gives Table 27 3 Additional Current Consumption for the different I O modules absolute values PRR bit Typical numbers VCC 2V F 1MHz VCC 3V F 4MHz VCC 5V F 8MHz PRUSART0 4 12 uA 26 7 uA 108 3 uA PRTWI 8 96 uA 58 6 uA 238 2 uA PRTIM2 9 94 uA ...

Page 359: ...gure 27 58 Power Down Supply Current vs VCC Watchdog Timer Enabled POWER DOWN SUPPLY CURRENT vs VCC WATCHDOG TIMER DISABLED 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA POWER DOWN SUPPLY CURRENT vs VCC WATCHDOG TIMER ENABLED 85 C 25 C 40 C 0 1 2 3 4 5 6 7 8 9 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 360: ...Supply Current vs Vcc Watchdog Timer Disabled 1 6 1 4 1 2 1 0 0 8 0 6 0 4 0 2 VCC V I CC u A 2 5 3 0 3 5 4 0 4 5 5 0 5 5 1 5 2 0 POWER SAVE SUPPLY CURRENT vs VCC WATCHDOG TIMER DISABLED and 32 kHz CRYSTAL OSCILLATOR RUNNING 25 C STANDBY SUPPLY CURRENT vs VCC WATCHDOG TIMER DISABLED 6MHz_xtal 6MHz_res 4MHz_xtal 4MHz_res 450kHz_res 2MHz_xtal 2MHz_res 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 0 18 1 5...

Page 361: ...7 62 I O Pin Pull up Resistor Current vs Input Voltage VCC 2 7 V I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE 0 10 20 30 40 50 60 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 VOP V I OP uA 85 C 25 C 40 C VCC 1 8 V I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE 0 10 20 30 40 50 60 70 80 0 0 5 1 1 5 2 2 5 3 VOP V I OP uA 85 C 25 C 40 C VCC 2 7 V ...

Page 362: ...up Resistor Current vs Reset Pin Voltage VCC 1 8 V 85 C 25 C 40 C I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 VOP V I OP uA VCC 5 V RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE VCC 1 8 V 0 5 10 15 20 25 30 35 40 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 VRESET V I RESET uA 85 C 25 C 40 C ...

Page 363: ...t Pull up Resistor Current vs Reset Pin Voltage VCC 5 V RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE VCC 2 7 V 0 10 20 30 40 50 60 70 0 0 5 1 1 5 2 2 5 3 VRESET V I RESET uA 85 C 25 C 40 C I RESET uA RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE VCC 5 V 0 20 40 60 80 100 120 0 1 2 3 4 5 6 VRESET V I RESET uA 85 C 25 C 40 C ...

Page 364: ...t VCC 3 V Figure 27 68 I O Pin Output Voltage vs Sink Current VCC 5 V I O PIN OUTPUT VOLTAGE vs SINK CURRENT VCC 3 V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 5 10 15 20 25 IOL mA V OL V I O PIN OUTPUT VOLTAGE vs SINK CURRENT VCC 5 V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 5 10 15 20 25 IOL mA V OL V ...

Page 365: ...gure 27 70 I O Pin Output Voltage vs Source Current VCC 5 V I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT VCC 3 V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 0 4 8 12 16 20 IOH mA V OH V I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT VCC 5 V 85 C 25 C 40 C 4 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 10 15 20 25 IOH mA V OH V ...

Page 366: ...7 72 I O Pin Input Threshold Voltage vs VCC VIL I O Pin read as 0 Input I O PIN INPUT THRESHOLD VOLTAGE vs VCC VIH IO PIN READ AS 1 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 4 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V I O PIN INPUT THRESHOLD VOLTAGE vs VCC VIL IO PIN READ AS 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Threshold V ...

Page 367: ...ut Threshold Voltage vs VCC VIH I O Pin read as 1 I O PIN INPUT HYSTERESIS vs VCC 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis mV RESET INPUT THRESHOLD VOLTAGE vs VCC VIH IO PIN READ AS 1 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 368: ... 0 Figure 27 76 Reset Pin Input Hysteresis vs VCC RESET INPUT THRESHOLD VOLTAGE vs VCC VIL IO PIN READ AS 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V RESET PIN INPUT HYSTERESIS vs VCC 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis mV ...

Page 369: ... BODLEVEL is 2 7 V BOD THRESHOLDS vs TEMPERATURE BODLEVEL IS 1 8 V Rising Vcc Falling Vcc 1 5 1 6 1 7 1 8 1 9 2 2 1 2 2 2 3 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature C Threshold V BOD THRESHOLDS vs TEMPERATURE Rising Vcc Falling Vcc 2 5 2 55 2 6 2 65 2 7 2 75 2 8 2 85 2 9 2 95 3 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature C Threshold V ...

Page 370: ...y vs Temperature BOD THRESHOLDS vs TEMPERATURE BODLEVEL IS 4 3 V Rising Vcc Falling Vcc 4 4 05 4 1 4 15 4 2 4 25 4 3 4 35 4 4 4 45 4 5 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature C Threshold V 5 5 V 4 0 V 3 3 V 2 7 V WATCHDOG OSCILLATOR FREQUENCY vs TEMPERATURE 92 94 96 98 100 102 104 106 108 110 112 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature F RC kHz ...

Page 371: ...librated 8 MHz RC Oscillator Frequency vs VCC WATCHDOG OSCILLATOR FREQUENCY vs VCC 85 C 25 C 40 C 102 103 104 105 106 107 108 109 110 111 112 2 5 3 3 5 4 4 5 5 VCC V F RC kHz CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs VCC 85 C 25 C 40 C 7 6 7 7 7 8 7 9 8 8 1 8 2 8 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC MHz ...

Page 372: ...Frequency vs OSCCAL Value CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs TEMPERATURE 5 0 V 3 0 V 7 6 7 7 7 8 7 9 8 8 1 8 2 8 3 8 4 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Temperature F RC MHz CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs OSCCAL VALUE 85 C 25 C 40 C 0 2 4 6 8 10 12 14 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL X1 F RC MHz ...

Page 373: ...urrent vs VCC AREF AVCC Figure 27 86 Analog Comparator Current vs VCC ADC CURRENT vs Vcc AREF AVCC 85 C 25 C 40 C 0 50 100 150 200 250 300 350 400 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ANALOG COMPARATOR CURRENT vs VCC 85 C 25 C 40 C 0 10 20 30 40 50 60 70 80 90 100 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 374: ...C Figure 27 88 Brownout Detector Current vs VCC AREF EXTERNAL REFERENCE CURRENT vs VCC 85 C 25 C 40 C 0 20 40 60 80 100 120 140 160 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA BROWNOUT DETECTOR CURRENT vs VCC 85 C 25 C 40 C 0 10 20 30 40 50 60 70 80 90 100 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 375: ...gure 27 90 Reset Supply Current vs Low Frequency 0 1 1 0 MHz PROGRAMMING CURRENT vs VCC 85 C 25 C 40 C 0 2 4 6 8 10 12 14 16 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA RESET SUPPLY CURRENT vs LOW FREQUENCY 0 1 1 0 MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 05 0 1 0 15 0 2 0 25 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ...

Page 376: ... Reset Pulse width vs VCC RESET SUPPLY CURRENT vs FREQUENCY 1 20 MHz 5 5 V 4 5 V 0 0 5 1 1 5 2 2 5 3 3 5 4 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 4 V 3 3 V 2 7 V 1 8 V MINIMUM RESET PULSE WIDTH vs VCC 85 C 25 C 40 C 0 200 400 600 800 1000 1200 1400 1600 1800 2000 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Pulsewidth ns ...

Page 377: ...Figure 27 94 Active Supply Current vs Frequency 1 20 MHz ACTIVE SUPPLY CURRENT vs LOW FREQUENCY 0 1 1 0 MHz 5 5 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 2 0 4 0 6 0 8 1 1 2 1 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ACTIVE SUPPLY CURRENT vs FREQUENCY 1 20 MHz 5 5 V 4 5 V 0 5 10 15 20 25 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 4 0 V 3 3 V 2 7 V 1 8 V ...

Page 378: ...t vs VCC Internal RC Oscillator 1 MHz ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 128 KHz 85 C 25 C 40 C 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 0 18 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 1 MHz 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 379: ... Supply Current vs Low Frequency 0 1 1 0 MHz ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 8 MHz 85 C 25 C 40 C 0 1 2 3 4 5 6 7 8 9 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA IDLE SUPPLY CURRENT vs LOW FREQUENCY 0 1 1 0 MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 05 0 1 0 15 0 2 0 25 0 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ...

Page 380: ...scillator 128 kHz IDLE SUPPLY CURRENT vs FREQUENCY 1 20 MHz 5 5 V 5 0 V 4 5 V 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 4 0 V 3 3 V 2 7 V 1 8 V IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 128 KHz 85 C 25 C 40 C 0 0 005 0 01 0 015 0 02 0 025 0 03 0 035 0 04 0 045 0 05 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 381: ...ly Current vs Vcc Internal RC Oscillator 8 MHz IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 1 MHz 85 C 25 C 40 C 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 0 4 0 45 0 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 8 MHz 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 382: ...age 379 we find that the idle current consumption is 0 055 mA at VCC 2 0V and F 1MHz The total current consumption in idle mode with TIMER1 ADC and SPI enabled gives Table 27 5 Additional Current Consumption for the different I O modules absolute values PRR bit Typical numbers VCC 2V F 1MHz VCC 3V F 4MHz VCC 5V F 8MHz PRUSART0 5 54 uA 34 8 uA 133 9 uA PRTWI 10 1 uA 63 1 uA 250 6 uA PRTIM2 10 4 uA ...

Page 383: ... Figure 27 104 Power Down Supply Current vs VCC Watchdog Timer Enabled POWER DOWN SUPPLY CURRENT vs VCC WATCHDOG TIMER DISABLED 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA POWER DOWN SUPPLY CURRENT vs VCC WATCHDOG TIMER ENABLED 85 C 25 C 40 C 0 1 2 3 4 5 6 7 8 9 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 384: ...by Supply Current vs Vcc Watchdog Timer Disabled POWER SAVE SUPPLY CURRENT vs VCC WATCHDOG TIMER DISABLED and 32 kHz CRYSTAL OSCILLATOR RUNNING 0 0 2 0 4 0 6 0 8 1 0 1 2 1 4 1 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 25 C STANDBY SUPPLY CURRENT vs VCC WATCHDOG TIMER DISABLED 6MHz_xtal 6MHz_res 4MHz_xtal 4MHz_res 2MHz_xtal 2MHz_res 1MHz_res 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 0 18 0 2 1 5 2...

Page 385: ... 108 I O Pin Pull up Resistor Current vs Input Voltage VCC 2 7 V I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE VCC 1 8V 85 C 25 C 40 C 0 10 20 30 40 50 60 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 VOP V I OP uA I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE VCC 2 7V 85 C 25 C 40 C 0 10 20 30 40 50 60 70 80 90 0 0 5 1 1 5 2 2 5 3 VOP V I OP uA ...

Page 386: ...l up Resistor Current vs Reset Pin Voltage VCC 1 8 V I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE VCC 5V 85 C 25 C 40 C 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 VOP V I OP uA RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE VCC 1 8V 25 C 85 C 40 C 0 5 10 15 20 25 30 35 40 0 0 2 0 4 0 8 1 1 2 1 4 1 6 1 8 2 VRESET V I RESET uA 0 6 ...

Page 387: ...112 Reset Pull up Resistor Current vs Reset Pin Voltage VCC 5 V RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE VCC 2 7V 40 C 25 C 85 C 0 10 20 30 40 50 60 70 0 0 5 1 1 5 2 2 5 3 VRESET V I RESET uA RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE VCC 5V 85 C 25 C 40 C 0 20 40 60 80 100 120 0 1 2 3 4 5 6 VRESET V I RESET uA ...

Page 388: ...t VCC 3 V Figure 27 114 I O Pin Output Voltage vs Sink Current VCC 5 V I O PIN OUTPUT VOLTAGE vs SINK CURRENT VCC 3V 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 0 5 10 15 20 25 IOL mA V OL V I O PIN OUTPUT VOLTAGE vs SINK CURRENT VCC 5V NORMAL POWER PINS 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 5 10 15 20 25 IOL mA V OL V ...

Page 389: ...in Output Voltage vs Source Current VCC 5 V I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT VCC 3V NORMAL POWER PINS 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 0 5 10 15 20 25 IOH mA V OH V I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT VCC 5V NORMAL POWER PINS 85 C 25 C 40 C 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 5 1 0 5 10 15 20 25 IOH mA V OH V ...

Page 390: ...igure 27 118 I O Pin Input Threshold Voltage vs VCC VIL I O Pin read as 0 I O PIN INPUT THRESHOLD VOLTAGE vs VCC VIH IO PIN READ AS 1 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V I O PIN INPUT THRESHOLD VOLTAGE vs VCC VIL IO PIN READ AS 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 391: ...put Threshold Voltage vs VCC VIH I O Pin read as 1 I O PIN INPUT HYSTERESIS vs VCC 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis mV RESET INPUT THRESHOLD VOLTAGE vs VCC VIH IO PIN READ AS 1 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 392: ... 0 Figure 27 122 Reset Pin Input Hysteresis vs VCC RESET INPUT THRESHOLD VOLTAGE vs VCC VIL IO PIN READ AS 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V RESET PIN INPUT HYSTERESIS vs VCC 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis mV ...

Page 393: ...L is 2 7 V BOD THRESHOLDS vs TEMPERATURE Vcc 1 8V 1 7 1 72 1 74 1 76 1 78 1 8 1 82 1 84 1 86 1 88 1 9 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature C Threshold V Rising Vcc Falling Vcc BOD THRESHOLDS vs TEMPERATURE Vcc 2 7V 2 5 2 55 2 6 2 65 2 7 2 75 2 8 2 85 2 9 2 95 3 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature C Threshold V Rising Vcc Falling Vcc ...

Page 394: ...tor Frequency vs Temperature BOD THRESHOLDS vs TEMPERATURE Vcc 4 3V 4 4 05 4 1 4 15 4 2 4 25 4 3 4 35 4 4 4 45 4 5 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature C Threshold V Rising Vcc Falling Vcc WATCHDOG OSCILLATOR FREQUENCY vs TEMPERATURE 5 0 V 3 3 V 2 7 V 104 106 108 110 112 114 116 118 120 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature F RC kHz ...

Page 395: ...rated 8 MHz RC Oscillator Frequency vs VCC WATCHDOG OSCILLATOR FREQUENCY vs VCC 85 C 25 C 109 110 111 112 113 114 115 116 117 118 119 120 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC kHz CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs OPERATING VOLTAGE 85 C 25 C 7 8 7 85 7 9 7 95 8 8 05 8 1 2 2 5 3 3 5 4 4 5 5 5 5 V F RC MHz ...

Page 396: ...llator Frequency vs OSCCAL Value CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs TEMPERATURE 5 5 V 2 7 V 1 8 V 7 8 7 85 7 9 7 95 8 8 05 8 1 8 15 0 10 20 30 40 50 60 70 80 90 100 Temperature F RC MHz CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs OSCCAL VALUE 85 C 25 C 0 2 4 6 8 10 12 14 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL X1 F RC MHz ...

Page 397: ...1 ADC Current vs VCC AREF AVCC Figure 27 132 Analog Comparator Current vs VCC ADC CURRENT vs VCC AREF AVCC 85 C 25 C 40 C 100 150 200 250 300 350 400 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ANALOG COMPARATOR CURRENT vs VCC 85 C 25 C 40 C 25 35 45 55 65 75 85 95 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 398: ...ure 27 134 Brownout Detector Current vs VCC AREF CURRENT EXTERNAL REFERENCE CURRENT vs VCC 85 C 25 C 40 C 0 20 40 60 80 100 120 140 160 180 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA BROWNOUT DETECTOR CURRENT vs VCC 85 C 25 C 40 C 10 12 14 16 18 20 22 24 26 28 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 399: ...7 136 Reset Supply Current vs Low Frequency 0 1 1 0 MHz PROGRAMMING CURRENT vs Vcc 85 C 25 C 40 C 0 2 4 6 8 10 12 14 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA RESET SUPPLY CURRENT vs VCC 0 1 1 0 MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 0 18 0 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ...

Page 400: ...Reset Pulse width vs VCC RESET SUPPLY CURRENT vs FREQUENCY 1 20 MHz 5 5 V 5 0 V 4 5 V 0 0 5 1 1 5 2 2 5 3 3 5 4 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 4 0 V 3 3 V 2 7 V 1 8 V MINIMUM RESET PULSE WIDTH vs VCC 85 C 25 C 40 C 0 200 400 600 800 1000 1200 1400 1600 1800 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Pulsewidth ns ...

Page 401: ... 27 140 Active Supply Current vs Frequency 1 20 MHz ACTIVE SUPPLY CURRENT vs LOW FREQUENCY 0 1 1 0 MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 2 0 4 0 6 0 8 1 1 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ACTIVE SUPPLY CURRENT vs FREQUENCY 1 20 MHz 5 5 V 5 0 V 4 5 V 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V ...

Page 402: ...ive Supply Current vs VCC Internal RC Oscillator 1 MHz ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 128 kHz 85 C 25 C 40 C 0 0 04 0 08 0 12 0 16 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 1 MHz 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 403: ...dle Supply Current vs Low Frequency 0 1 1 0 MHz ACTIVE SUPPLY CURRENT vs V CC INTERNAL RC OSCILLATOR 8 MHz 85 C 25 C 40 C 0 1 2 3 4 5 6 7 8 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA IDLE SUPPLY CURRENT vs LOW FREQUENCY 0 1 1 0 MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 04 0 08 0 12 0 16 0 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ...

Page 404: ...CC Internal RC Oscillator 128 kHz IDLE SUPPLY CURRENT vs FREQUENCY 1 20 MHz 5 5 V 5 0 V 4 5 V 0 0 5 1 1 5 2 2 5 3 3 5 4 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 128 KHz 85 C 25 C 40 C 0 0 01 0 02 0 03 0 04 0 05 0 06 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 405: ...Supply Current vs Vcc Internal RC Oscillator 8 MHz IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 1 MHz 85 C 25 C 40 C 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 0 4 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 8 MHz 85 C 25 C 40 C 0 0 4 0 8 1 2 1 6 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA ...

Page 406: ...e find that the idle current consumption is 0 055 mA at VCC 2 0V and F 1MHz The total current consumption in idle mode with TIMER1 ADC and SPI enabled gives Table 27 7 Additional Current Consumption for the different I O modules absolute values PRR bit Typical numbers VCC 2V F 1MHz VCC 3V F 4MHz VCC 5V F 8MHz PRUSART0 3 20 µA 22 17 µA 100 25 µA PRTWI 7 34 µA 46 55 µA 199 25 µA PRTIM2 7 34 µA 50 79...

Page 407: ...ed Figure 27 150 Power Down Supply Current vs VCC Watchdog Timer Enabled POWER DOWN SUPPLY CURRENT vs VCC WATCHDOG TIMER DISABLED 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 1 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA POWER DOWN SUPPLY CURRENT vs VCC WATCHDOG TIMER ENABLED 85 C 25 C 40 C 0 1 2 3 4 5 6 7 8 9 10 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 408: ...andby Supply Current vs Vcc Watchdog Timer Disabled POWER SAVE SUPPLY CURRENT vs VCC WATCHDOG TIMER ENABLED and 32 kHz CRYSTAL OSCILLATOR RUNNING 25 C 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA STANDBY SUPPLY CURRENT vs VCC WATCHDOG TIMER DISABLED 6MHz_xtal 6MHz_res 4MHz_xtal 4MHz_res 2MHz_xtal 2MHz_res 1MHz_res 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 1 5 2 2 ...

Page 409: ... 154 I O Pin Pull up Resistor Current vs Input Voltage VCC 2 7 V I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE VCC 1 8V 85 C 25 C 40 C 0 10 20 30 40 50 60 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 VOP V I OP uA I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE VCC 2 7V 85 C 25 C 40 C 0 10 20 30 40 50 60 70 80 90 0 0 5 1 1 5 2 2 5 3 VOP V I OP uA ...

Page 410: ...l up Resistor Current vs Reset Pin Voltage VCC 1 8 V I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE VCC 5V 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 VOP V I OP uA 85 C 25 C 40 C RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE VCC 1 8V 0 5 10 15 20 25 30 35 40 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 VRESET V I RESET uA 85 C 25 C 40 C ...

Page 411: ...158 Reset Pull up Resistor Current vs Reset Pin Voltage VCC 5 V RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE VCC 2 7V 0 10 20 30 40 50 60 70 0 0 5 1 1 5 2 2 5 3 VRESET V I RESET uA 85 C 25 C 40 C RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE VCC 5V 0 20 40 60 80 100 120 0 1 2 3 4 5 6 VRESET V I RESET uA 85 C 25 C 40 C ...

Page 412: ...s Sink Current VCC 3 V Figure 27 160 I O Pin Output Voltage vs Sink Current VCC 5 V I O PIN OUTPUT VOLTAGE vs SINK CURRENT VCC 3V 85 C 25 C 40 C 0 0 2 0 4 0 6 0 8 1 0 5 10 15 20 25 IOL mA V OL V I O PIN OUTPUT VOLTAGE vs SINK CURRENT VCC 5V 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 5 10 15 20 25 IOL mA V OL V ...

Page 413: ... Figure 27 162 I O Pin Output Voltage vs Source Current VCC 5 V I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT VCC 3V 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 0 5 10 15 20 25 IOH mA V OH V I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT VCC 5V 85 C 25 C 40 C 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 5 1 0 5 10 15 20 25 IOH mA V OH V ...

Page 414: ...gure 27 164 I O Pin Input Threshold Voltage vs VCC VIL I O Pin read as 0 I O PIN INPUT THRESHOLD VOLTAGE vs VCC VIH IO PIN READ AS 1 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 4 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V I O PIN INPUT THRESHOLD VOLTAGE vs VCC VIL IO PIN READ AS 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 415: ...t Threshold Voltage vs VCC VIH I O Pin read as 1 I O PIN INPUT HYSTERESIS vs VCC 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis mV RESET INPUT THRESHOLD VOLTAGE vs VCC VIH IO PIN READ AS 1 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V ...

Page 416: ... Figure 27 168 Reset Pin Input Hysteresis vs VCC RESET INPUT THRESHOLD VOLTAGE vs VCC VIL IO PIN READ AS 0 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V RESET PIN INPUT HYSTERESIS vs VCC 85 C 25 C 40 C 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Input Hysteresis mV ...

Page 417: ...1 8 V Figure 27 170 BOD Thresholds vs Temperature BODLEVEL is 2 7 V BOD THRESHOLDS vs TEMPERATURE VCC 1 8V 1 0 1 75 1 77 1 79 1 81 1 83 1 85 60 40 20 0 20 40 60 80 100 Temperature C Threshold V BOD THRESHOLDS vs TEMPERATURE VCC 2 7V 1 0 2 66 2 68 2 7 2 72 2 74 2 76 2 78 60 40 20 0 20 40 60 80 100 Temperature C Threshold V ...

Page 418: ...peed Figure 27 172 Watchdog Oscillator Frequency vs Temperature BOD THRESHOLDS vs TEMPERATURE VCC 4 3V 1 0 4 25 4 3 4 35 4 4 60 40 20 0 20 40 60 80 100 Temperature C Threshold V WATCHDOG OSCILLATOR FREQUENCY vs TEMPERATURE 5 5 V 4 0 V 3 3 V 2 7 V 109 110 111 112 113 114 115 116 117 118 119 60 40 20 0 20 40 60 80 100 Temperature F RC kHz ...

Page 419: ...7 174 Calibrated 8 MHz RC Oscillator Frequency vs VCC 85 C 25 C 40 C 1 5 2 2 5 3 3 5 4 4 5 5 5 5 V F RC kHz WATCHDOG OSCILLATOR FREQUENCY vs VCC 108 110 112 114 116 118 120 VCC CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs VCC 85 C 25 C 40 C 7 4 7 6 7 8 8 8 2 8 4 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC MHz ...

Page 420: ...uency vs OSCCAL Value CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs TEMPERATURE 5 0 V 3 0 V 7 6 7 7 7 8 7 9 8 8 1 8 2 8 3 8 4 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature F RC MHz CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs OSCCAL VALUE 85 C 25 C 40 C 0 2 4 6 8 10 12 14 16 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL X1 F RC MHz ...

Page 421: ...77 ADC Current vs VCC AREF AVCC Figure 27 178 Analog Comparator Current vs VCC ADC CURRENT vs VCC AREF AVCC 85 C 25 C 40 C 0 50 100 150 200 250 300 350 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ANALOG COMPARATOR CURRENT vs VCC 85 C 25 C 40 C 0 20 40 60 80 100 120 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 422: ...vs VCC Figure 27 180 Brownout Detector Current vs VCC AREF EXTERNAL REFERENCE CURRENT vs VCC 85 C 25 C 40 C 0 20 40 60 80 100 120 140 160 180 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA BROWNOUT DETECTOR CURRENT vs VCC 85 C 25 C 40 C 0 5 10 15 20 25 30 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 423: ...h Figure 27 182 Reset Supply Current vs Low Frequency 0 1 1 0 MHz PROGRAMMING CURRENT vs Vcc 85 C 25 C 40 C 0 1 2 3 4 5 6 7 8 9 10 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA RESET SUPPLY CURRENT vs LOW FREQUENCY 0 1 1 0 MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 05 0 1 0 15 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA ...

Page 424: ...um Reset Pulse width vs VCC RESET SUPPLY CURRENT vs FREQUENCY 1 20 MHz 5 5 V 5 0 V 4 5 V 0 0 5 1 1 5 2 2 5 3 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 1 8 V 2 7 V 3 3 V 4 0 V MINIMUM RESET PULSE WIDTH vs VCC 85 C 25 C 40 C 0 200 400 600 800 1000 1200 1400 1600 1800 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Pulsewidth ns ...

Page 425: ... 0xE6 Reserved 0xE5 Reserved 0xE4 Reserved 0xE3 Reserved 0xE2 Reserved 0xE1 Reserved 0xE0 Reserved 0xDF Reserved 0xDE Reserved 0xDD Reserved 0xDC Reserved 0xDB Reserved 0xDA Reserved 0xD9 Reserved 0xD8 Reserved 0xD7 Reserved 0xD6 Reserved 0xD5 Reserved 0xD4 Reserved 0xD3 Reserved 0xD2 Reserved 0xD1 Reserved 0xD0 Reserved 0xCF Reserved 0xCE Reserved 0xCD Reserved 0xCC Reserved 0xCB Reserved 0xCA Re...

Page 426: ...ed 0xA9 Reserved 0xA8 Reserved 0xA7 Reserved 0xA6 Reserved 0xA5 Reserved 0xA4 Reserved 0xA3 Reserved 0xA2 Reserved 0xA1 Reserved 0xA0 Reserved 0x9F Reserved 0x9E Reserved 0x9D Reserved 0x9C Reserved 0x9B Reserved 0x9A Reserved 0x99 Reserved 0x98 Reserved 0x97 Reserved 0x96 Reserved 0x95 Reserved 0x94 Reserved 0x93 Reserved 0x92 Reserved 0x91 Reserved 0x90 Reserved 0x8F Reserved 0x8E Reserved 0x8D ...

Page 427: ... C 9 0x3E 0x5E SPH SP10 5 SP9 SP8 12 0x3D 0x5D SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 12 0x3C 0x5C Reserved 0x3B 0x5B Reserved 0x3A 0x5A Reserved 0x39 0x59 Reserved 0x38 0x58 Reserved 0x37 0x57 SPMCSR SPMIE RWWSB 5 RWWSRE 5 BLBSET PGWRT PGERS SELFPRGEN 292 0x36 0x56 Reserved 0x35 0x55 MCUCR BODS BODSE PUD IVSEL IVCE 44 68 92 0x34 0x54 MCUSR WDRF BORF EXTRF PORF 54 0x33 0x53 SMCR SM2 SM1 SM0 SE 40 0x3...

Page 428: ...nstructions For the Extended I O space from 0x60 0xFF in SRAM only the ST STS STD and LD LDS LDD instructions can be used 5 Only valid for ATmega88P 168P 0x1D 0x3D EIMSK INT1 INT0 72 0x1C 0x3C EIFR INTF1 INTF0 72 0x1B 0x3B PCIFR PCIF2 PCIF1 PCIF0 0x1A 0x3A Reserved 0x19 0x39 Reserved 0x18 0x38 Reserved 0x17 0x37 TIFR2 OCF2B OCF2A TOV2 163 0x16 0x36 TIFR1 ICF1 OCF1B OCF1A TOV1 140 0x15 0x35 TIFR0 O...

Page 429: ...irect Jump to Z PC Z None 2 JMP 1 k Direct Jump PC k None 3 RCALL k Relative Subroutine Call PC PC k 1 None 3 ICALL Indirect Call to Z PC Z None 3 CALL 1 k Direct Subroutine Call PC k None 4 RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK I 4 CPSE Rd Rr Compare Skip if Equal if Rd Rr PC PC 2 or 3 None 1 2 3 CP Rd Rr Compare Rd Rr Z N V C H 1 CPC Rd Rr Compare with Carry Rd Rr ...

Page 430: ...tween Registers Rd Rr None 1 MOVW Rd Rr Copy Register Word Rd 1 Rd Rr 1 Rr None 1 LDI Rd K Load Immediate Rd K None 1 LD Rd X Load Indirect Rd X None 2 LD Rd X Load Indirect and Post Inc Rd X X X 1 None 2 LD Rd X Load Indirect and Pre Dec X X 1 Rd X None 2 LD Rd Y Load Indirect Rd Y None 2 LD Rd Y Load Indirect and Post Inc Rd Y Y Y 1 None 2 LD Rd Y Load Indirect and Pre Dec Y Y 1 Rd Y None 2 LDD ...

Page 431: ...328P POP Rd Pop Register from Stack Rd STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep see specific descr for Sleep function None 1 WDR Watchdog Reset see specific descr for WDR timer None 1 BREAK Break For On chip Debug Only None N A Mnemonics Operands Description Operation Flags Clocks ...

Page 432: ...317 Speed MHz Power Supply Ordering Code 2 Package 1 Operational Range 10 3 1 8 5 5 ATmega48PV 10AU ATmega48PV 10MMU ATmega48PV 10MU ATmega48PV 10PU 32A 28M1 32M1 A 28P3 Industrial 40 C to 85 C 20 3 2 7 5 5 ATmega48P 20AU ATmega48P 20MMU ATmega48P 20MU ATmega48P 20PU 32A 28M1 32M1 A 28P3 Industrial 40 C to 85 C Package Type 32A 32 lead Thin 1 0 mm Plastic Quad Flat Package TQFP 28M1 28 pad 4 x 4 x...

Page 433: ...reen 3 See Figure 26 1 on page 317 and Figure 26 2 on page 317 Speed MHz Power Supply Ordering Code 2 Package 1 Operational Range 10 3 1 8 5 5 ATmega88PV 10AU ATmega88PV 10MU ATmega88PV 10PU 32A 32M1 A 28P3 Industrial 40 C to 85 C 20 3 2 7 5 5 ATmega88P 20AU ATmega88P 20MU ATmega88P 20PU 32A 32M1 A 28P3 Industrial 40 C to 85 C Package Type 32A 32 lead Thin 1 0 mm Plastic Quad Flat Package TQFP 28P...

Page 434: ...een 3 See Figure 26 1 on page 317 and Figure 26 2 on page 317 Speed MHz 3 Power Supply Ordering Code 2 Package 1 Operational Range 10 1 8 5 5 ATmega168PV 10AU ATmega168PV 10MU ATmega168PV 10PU 32A 32M1 A 28P3 Industrial 40 C to 85 C 20 2 7 5 5 ATmega168P 20AU ATmega168P 20MU ATmega168P 20PU 32A 32M1 A 28P3 Industrial 40 C to 85 C Package Type 32A 32 lead Thin 1 0 mm Plastic Quad Flat Package TQFP ...

Page 435: ...of Hazardous Substances RoHS directive Also Halide free and fully Green 3 See Figure 26 3 on page 318 Speed MHz Power Supply Ordering Code 2 Package 1 Operational Range 20 3 1 8 5 5 ATmega328P AU ATmega328P MU ATmega328P PU 32A 32M1 A 28P3 Industrial 40 C to 85 C Package Type 32A 32 lead Thin 1 0 mm Plastic Quad Flat Package TQFP 28P3 28 lead 0 300 Wide Plastic Dual Inline Package PDIP 32M1 A 32 p...

Page 436: ...E B Notes 1 This package conforms to JEDEC reference MS 026 Variation ABA 2 Dimensions D1 and E1 do not include mold protrusion Allowable protrusion is 0 25 mm per side Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch 3 Lead coplanarity is 0 10 mm maximum A 1 20 A1 0 05 0 15 A2 0 95 1 00 1 05 D 8 75 9 00 9 25 D1 6 90 7 00 7 10 Note 2 E 8 75 9 00 9 25 E1 6 90 7 ...

Page 437: ...ery Thin Quad Flat No Lead Package VQFN 10 24 08 SIDE VIEW Pin 1 ID BOTTOM VIEW TOP VIEW Note The terminal 1 ID is a Laser marked Feature D E e K A1 C A D2 E2 y L 1 2 3 b 1 2 3 0 45 COMMON DIMENSIONS Unit of Measure mm SYMBOL MIN NOM MAX NOTE A 0 80 0 90 1 00 A1 0 00 0 02 0 05 b 0 17 0 22 0 27 C 0 20 REF D 3 95 4 00 4 05 D2 2 35 2 40 2 45 E 3 95 4 00 4 05 E2 2 35 2 40 2 45 e 0 45 L 0 35 0 40 0 45 ...

Page 438: ...IONS Unit of Measure mm SYMBOL MIN NOM MAX NOTE D1 D E1 E e b A3 A2 A1 A D2 E2 0 08 C L 1 2 3 P P 0 1 2 3 A 0 80 0 90 1 00 A1 0 02 0 05 A2 0 65 1 00 A3 0 20 REF b 0 18 0 23 0 30 D D1 D2 2 95 3 10 3 25 4 90 5 00 5 10 4 70 4 75 4 80 4 70 4 75 4 80 4 90 5 00 5 10 E E1 E2 2 95 3 10 3 25 e 0 50 BSC L 0 30 0 40 0 50 P 0 60 12o Note JEDEC Standard MO 220 Fig 2 Anvil Singulation VHHD 2 TOP VIEW SIDE VIEW ...

Page 439: ...B REF E B1 C L SEATING PLANE A 0º 15º D e eB B2 4 PLACES COMMON DIMENSIONS Unit of Measure mm SYMBOL MIN NOM MAX NOTE A 4 5724 A1 0 508 D 34 544 34 798 Note 1 E 7 620 8 255 E1 7 112 7 493 Note 1 B 0 381 0 533 B1 1 143 1 397 B2 0 762 1 143 L 3 175 3 429 C 0 203 0 356 eB 10 160 e 2 540 TYP Note 1 Dimensions D and E1 do not include mold Flash or Protrusion Mold Flash or Protrusion shall not exceed 0 ...

Page 440: ...v C Not sampled 32 2 2 Rev B No known errata 32 2 3 Rev A No known errata 32 3 Errata ATmega168P The revision letter in this section refers to the revision of the ATmega168P device 32 3 1 Rev B No known errata 32 3 2 Rev A No known errata 32 4 Errata ATmega328P The revision letter in this section refers to the revision of the ATmega328P device 32 4 1 Rev C No known errata 32 4 2 Rev B Unstable 32 ...

Page 441: ...8P Problem Fix Workaround None 32 4 3 Rev A Unstable 32 kHz Oscillator 1 Unstable 32 kHz Oscillator The 32 kHz oscillator does not work as system clock The 32 kHz oscillator used as asynchronous timer is inaccurate Problem Fix Workaround None ...

Page 442: ... for new designs 2 Updated the footnote Note1 of the Table 6 3 on page 29 3 Updated the Table 6 5 on page 30 by removing a footnote Note1 4 Updated the Table 6 10 on page 33 by removing a footnote Note1 5 Updated the footnote Note1 of the Table 6 12 on page 34 6 Updated the footnote Note2 of the ATmega48P DC Characteristics on page 314 and removed TBD from the table 7 Updated the footnote Note2 of...

Page 443: ... 316 8 Updated Speed Grades on page 316 for ATmega328P 9 Removed note 6 and 7 from the table 2 wire Serial Interface Characteristics on page 323 10 Added figure Minimum Reset Pulse width vs VCC on page 352 for ATmega48P 11 Added figure Minimum Reset Pulse width vs VCC on page 376 for ATmega88P 12 Added figure Minimum Reset Pulse width vs VCC on page 400 for ATmega168P 13 Added ATmega328P Typical C...

Page 444: ...ectors Start Address in Table 9 5 on page 63 and Table 9 7 on page 66 8 Updated Temperature Measurement on page 261 9 Updated ATmega328P Fuse Bits on page 295 10 Removed VOL3 VOH3 rows from DC Characteristics on page 313 11 Updated condition for VOL in DC Characteristics on page 313 Updated max value for VIL2 in DC Characteristics on page 313 12 Added ATmega48P DC Characteristics on page 314 ATmeg...

Page 445: ...c Logic Unit 9 4 3Status Register 9 4 4General Purpose Register File 11 4 5Stack Pointer 12 4 6Instruction Execution Timing 13 4 7Reset and Interrupt Handling 14 5 AVR Memories 16 5 1Overview 16 5 2In System Reprogrammable Flash Program Memory 16 5 3SRAM Data Memory 18 5 4EEPROM Data Memory 19 5 5I O Memory 20 5 6Register Description 21 6 System Clock and Clock Options 26 6 1Clock Systems and thei...

Page 446: ...ower save Mode 41 7 7Standby Mode 41 7 8Extended Standby Mode 41 7 9Power Reduction Register 42 7 10Minimizing Power Consumption 42 7 11Register Description 44 8 System Control and Reset 46 8 1Resetting the AVR 46 8 2Reset Sources 46 8 3Power on Reset 47 8 4External Reset 48 8 5Brown out Detection 48 8 6Watchdog System Reset 49 8 7Internal Voltage Reference 49 8 8Watchdog Timer 50 8 9Register Desc...

Page 447: ...tch Output Unit 98 12 7Modes of Operation 99 12 8Timer Counter Timing Diagrams 104 12 9Register Description 106 13 16 bit Timer Counter1 with PWM 113 13 1Features 113 13 2Overview 113 13 3Accessing 16 bit Registers 115 13 4Timer Counter Clock Sources 118 13 5Counter Unit 119 13 6Input Capture Unit 120 13 7Output Compare Units 122 13 8Compare Match Output Unit 124 13 9Modes of Operation 125 13 10Ti...

Page 448: ... 158 16 SPI Serial Peripheral Interface 166 16 1Features 166 16 2Overview 166 16 3SS Pin Functionality 171 16 4Data Modes 171 16 5Register Description 173 17 USART0 176 17 1Features 176 17 2Overview 176 17 3Clock Generation 177 17 4Frame Formats 180 17 5USART Initialization 182 17 6Data Transmission The USART Transmitter 183 17 7Data Reception The USART Receiver 186 17 8Asynchronous Data Reception...

Page 449: ...and Arbitration 240 19 9Register Description 241 20 Analog Comparator 246 20 1Overview 246 20 2Analog Comparator Multiplexed Input 246 20 3Register Description 247 21 Analog to Digital Converter 250 21 1Features 250 21 2Overview 250 21 3Starting a Conversion 252 21 4Prescaling and Conversion Timing 253 21 5Changing Channel or Reference Selection 255 21 6ADC Noise Canceler 256 21 7ADC Conversion Re...

Page 450: ...rogramming 282 24 8Self Programming the Flash 282 24 9Register Description 292 25 Memory Programming 294 25 1Program And Data Memory Lock Bits 294 25 2Fuse Bits 295 25 3Signature Bytes 298 25 4Calibration Byte 299 25 5Page Size 299 25 6Parallel Programming Parameters Pin Mapping and Commands 299 25 7Parallel Programming 301 25 8Serial Downloading 308 26 Electrical Characteristics 313 26 1Absolute ...

Page 451: ...2ATmega88P 433 30 3ATmega168P 434 30 4ATmega328P 435 31 Packaging Information 436 31 132A 436 31 228M1 437 31 332M1 A 438 31 428P3 439 32 Errata 440 32 1Errata ATmega48P 440 32 2Errata ATmega88P 440 32 3Errata ATmega168P 440 32 4Errata ATmega328P 440 33 Datasheet Revision History 442 33 1Rev 2545I 02 09 442 33 2Rev 2545H 02 09 442 33 3Rev 2545G 01 09 442 33 4Rev 2545F 08 08 443 33 5Rev 2545E 08 08...

Page 452: ... is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDI TIONS OF SALE LOCATED ON ATMEL S WEB SITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRI...

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