Atmel AVR AT90CAN128, Manual

Page: 179 / 428

179
7679H–CAN–08/08
AT90CAN32/64/128
17.4 Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USARTn supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USARTn
Control and Status Register C (UCSRnC) selects between asynchronous and synchronous
operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register
for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCKn pin is only active when using synchronous mode.
Figure 17-2 shows a block diagram of the clock generation logic.
Figure 17-2. USARTn Clock Generation Logic, Block Diagram
Signal description:
txn clk Transmitter clock (Internal Signal).
rxn clk Receiver base clock (Internal Signal).
xn cki Input from XCK pin (internal Signal). Used for synchronous slave
operation.
xn cko Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
f
clk
io
System I/O Clock frequency.
17.4.1 Internal Clock Generation – Baud Rate Generator
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to
Figure 17-2 .
The USARTn Baud Rate Register (UBRRn) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(
f
clk
io
), is loaded with the UBRRn value each time the counter has counted down to zero or
when the UBRRnL Register is written. A clock is generated each time the counter reaches zero.
This clock is the baud rate generator clock output (=
f
clk
io
/(UBRRn+1)). The Transmitter divides
the baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator
output is used directly by the Receiver’s clock and data recovery units. However, the recovery
Prescaling
Down-Counter
/2
UBRRn
/4 /2
Sync
Register
clk
XCKn
Pin
txn clk
U2Xn
UMSELn
DDR_XCKn
0
1
0
1
xn cki
xn cko
DDR_XCKn
rxn clk
0
1
1
0
Edge
Detector
UCPOLn
io
UBRRn+1
f
clk
io