108
7679H–CAN–08/08
AT90CAN32/64/128
decrements. The PWM frequency for the output when using phase correct PWM can be calcu-
lated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
12.8
Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T0
) is therefore shown as a
clock enable signal in the following figures. The figures include information on when interrupt
flags are set.
contains timing data for basic Timer/Counter operation. The figure
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 12-8.
Timer/Counter Timing Diagram, no Prescaling
shows the same timing data, but with the prescaler enabled.
Figure 12-9.
Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
f
OCnxPCPWM
f
clk_I/O
N
510
⋅
------------------
=
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn
MAX - 1
MAX
BOTTOM
1
TOVn
TCNTn
MAX - 1
MAX
BOTTOM
1
clk
I/O
clk
Tn
(clk
I/O
/8)
