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57

8068C–AVR–06/08

XMEGA A3

Notes:

1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid 

for accesses via the external RAM interface.

2. One extra cycle must be added when accessing Internal SRAM.

ROL

Rd

Rotate Left Through Carry

Rd(0)

Rd(n+1)

C

←

←

←

C,
Rd(n),
Rd(7)

Z,C,N,V,H

1

ROR

Rd

Rotate Right Through Carry

Rd(7)
Rd(n)

C

←

←

←

C,
Rd(n+1),
Rd(0)

Z,C,N,V

1

ASR

Rd

Arithmetic Shift Right

Rd(n)

←

Rd(n+1), n=0..6

Z,C,N,V

1

S

W

AP

Rd

Swap Nibbles

Rd(3..0)

↔

Rd(7..4)

None

1

BSET

s

Flag Set

SREG(s)

←

1

SREG(s)

1

BCLR

s

Flag Clear

SREG(s)

←

0

SREG(s)

1

SBI

A, b

Set Bit in I/O Register

I/O(A, b)

←

1

None

1

CBI

A, b

Clear Bit in I/O Register

I/O(A, b)

←

0

None

1

BST

Rr, b

Bit Store from Register to T

T

←

Rr(b)

T

1

BLD

Rd, b

Bit load from T to Register

Rd(b)

←

T

None

1

SEC

Set Carry

C

←

1

C

1

CLC

Clear Carry

C

←

0

C

1

SEN

Set Negative Flag

N

←

1

N

1

CLN

Clear Negative Flag

N

←

0

N

1

SEZ

Set Zero Flag

Z

←

1

Z

1

CLZ

Clear Zero Flag

Z

←

0

Z

1

SEI

Global Interrupt Enable

I

←

1

I

1

CLI

Global Interrupt Disable

I

←

0

I

1

SES

Set Signed Test Flag

S

←

1

S

1

CLS

Clear Signed Test Flag

S

←

0

S

1

SEV

Set Two’s Complement Overflow

V

←

1

V

1

CLV

Clear Two’s Complement Overflow

V

←

0

V

1

SET

Set T in SREG

T

←

1

T

1

CLT

Clear T in SREG

T

←

0

T

1

SEH

Set Half Carry Flag in SREG

H

←

1

H

1

CLH

Clear Half Carry Flag in SREG

H

←

0

H

1

MCU Control Instructions

BREAK

Break

(See specific descr. for BREAK)

None

1

NOP

No Operation

None

1

SLEEP

Sleep

(see specific descr. for Sleep)

None

1

W

DR

W

atchdog Reset

(see specific descr. for 

W

DR)

None

1

Mnemonics

Operands

Description

Operation

Flags

#Clocks

Summary of Contents for ATxmega128A3-AU

Page 1: ...nalog to Digital Converters One Two channel 12 bit 1 Msps Digital to Analog Converter Four Analog Comparators with Window compare function External Interrupts on all General Purpose I O pins Programma...

Page 2: ...MU 128K 8K 2K 8K 32 1 8 3 6V ATxmega64A3 MU 64K 4K 2K 4K 32 1 8 3 6V Package Type 64A 64 lead 14 x 14 mm Body Size 1 0 mm Body Thickness 0 8 mm Lead Pitch Thin Profile Plastic Quad Flat Package TQFP 6...

Page 3: ...also have an IEEE std 1149 1 compliant JTAG test interface and this can also be used for On chip Debug and programming The XMEGA A3 devices have five software selectable power saving modes The Idle m...

Page 4: ...PB 0 7 JTAG Watchdog Timer Watchdog Oscillator Interrupt Controller DATA BUS DATA BUS Prog Debug Controller VCC GND Oscillator Circuits Clock Generation Oscillator Control Real Time Counter Event Sys...

Page 5: ...e The XMEGA A Manual describes the modules and peripherals in depth The XMEGA A application notes contain example code and show applied use of the modules and peripherals The XMEGA A Manual and Applic...

Page 6: ...ure cor rect program execution The CPU must therefore be able to access memories perform calculations and control peripherals Interrupt handling is described in a separate section Figure 6 1 on page 6...

Page 7: ...d to reflect information about the result of the operation The ALU operations are divided into three main categories arithmetic logical and bit func tions Both 8 and 16 bit arithmetic is supported and...

Page 8: ...roller priority Separate buses for SRAM EEPROM I O Memory and External Memory access Simultaneous bus access for CPU and DMA Controller Calibration Row Memory for factory programmed data Oscillator ca...

Page 9: ...ide in the Boot Section when used to write to the Flash memory A third section inside the Application section is referred to as the Application Table section which has separate Lock bits for storage o...

Page 10: ...ress Byte Address ATxmega192A3 Byte Address ATxmega128A3 Byte Address ATxmega64A3 0 I O Registers 4KB 0 I O Registers 4KB 0 I O Registers 4KB FFF FFF FFF 1000 EEPROM 4K 1000 EEPROM 2K 1000 EEPROM 2K 1...

Page 11: ...range 0x00 0x1F are directly bit accessible using the SBI and CBI instructions The value of single bits can be checked by using the SBIS and SBIC instruc tions on these registers The I O memory addres...

Page 12: ...om application software and external programming Table 7 1 Device ID bytes for XMEGA A3 devices 7 6 User Signature Row The User Signature Row is a separate memory section that is fully accessible read...

Page 13: ...and erase operations can be performed one page or one byte at the time while reading the EEPROM is done one byte at the time For EEPROM access the NVM Address Register ADDR m n is used for addressing...

Page 14: ...gle transactions up to 16M bytes Each DMA channel can be configured to access the source and destination memory address with incrementing decrement ing or static addressing The addressing is independe...

Page 15: ...ossibil ity for a change of state in one peripheral to automatically trigger actions in one or more peripherals What changes in a peripheral that will trigger actions in other peripherals are config u...

Page 16: ...nts from all peripherals are always routed into the Event Routing Network This consist of eight multiplexers where each can be configured in software to select which event to be routed into that event...

Page 17: ...advanced clock system supporting a large number of clock sources It incor porates both integrated oscillators external crystal oscillators and resonators A high frequency Phase Locked Loop PLL and cl...

Page 18: ...8 kHz Calibrated Internal Oscillator The 32 768 kHz Calibrated Internal Oscillator is a high accuracy clock source that can be used as the system clock source or as an asynchronous clock source for th...

Page 19: ...calibrating the frequency run time to compensate for temperature and voltage drift hereby optimizing the accuracy of the oscillator 10 3 6 32 MHz Run time Calibrated Internal Oscillator The 32 MHz Run...

Page 20: ...ion in Active mode and Idle sleep mode 11 3 Sleep Modes 11 3 1 Idle Mode In Idle mode the CPU and Non Volatile Memory are stopped but all peripherals including the Interrupt Controller Event System an...

Page 21: ...de Extended Standby mode is identical to Power save mode with the exception that all enabled system clock sources are kept running while the CPU and Peripheral clocks are stopped This reduces the wake...

Page 22: ...e Reset Vector to the first address in the Boot Section The I O ports of the AVR are immediately tri stated when a reset source goes active The reset functionality is asynchronous so no running clock...

Page 23: ...s a Watchdog Timer WDT The WDT will run continuously when turned on and if the Watchdog Timer is not reset within a software configurable time out period the micro controller will be reset The Watchdo...

Page 24: ...ump to the interrupt vector address The interrupt vector is the sum of the peripheral s base interrupt address and the offset address for specific interrupts in each peripheral The base addresses for...

Page 25: ...base USART 1 on port E Interrupt base 0x080 PORTD_INT_base Port D Interrupt base 0x084 PORTA_INT_base Port A Interrupt base 0x088 ACA_INT_base Analog Comparator on Port A Interrupt base 0x08E ADCA_INT...

Page 26: ...nnel 7 output on port pin Mapping of port registers virtual ports into bit accessible I O memory space 14 2 Overview The XMEGA A3 devices have flexible General Purpose I O Ports A port consists of up...

Page 27: ...e with pull down on input 14 3 3 Pull up Figure 14 3 I O configuration Totem pole with pull up on input 14 3 4 Bus keeper The bus keeper s weak output produces the same logical level as the last outpu...

Page 28: ...14 4 I O configuration Totem pole with bus keeper 14 3 5 Others Figure 14 5 Output configuration Wired OR with optional pull down Figure 14 6 I O configuration Wired AND with optional pull up INn OUT...

Page 29: ...source for each of the interrupts The interrupts are then triggered according to the input sense configuration for each pin configured as source for the interrupt 14 6 Alternate Port Functions In add...

Page 30: ...en them is that Timer Counter 0 has four Compare Capture channels while Timer Counter 1 has two Compare Capture channels The Timer Counters T C are 16 bit and can count any clock event or external inp...

Page 31: ...tension can be enabled to provide extra and more advanced fea tures for the Timer Counter This are only available for Timer Counter 0 See AWEX Advanced Waveform Extension on page 32 for more details A...

Page 32: ...ure is enabled These output pairs go through a Dead Time Insertion DTI unit that enables generation of the non inverted Low Side LS and inverted High Side HS of the WG output with dead time insertion...

Page 33: ...o increase the resolution of the waveform genera tion output by a factor of 4 When enabled for a Timer Counter the Fast Peripheral clock running at four times the CPU clock speed will be as input to t...

Page 34: ...ate 32 768 kHz Crystal Oscillator the 32 768 kHz Calibrated Internal Oscillator or from the 32 kHz Ultra Low Power Internal Oscillator The RTC includes both a Period and a Compare register For details...

Page 35: ...l Support Address Recognition Causes Wake up when in Sleep Mode I2 C and System Management Bus SMBus compatible 19 2 Overview The Two Wire Interface TWI is a bi directional wired AND bus with only two...

Page 36: ...sion Interrupt Flag Write Collision Flag Protection Wake up from Idle Mode Double Speed CK 2 Master SPI Mode 20 2 Overview The Serial Peripheral Interface SPI allows high speed full duplex synchronous...

Page 37: ...Transmitter USART is a highly flexible serial communication module The USART supports full duplex communication and both asynchronous and clocked synchronous operation The USART can also be set in Ma...

Page 38: ...modulation disabled Built in filtering Can be connected to and used by one USART at the time 22 2 Overview XMEGA contains an Infrared Communication Module IRCOM for IrDA communication with baud rates...

Page 39: ...ll communication interfaces and the CPU can optionally use AES and DES encrypted communication and data storage DES is supported by a DES instruction in the AVR XMEGA CPU The 8 byte key and 8 byte dat...

Page 40: ...is flexible and both single ended and differential measurements can be performed The ADC can provide both signed and unsigned results and an optional gain stage is available to increase the dynamic r...

Page 41: ...op agation delay from 3 5 s for 12 bit to 2 5 s for 8 bit result ADC conversion results are provided left or right adjusted with optional 1 or 0 padding This eases calculation when the result is repre...

Page 42: ...shared with the ADC reference input Figure 25 1 DAC overview Each DAC has one continuous output with high drive capabilities for both resistive and capaci tive loads It is also possible to split the...

Page 43: ...atures four Analog Comparators AC An Analog Comparator compares two volt ages and the output indicates which input is largest The Analog Comparator may be configured to give interrupt requests and or...

Page 44: ...e 26 1 Analog comparator overview AC0 Pin inputs Internal inputs Pin inputs Internal inputs VCC scaled Interrupt sensitivity control Interrupts AC1 Pin inputs Internal inputs Pin inputs Internal input...

Page 45: ...alog comparator Internal signals available on positive analog comparator inputs Output from 12 bit DAC Internal signals available on negative analog comparator inputs 64 level scaler of the VCC availa...

Page 46: ...nge Bits of a data location are equal or not equal to a value Non Intrusive Operation No hardware or software resources in the device are used High Speed Operation No limitation on debug programming c...

Page 47: ...accessed through the JTAG and PDI physical inter faces The PDI physical uses one dedicated pin together with the Reset pin and no general purpose pins are used JTAG uses four general purpose pins on...

Page 48: ...les below show the notation for all pin functions available and describe its function 29 1 1 Operation Power Supply 29 1 2 Port Interrupt functions 29 1 3 Analog functions VCC Digital supply voltage A...

Page 49: ...hen external driver interface is enabled SDAOUT Serial Data Out for TWI when external driver interface is enabled XCKn Transfer Clock for USART n RXDn Receiver Data for USART n TXDn Transmitter Data f...

Page 50: ...SYNC ASYNC ADC2 ADC2 ADC2 AC2 PA3 1 SYNC ADC3 ADC3 ADC3 AC3 AC3 PA4 2 SYNC ADC4 ADC4 ADC4 AC4 PA5 3 SYNC ADC5 ADC5 ADC5 AC5 AC5 PA6 4 SYNC ADC6 ADC6 ADC6 AC6 PA7 5 SYNC ADC7 ADC7 ADC7 AC7 AC0 OUT Tab...

Page 51: ...functions PORT D PIN INTERRUPT TCD0 TCD1 USARTD0 USARTD1 SPID CLOCKOUT EVENTOUT PD0 26 SYNC OC0A PD1 27 SYNC OC0B XCK0 PD2 28 SYNC ASYNC OC0C RXD0 PD3 29 SYNC OC0D TXD0 PD4 30 SYNC OC1A SS PD5 31 SYNC...

Page 52: ...nctions PORT F PIN INTERRUPT TCF0 USARTF0 PF0 46 SYNC OC0A PF1 47 SYNC OC0B XCK0 PF2 48 SYNC ASYNC OC0C RXD0 PF3 49 SYNC OC0D TXD0 PF4 50 SYNC PF5 51 SYNC PF6 54 SYNC PF7 55 SYNC GND 52 VCC 53 PORT R...

Page 53: ...nalog Comparator pair on port A 0x0390 ACB Analog Comparator pair on port B 0x0400 RTC Real Time Counter 0x0480 TWIC Two Wire Interface on port C 0x04A0 TWIE Two Wire Interfaceon port E 0x0600 PORTA P...

Page 54: ...t s in Register Rd Rd v K Z N V S 1 CBR Rd K Clear Bit s in Register Rd Rd FFh K Z N V S 1 INC Rd Increment Rd Rd 1 Z N V S 1 DEC Rd Decrement Rd Rd 1 Z N V S 1 TST Rd Test for Zero or Minus Rd Rd Rd...

Page 55: ...PC PC k 1 None 1 2 BRMI k Branch if Minus if N 1 then PC PC k 1 None 1 2 BRPL k Branch if Plus if N 0 then PC PC k 1 None 1 2 BRGE k Branch if Greater or Equal Signed if N V 0 then PC PC k 1 None 1 2...

Page 56: ...e 1 1 ST Z Rr Store Indirect and Post Increment Z Z Rr Z 1 None 1 1 ST Z Rr Store Indirect and Pre Decrement Z Z 1 None 2 1 STD Z q Rr Store Indirect with Displacement Z q Rr None 2 1 LPM Load Program...

Page 57: ...from Register to T T Rr b T 1 BLD Rd b Bit load from T to Register Rd b T None 1 SEC Set Carry C 1 C 1 CLC Clear Carry C 0 C 1 SEN Set Negative Flag N 1 N 1 CLN Clear Negative Flag N 0 N 1 SEZ Set Zer...

Page 58: ...or extended periods may affect device reliability Storage Temperature 65 C to 150 C Voltage on any Pin with respect to Ground 0 5V to VCC 0 5V Maximum Operating Voltage 3 6V DC Current per I O Pin 20...

Page 59: ...maximum frequency of the XMEGA A3 devices is depending on VCC As shown in Figure 32 1 on page 59 the Frequency vs VCC curve is linear between 1 8V VCC 2 7V Figure 32 1 Maximum Frequency vs Vcc 1 8 12...

Page 60: ...n Linearity DNL LSB Gain Error LSB Offset Error LSB Conversion Time s ADC Clock Frequency MHz DC Supply Voltage mA Source Impedance Start up time s AVCC Analog Supply Voltage VCC 0 3 VCC 0 3 V Table 3...

Page 61: ...B Calibrated Gain Offset Error LSB Output Range V Output Settling Time s Output Capacitance nF Output Resistance k Reference Input Voltage V Reference Input Capacitance pF Reference Input Resistance k...

Page 62: ...62 8068C AVR 06 08 XMEGA A3 33 Typical Characteristics TBD...

Page 63: ...ENSIONS Unit of Measure mm SYMBOL MIN NOM MAX NOTE Notes 1 This package conforms to JEDEC reference MS 026 Variation AEB 2 Dimensions D1 and E1 do not include mold protrusion Allowable protrusion is 0...

Page 64: ...30 D D2 5 20 5 40 5 60 8 90 9 00 9 10 8 90 9 00 9 10 E E2 5 20 5 40 5 60 e 0 50 BSC L 0 35 0 40 0 45 Note 1 JEDEC Standard MO 220 SAW Singulation Fig 1 VMMD 2 Dimension and tolerance conform to ASMEY1...

Page 65: ...65 8068C AVR 06 08 XMEGA A3 35 Errata 35 1 All rev No known errata...

Page 66: ...n Functions on page 48 3 Updated Ordering Information on page 2 4 Updated Overview on page 3 included the XMEGA A3 explanation text on page 6 5 Added XMEGA A3 Block Diagram Figure 3 1 on page 4 6 Upda...

Page 67: ...2Overview 6 6 3Register File 7 6 4ALU Arithmetic Logic Unit 7 6 5Program Flow 7 7 Memories 8 7 1Features 8 7 2Overview 8 7 3In System Programmable Flash Program Memory 9 7 4Data Memory 10 7 5Calibrat...

Page 68: ...lti level Interrupt Controller 24 13 1Features 24 13 2Overview 24 13 3Interrupt vectors 24 14 I O Ports 26 14 1Features 26 14 2Overview 26 14 3I O configuration 26 14 4Input sensing 29 14 5Port Interr...

Page 69: ...eatures 38 22 2Overview 38 23 Crypto Engine 39 23 1Features 39 23 2Overview 39 24 ADC 12 bit Analog to Digital Converter 40 24 1Features 40 24 2Overview 40 25 DAC 12 bit Digital to Analog Converter 42...

Page 70: ...Summary 54 32 Electrical Characteristics TBD 58 32 1Absolute Maximum Ratings 58 32 2DC Characteristics 58 32 3Speed 59 32 4ADC Characteristics TBD 60 32 5DAC Characteristics TBD 61 32 6Analog Comparat...

Page 71: ...R STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABL...

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