14.5.3. Clocks
The DSU bus clocks (CLK_DSU_APB and CLK_DSU_AHB) can be enabled and disabled by the Main
Clock Controller.
Related Links
on page 141
14.5.4. Interrupts
Not applicable.
14.5.5. Events
Not applicable.
14.5.6. Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC),
except the following:
•
Debug Communication Channel 0 register (DCC0)
•
Debug Communication Channel 1 register (DCC1)
Note:
Optional write-protection is indicated by the "PAC Write-Protection" property in the register
description.
When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection
does not apply for accesses through an external debugger.
Related Links
PAC - Peripheral Access Controller
on page 50
14.5.7. Analog Connections
Not applicable.
14.6. Debug Operation
14.6.1. Principle of Operation
The DSU provides basic services to allow on-chip debug using the ARM Debug Access Port and the
ARM processor debug resources:
•
CPU reset extension
•
Debugger probe detection
For more details on the ARM debug components, refer to the ARM Debug Interface v5 Architecture
Specification.
14.6.2. CPU Reset Extension
“CPU reset extension” refers to the extension of the reset phase of the CPU core after the external reset
is released. This ensures that the CPU is not executing code at startup while a debugger connects to the
system. It is detected on a RESET release event when SWCLK is low. At startup, SWCLK is internally
pulled up to avoid false detection of a debugger if SWCLK is left unconnected. When the CPU is held in
the reset extension phase, the CPU Reset Extension bit of the Status A register (STATUSA.CRSTEXT) is
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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