Sleep Mode
The CFD is halted depending on configuration of the XOSC32K and the peripheral clock request. For
further details, refer to the Sleep Behavior table above. The CFD interrupt can be used to wake up the
device from sleep modes.
22.6.4. 32KHz Ultra Low Power Internal Oscillator (OSCULP32K) Operation
The OSCULP32K provides a tunable, low-speed, and ultra-low-power clock source. The OSCULP32K is
factory-calibrated under typical voltage and temperature conditions.
The OSCULP32K is enabled by default after a power-on reset (POR) and will always run except during
POR. The frequency of the OSCULP32K oscillator is controlled by the value in the 32KHz Ultra Low
Power Internal Oscillator Calibration bits in the 32KHz Ultra Low Power Internal Oscillator Control register
(OSCULP32K.CALIB). This data is used to compensate for process variations.
OSCULP32K.CALIB is automatically loaded from Flash Factory Calibration during start-up. The
calibration value can be overridden by the user by writing to OSCULP32K.CALIB.
It is also possible to lock the OSCULP32K configuration by setting the Write Lock bit in the 32KHz Ultra
Low Power Internal Oscillator Control register (OSCULP32K.WRTLOCK=1). If set, the OSCULP32K
configuration is locked until a power-on reset (POR) is detected.
The OSCULP32K can be used as a source for Generic Clock Generators (GCLK) or for the Real-Time
Counter (RTC). To ensure proper operation, the GCLK or RTC modules must be disabled before the clock
selection is changed.
Related Links
Real-Time Counter Clock Selection
on page 264
GCLK - Generic Clock Controller
on page 121
22.6.5. Watchdog Timer Clock Selection
The Watchdog Timer (WDT) uses the internal 1.024kHz OSCULP32K output clock. This clock is running
all the time and internally enabled when requested by the WDT module.
Related Links
on page 311
22.6.6. Real-Time Counter Clock Selection
Before enabling the RTC module, the RTC clock must be selected first. All oscillator outputs are valid as
RTC clock. The selection is done in the RTC Control register (RTCCTRL). To ensure a proper operation,
it is highly recommended to disable the RTC module first, before the RTC clock source selection is
changed.
Related Links
22.6.7. SLCD Clock Selection
Before enabling the SLCD module, the SLCD clock must be selected first. the 32.768kHz outputs of
OSCULP32K and XOSC32K are valid as SLCD clock. The selection is done by the SLCD Selection bit in
the SLCD Control register (
To ensure proper operation, it is highly recommended to first disable the SLCD module before the SLCD
clock source is selected.
changed.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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