Request for Clock n
present
GENCTRLn.RUNSTDB
Y
GENCTRLn.OE
Clock Generator n
no
0
1
OFF
no
0
0
OFF
16.6.5.3. Entering Standby Mode
There may occur a delay when the device is put into Standby, until the power is turned off. This delay is
caused by running Clock Generators: if the Run in Standby bit in the Generator Control register
(GENCTRLn.RUNSTDBY) is '0', GCLK must verify that the clock is turned of properly. The duration of this
verification is frequency-dependent.
Related Links
on page 188
16.6.6. Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
An exception is the Channel Enable bit in the Peripheral Channel Control registers (PCHCTRLm.CHEN).
When changing this bit, the bit value must be read-back to ensure the synchronization is complete and to
assert glitch free internal operation. Note that changing the bit value under ongoing synchronization will
not
generate an error.
The following registers are synchronized when written:
•
Generic Clock Generator Control register (GENCTRLn)
•
Control A register (CTRLA)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register
description.
Related Links
on page 138
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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