background image

ATDH2200E Programming Kit User Guide

3-1

Rev. 1417E–CNFG–4/05

Section 3

In-System Programming (ISP)

Using Atmel’s ATDH2200E

Configurator Programming System

3.1

Hardware Setup

This User Guide is intended for the ATDH2200 Programming Board Rev.15. 

3.1.1

Hardware 
Requirements

„

ATDH2200 Programming Board Rev. 15

„

25-pin Parallel Cable

„

10-pin Ribbon Cable

„

PC with Standard Configuration Parallel Port

„

FPGA Configurators – AT17(A) Series Devices

3.1.2

Hardware 
Connections

1.

Connect the 25-pin parallel cable from the PC’s parallel port to connector P1 on 
the ATDH2200 programming board.

2.

Connect the 10-pin ribbon cable from the ATDH2200’s in-system programming 
Header U1 to the Target System’s matching ISP Header.

3.

Set jumper JP2

(2)

 to PROGRAM

(1)

.

4.

Remove jumper JP1

(1)(3)

5.

Insert the AT17(A) Configurator in the socket of the Target System. 

6.

Apply power to the Target System.

Notes: 1.

There is no jumper setting for the ATDH2225 ISP direct download cable. 
Only the connection described in Figure 4 is required.

2.

JP1 for Rev. 12 and 13 boards.

3.

JP3 for Rev. 11 boards. J2 for Rev. 12 and 13 boards. J3 for Rev. 14 
boards.

Summary of Contents for ATDH2200E

Page 1: ...ATDH2200E Programming Kit User Guide ...

Page 2: ......

Page 3: ...Devices 2 3 2 3 2 Reading the Contents of the Configurator to a BST File 2 3 2 3 3 Verifying the Device against a BST File 2 3 2 3 4 Verifying the Device Reset Polarity AT17LVxx Devices Only 2 3 2 4 Using a Configurator with Xilinx FPGAs 2 4 2 4 1 Program the Contents of a MCS File to AT17 Devices 2 4 2 4 2 Converting a MCS File 2 4 2 4 3 Reading the Contents of the Configurator to a BST File 2 4 ...

Page 4: ...2 2 Installing and or Launching CPS 3 2 3 3 Using a Configurator with Atmel FPGAs FPSLICs 3 3 3 3 1 Programming the Contents of a BST File to AT17 Devices 3 3 3 3 2 Reading the Contents of the Configurator to a BST File 3 3 3 3 3 Verifying the Device against a BST File 3 3 3 4 Using a Configurator with Xilinx FPGAs 3 4 3 4 1 Programming the Contents of a MCS File to the AT17 Devices 3 4 3 4 2 Conv...

Page 5: ...or Programming System GUI based Interface Supports Windows 98 2000 XP and Windows NT Online Help Supports Programming Reset Polarity Verification Routines to Validate Programming Accepts HEX MCS POF RBF and BST File Formats 1 1 3 System Contents ATDH2200 Programming Board Rev 15 ATDH2222 20 pin PLCC Adapter CPS Software ATDH2200E Programming Kit User Guide Standard PC Printer Port Parallel Cable 1...

Page 6: ... 1 2 In System Programming Header Notes 1 Pin 10 activates SER_EN on target board 2 NC stands for no connection The ATDH2200E programming board has a 10 pin header 0 1 spacing to facilitate in system programming Figure 1 2 of the AT17 parts The control signals generated by the software are fed to the header as well as to socket U3 on the board By placing a similar socket on the target system and c...

Page 7: ...5 ATDH2221 for 20 pin SOIC Devices ATDH2222 for all 20 pin PLCC Devices Including 2 Mbit Devices ATDH2223 for all 8 pin SOIC Devices ATDH2224 for 44 pin TQFP Devices ATDH2226 for 32 pin TQFP Devices ATDH2227 for 44 pin PLCC Devices ATDH2227A for 44 pin A Part PLCC Devices ATDH2228 for 8 pin LAP Devices ...

Page 8: ...Atmel s ATDH2200E Configurator Programming Kit 1 4 ATDH2200E Programming Kit User Guide 1417E CNFG 4 05 ...

Page 9: ... 15 25 pin Parallel Cable 9V DC Power Supply FPGA Configurators AT17 A Series Devices PC with Standard Configuration Parallel Port Socket Adapters ATDH2220 for 20 pin PLCC Devices Excluding 2 Mbit Devices ATDH2221 for 20 pin SOIC Devices ATDH2222 for all 20 pin PLCC Devices Including 2 Mbit Devices ATDH2223 for all 8 pin SOIC Devices ATDH2224 for 44 pin TQFP Devices ATDH2226 for 32 pin TQFP Device...

Page 10: ... to apply power to the board LED D1 illuminates Notes 1 For Rev 12 and 13 of the ATDH2200 board this jumper is labeled as JP1 2 If programming AT17C series devices set the jumper towards AT17LV A For Rev 11 of the ATDH2200 board this jumper is labeled as JP3 For Rev 12 and 13 this jumper is labeled as J2 For Rev 14 this jumper is labeled as J3 2 2 Software Setup 2 2 1 Software Requirements CPS Con...

Page 11: ...name 3 Options Default or previous settings are given You may need to modify the following EEPROM Density Select the device density FPGA Family Select AT40K AT94K Cypress or AT6K Other A2 Bit Level Select Low 4 Press Start Procedure 1 2 3 3 Verifying the Device against a BST File 1 Procedure Select V Verify device against an Atmel file 2 Input File design bst 3 Options Default or previous settings...

Page 12: ...ut File design mcs 3 Output File Defaults to CPS_INSTALL_DIRECTORY out bst or the most recently used output filename 4 Press Start Procedure 2 4 3 Reading the Contents of the Configurator to a BST File 1 Procedure Select R Read data from device and save to an Atmel file 2 Output File Defaults to CPS_INSTALL_DIRECTORY out bst or the most recently used output filename 3 Options Default or previous s...

Page 13: ... 2 Options Default or previous settings are given You may need to modify the following Reset Polarity Select the reset polarity 3 Set JP2 2 to the VERIFY position on the ATDH2200 board 4 Press Start Procedure 1 5 Set JP2 2 back to the PROGRAM position on the ATDH2200 board Notes 1 If CPS is being launched for the first time the clock calibration dialog will appear Press Yes to proceed and select H...

Page 14: ...ECTORY out bst or the most recently used output filename 4 Options Default or previous settings are given You may need to modify the following EEPROM Density Select the device density 5 Press Start Procedure 2 5 3 Reading the Contents of the Configurator to a BST File 1 Procedure Select R Read data from device and save to an Atmel file 2 Output File Defaults to CPS_INSTALL_DIRECTORY out bst or the...

Page 15: ...40 Internal Clock 2 Options Default or previous settings are given You may need to modify the following EEPROM Density Select the device density A2 Bit Level Select Low 3 Press Start Procedure 1 2 2 5 7 Disabling the Clock Output on the AT17LV512A 010A 002A 040A Configurator 1 Procedure Select M Disable AT17LV512A 010A 020A 002A 040 Internal Clock 2 Options Default or previous settings are given Y...

Page 16: ... out bst or the most recently used output filename 4 Options Default or previous settings are given You may need to modify the following EEPROM Density Select the device density 5 Press Start Procedure 2 6 3 Reading the Contents of the Configurator to a BST File 1 Procedure Select R Read data from device and save to an Atmel file 2 Output File Defaults to CPS_INSTALL_DIRECTORY out bst or the most ...

Page 17: ... 5 Verifying the Device Polarity AT17LVxx Devices Only 1 Procedure Select X Verify device reset polarity 2 Options Default or previous settings are given You may need to modify the following Reset Polarity Select the reset polarity 3 Set JP2 1 to the VERIFY position on the ATDH2200E board 4 Press Start Procedure Note 1 JP1 for Rev 12 and 13 board ...

Page 18: ...Stand alone Device Programming Using Atmel s ATDH2200E Configurator Programming System 2 10 ATDH2200E Programming Kit User Guide 1417E CNFG 4 05 ...

Page 19: ...Connections 1 Connect the 25 pin parallel cable from the PC s parallel port to connector P1 on the ATDH2200 programming board 2 Connect the 10 pin ribbon cable from the ATDH2200 s in system programming Header U1 to the Target System s matching ISP Header 3 Set jumper JP2 2 to PROGRAM 1 4 Remove jumper JP1 1 3 5 Insert the AT17 A Configurator in the socket of the Target System 6 Apply power to the ...

Page 20: ...ystem Administrator privileges Atmel s CPS software can be downloaded from the Atmel web site at http www atmel com dyn products tools_card asp tool_id 3191 Figure 3 1 ATDH2200 In System Programming Figure 4 ATDH2225 In System Programming Parallel Cable Parallel Port PC DB 25M DB 25F ATDH2200 FPGA FPGA Target System 10 pin Ribbon Cable In System Programming Connector Header In System Programming C...

Page 21: ...ave to an Atmel file 2 Output File Defaults to CPS_INSTALL_DIRECTORY out bst or the most recently used output filename 3 Options Default or previous settings are given You may need to modify the following EEPROM Density Select the device density FPGA Family Select AT40K AT94K Cypress or AT6K Other A2 Bit Level Select the level that matches the level seen on the A2 pin of the target device 4 Press ...

Page 22: ...ed output filename 4 Press Start Procedure 3 4 3 Reading the Contents of the Configurator to a BST File 1 Procedure Select R Read data from device and save to an Atmel file 2 Output File Defaults to CPS_INSTALL_DIRECTORY out bst or the most recently used output filename 3 Options Default or previous settings are given You may need to modify the following EEPROM Density Select the device density FP...

Page 23: ...tents of a POF or RBF File Note Altera Quartus II users should use the rbf file 1 Procedure Select B Convert and partition an Altera file 2 Input File design pof rbf 3 Output File Defaults to CPS_INSTALL_DIRECTORY out bst or the most recently used output filename 4 Options Default or previous settings are given You may need to modify the following EEPROM Density Select the device density 5 Press S...

Page 24: ...A 040 Internal Clock 2 Options Default or previous settings are given You may need to modify the following EEPROM Density Select the device density A2 Bit Level Select the level that matches the level seen on the A2 pin of the target device 3 Press Start Procedure 1 2 3 5 6 Disabling the Clock Output on the AT17LV512A 010A 020A 002A 040A Configurator 1 Procedure Select M Disable AT17LV512A 010A 02...

Page 25: ... Rev Date Sheet of CE RESET_OE DATA CLK SELECT_IN CLKIN D0 INIT DATA ACK RESET_OE CE DATA RESET_OE CE SEREN CLK INIT GND GND D3 GND SELECT_IN D1 CLKIN GND D0 GND AUTO_FEED DATA_IN GND D6 D5 SELECT GND D2 D4 ACK GND BUSY PE CLK VCC VCC VCC VCC VCC R4 4 7K JP2 1 2 3 C3 0 1uF P1 DB25 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 U1 HARRISCD74LPT244 2 18 4 16 6 14 8 12 11 9 13 7 15...

Page 26: ... D D C C B B A A Layout U2 U9 for TO 220 pkgs R5 3 3k for 3 3 volts 9VDC 500mA AT17F A AT17N AT17LV A REMOVE FOR ISP ATDH2200 CHW 5450 15 FPGA CONFIGUATOR PROGRAMMER A 1 2 Tuesday March 23 2004 Title Size Document Number Rev Date Sheet of VCC U7 LM7805AT 1 2 3 VI GND VO U9 LM317T 3 1 2 IN ADJ OUT JP1 1 2 3 D2 LED C2 0 01uF J1 DC IN 3 2 1 D1 IN4001 S1 POWER R2 2 4K R3 3 3K R1 330ohms C1 100uF ...

Page 27: ...ostale 80 CH 1705 Fribourg Switzerland Tel 41 26 426 5555 Fax 41 26 426 5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721 9778 Fax 852 2722 1369 Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 Memory 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 436 4314...

Reviews: