Atmel ATA3741 Series, Operating

Page: 14 / 31

14
4899B–RKE–10/06
ATA3741
Figure 5-5 , Figure 5-6 and Figure 5-7 illustrate the bit check for the default bit-check limits
Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are
enabled during T
Startup
. The output of the ASK/FSK demodulator (Dem_out) is undefined during
that period. When the bit check becomes active, the bit-check counter is clocked with the cycle
T
XClk
.
Figure 5-5 shows how the bit check proceeds if the bit-check counter value CV_Lim is within the
limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In Figure 5-6 , the bit
check fails as the value CV_lim is lower than the limit Lim_min. The bit check also fails if CV_Lim
reaches Lim_max. This is illustrated in
Figure 5-7 .
Figure 5-5. Timing Diagram During Bit Check
Figure 5-6. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
Figure 5-7. Timing Diagram for Failed Bit Check (Condition: CV_Lim
≥
Lim_max)
Bit check
Enable IC
Dem_out
Bit check
counter
0 2 3 4 5 6 2 4 5 1 7 8 1 3 6 7 8 9 11121314 10
1/2 Bit
15161718 1 2 3 4 5 6
(Lim_min = 14, Lim_max = 24)
7 8 9 10 1112131415 1 2 3 4
1/2 Bit 1/2 Bit
Bit check ok Bit check ok
T
Startup
T
XClk
Bit check
Enable IC
Bit check
counter
0
2 3 4 5 6 2 4 5 1 3 6 7 8 9 11 12 10
1/2 Bit
Startup Mode
0
(Lim_min = 14, Lim_max = 24)
Sleep Mode
Bit check failed ( CV_Lim < Lim_min )
Dem_out
Bit check Mode
1
Bit check
Enable IC
Bit check
counter
0
2 3 4 5 6 2 4 5 1 7 3 6 7 8 9 1112 10
1/2 Bit
Startup Mode
20
(Lim_min = 14, Lim_max = 24)
Sleep Mode
Bit check failed (CV_Lim = Lim_max)
13141516171819 21222324 0 1
Dem_out
Bit check Mode