AT91SAM9263-EK Evaluation Board User Guide
6-1
6325D–ATARM–26-Aug-09
Section 6
Warning
6.1
BMS Signal Sampling
The following behavior and its consequences are related to an AT91SAM9263 device issue described in
the Errata section of the
AT91SAM9263 datasheet
(“BMS: BMS does not have correct state”). The text
below is a reminder of this issue and a Workaround proposal at the board level.
Description
The BMS signal, which is multiplexed with the PB3/AC97RX PIO needs to be sampled at a High Level
for the AT91SAM9263 microcontroller to boot out of the internal ROM.
At power up, the on-board AC97 device negates its “SDATA_IN” output pin and due to this fact, the
BMS_PB3/AC97RX pin needs to be isolated during the reset phase.
The MN20 gate, controlled by the NRST signal, achieves this, but with the default ERSTL value in the
reset controller (refer to the RSTC section in the
AT91SAM9263 datasheet
for more details), when the
VDDBU power supply is applied for more than 1.2 seconds before the VDDCORE power supply, the
AT91SAM9263 microcontroller samples the BMS signal one Slow Clock (SLCK) cycle after the NRST
signal rising (See
Figure 6-1
).
As a result, the BMS signal is sampled at a Low Level and the AT91SAM9263 boots out of the external
EBI device connected to NCS0.
