background image

7

6320B–ATARM–05-Nov-07

Application Note

4.2

ECC Controller Preliminary Requirements

In order to calculate ECC properly during write/read and read processes, the following con-
straints must be respected:

• at least 1 Hold time must be programmed in the RWHOLD field of the SMC_CSRx register 

(only AT91SAM7SE family is concerned)

• read/write sequence must start at a page boundary

• read/write accesses must be done through the whole main area since ECC is calculated on 

the main area data

• data accesses must be performed chronologically through the main area

• the appropriate page size must be programmed in the PAGESIZE field of the ECC_MR 

register

4.3

ECC Controller Functional Description

4.3.1

Page Write Sequence

The ECC controller is automatically reset as soon as the first write command (80h) is performed
to the NAND Flash or the SmartMedia device.

The ECC calculation starts only once the required address cycles (the number of address cycles
depends on the device type) is performed to NAND Flash or the SmartMedia device.

The ECC is refreshed at each write access of the page until the last byte or half word of the main
area is written.

Once the whole main area has been written, the final ECC result is available in the ECC Parity
Register (ECC_PR) and ECC NParity Register (ECC_NPR) until a new start condition occurs. It
is up to the software application to write the Parity ECC and NParity ECC in the appropriate loca-
tions of the device spare area.

Please note that apart from data accesses (ALE = CLE = 0), the ECC controller ignores any
other command which is performed to the NAND Flash or the SmartMedia device. 

Figure 4-3

 below illustrates a full page write sequence with ECC calculation.

Figure 4-3.

ECC Calculation During Page Write Sequence without Random Write Spare Area 

I/Ox

Address

Write 

Command 1

Write 

Command 2

Address cycles

ECC Controller

Reset

Main Area Write Accesses

Accesses Allowing ECC calculation

Start of ECC 

Calculation

ECC Result 

Ready in and Locked

Accesses Ignored by the ECC Controller

for ECC calculation

Spare Area ECC locations  

Write Accesses

80h

10h

1st

2nd

...

n th

ECC

ECC

ECC

ECC

Main Area Size

 

Summary of Contents for AT91 ARM Series

Page 1: ...of bad blocks does not affect the good ones because each block is indepen dent and individually isolated from the bit lines by block select transistors Because NAND Flash devices have a finite lifetim...

Page 2: ...in Section 2 1 Internal Array Architecture NAND flash devices contain a certain percentage of invalid blocks at the end of the production process Invalid blocks are defined as blocks that contain one...

Page 3: ...Half Word 7thHalf Word 8thHalf Word BI LSN1 LSN0 LSN2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved ECC0 ECC1 ECC2 S ECC0 S ECC1 Cell Array 512 Bytes Cell Array 512 Bytes Cell Array 5...

Page 4: ...8 bit devices or sixth half word 16 bit devices in the spare area of Small Page devices Manufacturers make sure that every invalid block has non FFh 8 bit devices or non FFFFh 16 bit devices data in...

Page 5: ...e bit correction per 512 1024 2048 4096 8 or 16 bit words Of the 32 ECC bits 26 bits are for line parity and 6 bits are for column parity They are generated according to the schemes shown in Figure 4...

Page 6: ...ARM 05 Nov 07 Application Note Figure 4 2 Parity Generation for 512 1024 2048 4096 16 bit Words 1st word 2nd word 3rd word 4th word Page size 3 th word Page size 2 th word Page size 1 th word Page siz...

Page 7: ...vice type is performed to NAND Flash or the SmartMedia device The ECC is refreshed at each write access of the page until the last byte or half word of the main area is written Once the whole main are...

Page 8: ...CLE 0 the ECC controller ignores any other command which is performed to the NAND Flash or the SmartMedia device The ECC controller performs error detection automatically by applying an XOR operation...

Page 9: ...d Sequence without Random Read Spare Area Main Area Size I Ox Address Read Command 1 Read Command 2 Address Cycles ECC Controller Reset Data Accesses Main Area Read Accesses Accesses allowing ECC calc...

Page 10: ...ytes ECC for 512 bytes of data per page The AT91SAM ECC controller manages ECC as 4 bytes ECC for 512 1024 2048 4096 bytes of data per page Since the ECC offset in the spare area and the number of ECC...

Page 11: ...05 Nov 07 Application Note 7 Revision History Doc Rev Comments Change Request Ref 6320A First issue 6320B Figure 4 3 and Figure 4 4 updated Section 3 2 Spare Area Assignment updated sentence refering...

Page 12: ...ELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIR...

Reviews: