Atmel AT91 ARM Series, Application Note

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2
6320B–ATARM–05-Nov-07
Application Note
The waveforms shown in Figure 2-1 depict the successive accesses: Command Latch, Address
Latch and Data Output. Notice that no command can be sent to the NAND Flash during t
R
due to
it’s busy-state period.
Figure 2-1. Page READ Operation
Please refer to the NAND Flash manufacturer’s datasheet for command sets and full operation
description.
3. Invalid Block Management
3.1 Invalid Block Definition
As mentioned in Section 2.1 ”Internal Array Architecture” , NAND flash devices contain a certain
percentage of invalid blocks at the end of the production process. Invalid blocks are defined as
blocks that contain one or more invalid bits.
3.2 Spare Area Assignment
The invalid block status byte location and the ECC locations within the spare area depend on the
device type (small/large-page devices and 8/16- bit devices).
The widely used spare area assignment defined by SAMSUNG is illustrated in Figure 3-1 , Fig-
ure 3-2 , Figure 3-3 and Figure 3-4 .
t
R
t
REA
t
CEA
ALE
CLE
I/Ox
Address (5 cycles)
Command
cycle 1
Command
cycle 2
Address cycles
00h 30h
WE
RE
CE
R/B
Don't Care