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15

AT90S/LS2323/2343

1004D–09/01

Constant Addressing Using
the LPM Instruction

Figure 18.

Code Memory Constant Addressing

Constant byte address is specified by the Z-register contents. The 15 MSBs select word
address (0 - 1K), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB =
1).

Indirect Program Addressing,
IJMP and ICALL

Figure 19.

Indirect Program Memory Addressing

Program execution continues at address contained by the Z-register (i.e., the PC is
loaded with the contents of the Z-register).

Relative Program Addressing,
RJMP and RCALL

Figure 20.

Relative Program Memory Addressing

Program execution continues at address PC + k + 1. The relative address k is -2048 to
2047.

+1

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Summary of Contents for AT90S2343

Page 1: ... down Modes External and Internal Interrupt Sources Power on Reset Circuit Selectable On chip RC Oscillator Specifications Low power High speed CMOS Process Technology Fully Static Operation Power Consumption at 4 MHz 3V 25 C Active 2 4 mA Idle Mode 0 5 mA Power down Mode 1 µA I O and Packages Three Programmable I O Lines for AT90S LS2323 Five Programmable I O Lines for AT90S LS2343 8 pin PDIP and...

Page 2: ... Arithmetic Logic Unit ALU allowing two independent registers to be accessed in one single instruction executed in one clock cycle The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers Block Diagram Figure 1 The AT90S LS2343 Block Diagram PROGRAM COUNTER INTERNAL OSCILLATOR WATCHDOG TIMER STACK POINTER PROGRAM F...

Page 3: ...functioning The Power down mode saves the register contents but freezes the oscillator disabling all other chip functions until the next interrupt or hardware reset The device is manufactured using Atmel s high density nonvolatile memory technology The On chip Flash allows the program memory to be reprogrammed in system through an SPI serial interface By combining an 8 bit RISC CPU with ISP Flash ...

Page 4: ...ns AT90S LS2323 VCC Supply voltage pin GND Ground pin Port B PB2 PB0 Port B is a 3 bit bi directional I O port with internal pull up resistors The Port B output buffers can sink 20 mA As inputs Port B pins that are externally pulled low will source current if the pull up resistors are activated Port B also serves the functions of various special features Port pins can provide internal pull up resi...

Page 5: ...e Clock Options Crystal Oscillator The AT90S LS2323 contains an inverting amplifier that can be configured for use as an On chip oscillator as shown in Figure 3 XTAL1 and XTAL2 are input and output respectively Either a quartz crystal or a ceramic resonator may be used It is recom mended that the AT90S LS2343 be used if an external clock source is used since this gives an extra I O pin Figure 3 Os...

Page 6: ...6 AT90S LS2323 2343 1004D 09 01 Figure 4 External Clock Drive Configuration GND GND EXTERNAL OSCILATOR SIGNAL EXTERNAL OSCILATOR SIGNAL NC XTAL2 XTAL1 PB3 AT90S LS2323 AT90S LS2343 ...

Page 7: ... registers or between a con stant and a register Single register operations are also executed in the ALU Figure 5 shows the AT90S2323 2343 AVR RISC microcontroller architecture In addition to the register operation the conventional memory addressing modes can be used on the register file as well This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses 00...

Page 8: ...uently the stack size is only limited by the total SRAM size and the usage of the SRAM All user programs must initialize the SP in the reset routine before subroutines or interrupts are executed The 8 bit stack pointer SP is read write accessible in the I O space The 128 bytes data SRAM register file and I O registers can be easily accessed through the five different addressing modes supported in ...

Page 9: ...R16 R31 The general SBC SUB CP AND and OR and all other operations between two registers or on a single register apply to the entire register file As shown in Figure 7 each register is also assigned a data memory address mapping them directly into the first 32 locations of the user Data Space Although the register file is not physically implemented as SRAM locations this memory organization provid...

Page 10: ...hip In System Programmable Flash memory for program storage Since all instructions are 16 or 32 bit words the Flash is organized as 1K x 16 The Flash memory has an endurance of at least 1000 write erase cycles The AT90S2323 2343 Program Counter PC is 10 bits wide hence addressing the 1024 program memory addresses See page 42 for a detailed description on Flash data programming Constant tables must...

Page 11: ...to R31 feature the indirect addressing pointer registers The direct addressing reaches the entire data address space The Indirect with Displacement mode features 63 address locations reached from the base address given by the Y and Z register When using register indirect addressing modes with automatic pre decrement and post increment the address registers X Y and Z are used and decremented and in...

Page 12: ...orted by the AVR architecture In the figures OP means the operation code part of the instruction word To simplify not all figures show the exact location of the addressing bits Register Direct Single Register Rd Figure 10 Direct Single Register Addressing The operand is contained in register d Rd Register Direct Two Registers Rd and Rr Figure 11 Direct Register Addressing Two Registers Operands ar...

Page 13: ...r address Data Direct Figure 13 Direct Data Addressing A 16 bit data address is contained in the 16 LSBs of a 2 word instruction Rd Rr specify the destination or source register Data Indirect with Displacement Figure 14 Data Indirect with Displacement Operand address is the result of the Y or Z register contents added to the address con tained in six bits of the instruction word ...

Page 14: ...t Addressing with Pre decrement The X Y or the Z register is decremented before the operation Operand address is the decremented contents of the X Y or the Z register Data Indirect with Post increment Figure 17 Data Indirect Addressing with Post increment The X Y or the Z register is incremented after the operation Operand address is the content of the X Y or the Z register prior to incrementing 1...

Page 15: ...low byte if cleared LSB 0 or high byte if set LSB 1 Indirect Program Addressing IJMP and ICALL Figure 19 Indirect Program Memory Addressing Program execution continues at address contained by the Z register i e the PC is loaded with the contents of the Z register Relative Program Addressing RJMP and RCALL Figure 20 Relative Program Memory Addressing Program execution continues at address PC k 1 Th...

Page 16: ...nique results for functions per cost functions per clocks and functions per power unit Figure 21 The Parallel Instruction Fetches and Instruction Executions Figure 22 shows the internal timing concept for the register file In a single clock cycle an ALU operation using two register operands is executed and the result is stored back to the destination register Figure 22 Single Cycle ALU Operation T...

Page 17: ...struction set section for more details When using the I O specific commands IN System Clock Ø WR RD Data Data Address Address T1 T2 T3 T4 Prev Address Read Write Table 2 AT90S2323 2343 I O Space Address Hex Name Function 3F 5F SREG Status REGister 3D 5D SPL Stack Pointer Low 3B 5B GIMSK General Interrupt MaSK register 3A 5A GIFR General Interrupt Flag Register 39 59 TIMSK Timer Counter Interrupt M...

Page 18: ...d by hardware after an interrupt has occurred and is set by the RETI instruction to enable subsequent interrupts Bit 6 T Bit Copy Storage The bit copy instructions BLD Bit LoaD and BST Bit STore use the T bit as source and destination for the operated bit A bit from a register in the register file can be copied into T by the BST instruction and a bit in T can be copied into a bit in a register in ...

Page 19: ...nted by 1 when data is popped from the stack with the POP instruction and it is incremented by 2 when an address is popped from the stack with return from subroutine RET or return from interrupt RETI Reset and Interrupt Handling The AT90S2323 2343 provides two interrupt sources These interrupts and the separate reset vector each have a separate program vector in the program memory space Both inter...

Page 20: ...f the program never enables an interrupt source the interrupt vectors are not used and regular program code can be placed at these locations The circuit diagram in Figure 24 shows the reset logic Table 4 defines the timing and electrical parameters of the reset circuitry Figure 24 Reset Logic The AT90S LS2323 has a programmable start up time A fuse bit FSTRT in the Flash memory selects the shortes...

Page 21: ...ncy of the Watchdog oscillator is voltage dependent as shown in Typical Characteristics on page 49 Table 4 Reset Characteristics VCC 5 0V Symbol Parameter Min Typ Max Units VPOT 1 Power on Reset Threshold Voltage rising 1 0 1 4 1 8 V Power on Reset Threshold Voltage falling 0 4 0 6 0 8 V VRST RESET Pin Threshold Voltage 0 6 VCC V tTOUT Reset Delay Time out Period AT90S LS2323 FSTRT Programmed 1 0 ...

Page 22: ... than 50 ns will generate a reset even if the clock is not running Shorter pulses are not guaranteed to generate a reset When the applied signal reaches the Reset Threshold Voltage VRST on its positive edge the delay timer starts the MCU after the Time out period tTOUT has expired Figure 27 External Reset during Operation VCC RESET TIME OUT INTERNAL RESET tTOUT VPOT VRST VCC RESET TIME OUT INTERNA...

Page 23: ...l leave this bit unchanged Bit 0 PORF Power on Reset Flag This bit is set by a Power on Reset A Watchdog Reset or an External Reset will leave this bit unchanged To summarize Table 7 shows the value of these two bits after the three modes of reset To make use of these bits to identify a reset condition the user software should clear both the PORF and EXTRF bits as early as possible in the program ...

Page 24: ...der of priority Note that external level interrupt does not have a flag and will only be remembered for as long as the interrupt condition is active Note that the Status Register is not automatically stored when entering an interrupt rou tine and restored when returning from an interrupt routine This must be handled by software General Interrupt Mask Register GIMSK Bit 7 Res Reserved Bit This bit ...

Page 25: ...tus Register is set one the Timer Counter0 Overflow interrupt is enabled The corresponding interrupt at vector 002 is executed if an overflow in Timer Counter0 occurs i e when the Overflow Flag Timer Counter0 is set one in the Timer Counter Interrupt Flag Register TIFR Bit 0 Res Reserved Bit This bit is a reserved bit in the AT90S2323 2343 and always reads as zero Timer Counter Interrupt FLAG Regi...

Page 26: ...erved A return from an interrupt handling routine same as for a subroutine call routine takes four clock cycles During these four clock cycles the Program Counter 2 bytes is popped back from the stack and the Stack Pointer is incremented by 2 When the AVR exits from an interrupt it will always return to the main program and execute one more instruction before any pending interrupt is served MCU Co...

Page 27: ...ces the MCU into the Power down mode In this mode the external oscillator is stopped while the external interrupts and the Watchdog if enabled continue operating Only an external reset a Watchdog reset if enabled or an external level interrupt on INT0 can wake up the MCU Note that if a level triggered interrupt is used for wake up from Power down mode the changed level must be held for some time t...

Page 28: ...fication for the Timer Counter0 Control Register TCCR0 The overflow status flag is found in the Timer Counter Interrupt Flag Register TIFR Control signals are found in the Timer Counter0 Control Register TCCR0 The interrupt enable disable settings for Timer Counter0 are found in the Timer Counter Interrupt Mask Register TIMSK When Timer Counter0 is externally clocked the external signal is synchro...

Page 29: ...Select0 Bits 2 1 and 0 The Clock Select0 bits 2 1 and 0 define the prescaling source of Timer Counter0 T0 Bit 7 6 5 4 3 2 1 0 33 53 CS02 CS01 CS00 TCCR0 Read Write R R R R R R W R W R W Initial Value 0 0 0 0 0 0 0 0 Table 10 Clock 0 Prescale Select CS02 CS01 CS00 Description 0 0 0 Stop the Timer Counter0 is stopped 0 0 1 CK 0 1 0 CK 8 0 1 1 CK 64 1 0 0 CK 256 1 0 1 CK 1024 1 1 0 External Pin T0 fa...

Page 30: ...ip oscillator By controlling the Watchdog Timer prescaler the Watchdog reset interval can be adjusted as shown in Table 11 See characterization data for typical values at other VCC levels The WDR Watchdog Reset instruction resets the Watchdog Timer Eight different clock cycle periods can be selected to determine the reset period If the reset period expires without another Watchdog reset the AT90S2...

Page 31: ...WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled The different prescaling values and their corresponding time out periods are shown in Table 11 Note The frequency of the Watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section The WDR Watchdog Reset instruction should always be executed before the Watchdog Timer is ena...

Page 32: ...PROM Address Register EEAR Bit 7 Res Reserved Bit This bit is a reserved bit in the AT90S2323 2343 and will always read as zero Bit 6 0 EEAR6 0 EEPROM Address The EEPROM Address Register EEAR6 0 specifies the EEPROM address in the 128 byte EEPROM space The EEPROM data bytes are addressed linearly between 0 and 127 EEPROM Data Register EEDR Bits 7 0 EEDR7 0 EEPROM Data For the EEPROM write operatio...

Page 33: ...1 to EEWE Caution An interrupt between step 4 and step 5 will make the write cycle fail since the EEPROM Master Write Enable will time out If an interrupt routine accessing the EEPROM is interrupting another EEPROM access the EEAR and EEDR registers will be modified causing the interrupted EEPROM access to fail It is recommended to have the global interrupt flag cleared during the four last steps ...

Page 34: ...EEPROM data corruption can easily be avoided by following these design recommen dations one is sufficient 1 Keep the AVR RESET active low during periods of insufficient power supply voltage This is best done by an external low VCC Reset Protection circuit often referred to as a Brown out Detector BOD Please refer to application note AVR 180 for design considerations regarding power on reset and lo...

Page 35: ...tion Register are read write All port pins have individually selectable pull up resistors The Port B output buffers can sink 20 mA and thus drive LED displays directly When pins PB0 to PB4 are used as inputs and are externally pulled low they will source current if the internal pull up resis tors are activated The Port B pins with alternate functions are shown in Table 12 When the pins are used fo...

Page 36: ...device runs from the internal RC oscillator this pin is a general I O pin When the RCEN fuse is unprogrammed an external clock source must be connected to CLOCK SCK T0 Port B Bit 2 In Serial Programming mode this bit serves as the serial clock input SCK During normal operation this pin can serve as the external counter clock input See the timer counter description for further details If external t...

Page 37: ...e bits SPIEN and RCEN When the SPIEN Fuse is programmed 0 Serial Program and Data Downloading are enabled Default value is programmed 0 This bit is not accessible in the low voltage Serial Programming mode When the RCEN Fuse is programmed 0 the internal RC oscillator is selected as the MCU clock source Default value is programmed 0 in AT90LS2343 1 Default value is un programmed 1 in AT90LS2343 4 a...

Page 38: ...g mode provides a convenient way to download program and data into the device inside the user s system The program and EEPROM memory arrays in the AT90S2323 2343 are programmed byte by byte in either programming modes For the EEPROM an auto erase cycle is provided within the self timed write instruction in the low voltage Serial Programming mode During programming the supply voltage must be in acc...

Page 39: ...ogrammed one byte at a time by supplying first the address then the low and high data bytes The write instruction is self timed wait until the PB2 RDY BSY pin goes high 3 The EEPROM array is programmed one byte at a time by supplying first the address then the data byte The write instruction is self timed wait until the PB2 RDY BSY pin goes high 4 Any memory location can be verified by using the R...

Page 40: ... each new address Read Flash High Byte PB0 PB1P B2 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 o_oooo_ooox_xx Repeat Instr 1 and Instr 2 for each new address Write EEPROM Low Address PB0 PB1 PB2 0_0001_0001_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0bbb_bbbb_00 0_0000_1100_00 x_xxxx_xxxx_xx Repeat Instr 2 for each new address Write EEPROM Byte PB0 PB1 PB2 0_ i i i i_i i i i...

Page 41: ...its AT90S LS2343 PB0 PB1 PB2 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 1_2Sxx_xxRx_xx Reading 1 2 S R 0 means the Fuse Lock bit is programmed Read Signature Bytes PB0 PB1 PB2 0_0000_1000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_00bb_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_...

Page 42: ...age Serial Programming and Verify Table 17 High voltage Serial Programming Characteristics TA 25 C 10 VCC 5 0V 10 unless otherwise noted Symbol Parameter Min Typ Max Units tSHSL SCI XTAL1 PB3 Pulse Width High 100 0 ns tSLSH SCI XTAL1 PB3 Pulse Width Low 100 0 ns tIVSH SDI PB0 SII PB1 Valid to SCI XTAL1 PB3 High 50 0 ns tSHIX SDI PB0 SII PB1 Hold after SCI XTAL1 PB3 High 50 0 ns tSHOV SCI XTAL1 PB3...

Page 43: ...e internal RC oscillator is selected as the clock source no external clock source needs to be applied AT90S LS2343 only 2 Wait for at least 20 ms and enable serial programming by sending the Program ming Enable serial instruction to the MOSI PB0 pin Refer to the above section for minimum low and high periods for the serial clock input SCK 3 The serial programming instructions will not work if the ...

Page 44: ...G value As a chip erased device contains FF in all locations programming of addresses that are meant to contain FF can be skipped This does not apply if the EEPROM is reprogrammed without first chip erasing the device Data Polling Flash When a byte is being programmed into the Flash reading the address location being programmed will give the value FF At the time the device is ready for a new byte ...

Page 45: ... address a b Write Program Memory 0100 H000 0000 00aa bbbb bbbb iiii iiii Write H high or low data i to program memory at word address a b Read EEPROM Memory 1010 0000 0000 0000 xbbb bbbb oooo oooo Read data o from EEPROM memory at address b Write EEPROM Memory 1100 0000 0000 0000 xbbb bbbb iiii iiii Write data i to EEPROM memory at address b Read Lock and Fuse Bits AT90S LS2323 0101 1000 xxxx xxx...

Page 46: ...llator Frequency VCC 4 0 6 0V 0 8 0 MHz tCLCL Oscillator Period VCC 4 0 6 0V 125 0 ns tSHSL SCK Pulse Width High 2 0 tCLCL ns tSLSH SCK Pulse Width Low 2 0 tCLCL ns tOVSH MOSI Setup to SCK High tCLCL ns tSHOX MOSI Hold after SCK High 2 0 tCLCL ns tSLIV SCK Low to MISO Valid 10 0 16 0 32 0 ns Table 21 Minimum Wait Delay after the Chip Erase Instruction Symbol 3 2V 3 6V 4 0V 5 0V tWD_ERASE 18 ms 14 ...

Page 47: ...DC Current VCC and GND Pins 200 0 mA DC Characteristics TA 40 C to 85 C VCC 2 7V to 6 0V unless otherwise noted Symbol Parameter Condition Min Typ Max Units VIL Input Low Voltage Except XTAL 0 5 0 3 VCC 1 V VIL1 Input Low Voltage XTAL 0 5 0 1 1 V VIH Input High Voltage Except XTAL RESET 0 6 VCC 2 VCC 0 5 V VIH1 Input High Voltage XTAL 0 7 VCC 2 VCC 0 5 V VIH2 Input High Voltage RESET 0 85 VCC 2 VC...

Page 48: ...k Drive TA 40 C to 85 C Symbol Parameter VCC 2 7V to 4 0V VCC 4 0V to 6 0V Units Min Max Min Max 1 tCLCL Oscillator Frequency 0 4 0 0 10 0 MHz tCLCL Clock Period 250 0 100 0 ns tCHCX High Time 100 0 40 0 ns tCLCX Low Time 100 0 40 0 ns tCLCH Rise Time 1 6 0 5 µs tCHCL Fall Time 1 6 0 5 µs VIL1 VIH1 ...

Page 49: ...m capacitive loaded pins may be estimated for one pin as CL VCC f where CL load capacitance VCC operating voltage and f average switch ing frequency of I O pin The parts are characterized at frequencies higher than test limits Parts are not guaran teed to function properly at frequencies higher than the ordering code indicates The difference between current consumption in Power down mode with Watc...

Page 50: ...Supply Current vs VCC 0 1 2 3 4 5 6 7 8 9 10 2 2 5 3 3 5 4 4 5 5 5 5 6 ACTIVE SUPPLY CURRENT vs Vcc FREQUENCY 4 MHz I cc mA Vcc V T 25 C A T 85 C A ACTIVE SUPPLY CURRENT vs Vcc DEVICE CLOCKED BY INTERNAL RC OSCILLATOR I cc mA Vcc V 0 1 2 3 4 5 6 7 2 2 5 3 3 5 4 4 5 5 5 5 6 T 25 C A T 85 C A ...

Page 51: ...1 1 5 2 2 5 3 3 5 4 4 5 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Vcc 6V Vcc 5 5V Vcc 5V Vcc 4 5V Vcc 4V Vcc 3 6V Vcc 3 3V Vcc 3 0V Vcc 2 7V IDLE SUPPLY CURRENT vs FREQUENCY T 25 C A Frequency MHz I cc mA 0 0 5 1 1 5 2 2 5 2 2 5 3 3 5 4 4 5 5 5 5 6 T 25 C A T 85 C A IDLE SUPPLY CURRENT vs Vcc I cc mA Vcc V FREQUENCY 4 MHz ...

Page 52: ...CC 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 2 2 5 3 3 5 4 4 5 5 5 5 6 T 25 C A T 85 C A IDLE SUPPLY CURRENT vs Vcc I cc mA Vcc V DEVICE CLOCKED BY INTERNAL RC OSCILLATOR T 85 C A T 25 C A POWER DOWN SUPPLY CURRENT vs Vcc I cc µΑ Vcc V WATCHDOG TIMER DISABLED T 45 C A T 70 C A 0 5 10 15 20 25 2 2 5 3 3 5 4 4 5 5 5 5 6 ...

Page 53: ...tor Frequency vs VCC 0 20 40 60 80 100 120 140 160 180 2 2 5 3 3 5 4 4 5 5 5 5 6 T 85 C A POWER DOWN SUPPLY CURRENT vs Vcc I cc µΑ Vcc V WATCHDOG TIMER ENABLED T 25 C A 0 200 400 600 800 1000 1200 1400 1600 2 2 5 3 3 5 4 4 5 5 5 5 6 T 85 C A T 25 C A WATCHDOG OSCILLATOR FREQUENCY vs Vcc V V cc F KHz RC ...

Page 54: ...or Current vs Input Voltage Figure 49 Pull up Resistor Current vs Input Voltage 0 20 40 60 80 100 120 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 PULL UP RESISTOR CURRENT vs INPUT VOLTAGE V 5V cc I µA OP V V OP T 85 C A T 25 C A 0 5 10 15 20 25 30 0 0 5 1 1 5 2 2 5 3 PULL UP RESISTOR CURRENT vs INPUT VOLTAGE I µA OP V V OP V 2 7V cc T 85 C A T 25 C A ...

Page 55: ...n Source Current vs Output Voltage 0 10 20 30 40 50 60 70 0 0 5 1 1 5 2 2 5 3 V 5V cc I mA OL V V OL T 85 C A T 25 C A I O PIN SINK CURRENT vs OUTPUT VOLTAGE 0 2 4 6 8 10 12 14 16 18 20 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 I O PIN SOURCE CURRENT vs OUTPUT VOLTAGE V 5V cc I mA OH V V OH T 85 C A T 25 C A ...

Page 56: ...e Figure 53 I O Pin Source Current vs Output voltage 0 5 10 15 20 25 0 0 5 1 1 5 2 I mA OL V V OL T 85 C A T 25 C A I O PIN SINK CURRENT vs OUTPUT VOLTAGE V 2 7V cc 0 1 2 3 4 5 6 0 0 5 1 1 5 2 2 5 3 I O PIN SOURCE CURRENT vs OUTPUT VOLTAGE I mA OH V V OH T 85 C A T 25 C A V 2 7V cc ...

Page 57: ...e vs VCC Figure 55 I O Pin Input Hysteresis vs VCC 0 0 5 1 1 5 2 2 5 2 7 4 0 5 0 Threshold Voltage V Vcc I O PIN INPUT THRESHOLD VOLTAGE vs Vcc T 25 C A 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 0 18 2 7 4 0 5 0 Input hysteresis V Vcc I O PIN INPUT HYSTERESIS vs Vcc T 25 C A ...

Page 58: ...5A GIFR INTF0 page 25 39 59 TIMSK TOIE0 page 25 38 58 TIFR TOV0 page 25 37 57 Reserved 36 56 Reserved 35 55 MCUCR SE SM ISC01 ISC00 page 26 34 54 MCUSR EXTRF PORF page 23 33 53 TCCR0 CS02 CS01 CS00 page 29 32 52 TCNT0 Timer Counter0 8 Bits page 30 31 51 Reserved 30 50 Reserved 2F 4F Reserved 2E 4E Reserved 2D 4D Reserved 2C 4C Reserved 2B 4B Reserved 2A 4A Reserved 29 49 Reserved 28 48 Reserved 27...

Page 59: ...al if Rd Rr PC PC 2 or 3 None 1 2 3 CP Rd Rr Compare Rd Rr Z N V C H 1 CPC Rd Rr Compare with Carry Rd Rr C Z N V C H 1 CPI Rd K Compare Register with Immediate Rd K Z N V C H 1 SBRC Rr b Skip if Bit in Register Cleared if Rr b 0 PC PC 2 or 3 None 1 2 3 SBRS Rr b Skip if Bit in Register is Set if Rr b 1 PC PC 2 or 3 None 1 2 3 SBIC P b Skip if Bit in I O Register Cleared if P b 0 PC PC 2 or 3 None...

Page 60: ... Rd P None 1 OUT P Rr Out Port P Rr None 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 BIT AND BIT TEST INSTRUCTIONS SBI P b Set Bit in I O Register I O P b 1 None 2 CBI P b Clear Bit in I O Register I O P b 0 None 2 LSL Rd Logical Shift Left Rd n 1 Rd n Rd 0 0 Z C N V 1 LSR Rd Logical Shift Right Rd n Rd n 1 Rd 7 0 Z C N V 1 ROL Rd Rotate Left thr...

Page 61: ...Operation Range 2 7 6 0V 4 AT90LS2323 4PC AT90LS2323 4SC 8P3 8S2 Commercial 0 C to 70 C AT90LS2323 4PI AT90LS2323 4SI 8P3 8S2 Industrial 40 C to 85 C 4 0 6 0V 10 AT90S2323 10PC AT90S2323 10SC 8P3 8S2 Commercial 0 C to 70 C AT90S2323 10PI AT90S2323 10SI 8P3 8S2 Industrial 40 C to 85 C 2 7 6 0V 1 AT90LS2343 1PC AT90LS2343 1SC 8P3 8S2 Commercial 0 C to 70 C AT90LS2343 1PI AT90LS2343 1SI 8P3 8S2 Indus...

Page 62: ... 015 MIN 0 559 0 022 0 356 0 014 3 81 0 150 2 92 0 115 1 78 0 070 1 14 0 045 8 26 0 325 7 62 0 300 10 90 0 430 MAX 0 356 0 014 0 203 0 008 4 95 0 195 2 92 0 115 Seating Plane Controlling dimension Inches 8P3 8 lead Plastic Dual Inline Package PDIP 0 300 Wide Dimensions in Millimeters and Inches JEDEC STANDARD MS 001 BA 1 524 0 060 0 000 0 000 REV A 04 11 2001 ...

Page 63: ...63 AT90S LS2323 2343 1004D 09 01 8S2 020 508 012 305 213 5 41 205 5 21 330 8 38 300 7 62 PIN 1 050 1 27 BSC 212 5 38 203 5 16 080 2 03 070 1 78 013 330 004 102 0 8 REF 010 254 007 178 035 889 020 508 ...

Page 64: ...41 26 426 5555 FAX 41 26 426 5500 Asia Atmel Asia Ltd Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL 852 2721 9778 FAX 852 2722 1369 Japan Atmel Japan K K 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan TEL 81 3 3523 3551 FAX 81 3 3523 7581 Atmel Colorado Springs 1150 E Cheyenne Mtn Blvd Colorado Springs CO 80906 TEL 719 576 3300 FAX 719 5...

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