294
4317I–AVR–01/08
AT90PWM2/3/2B/3B
Notes:
1. t
WLRH
is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
commands.
2. t
WLRH_CE
is valid for the Chip Erase command.
25.9
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in
, the pin
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.
t
XLPH
XTAL1 Low to PAGEL high
0
ns
t
PLXH
PAGEL low to XTAL1 high
150
ns
t
BVPH
BS1 Valid before PAGEL High
67
ns
t
PHPL
PAGEL Pulse Width High
150
ns
t
PLBX
BS1 Hold after PAGEL Low
67
ns
t
WLBX
BS2/1 Hold after WR Low
67
ns
t
PLWL
PAGEL Low to WR Low
67
ns
t
BVWL
BS1 Valid to WR Low
67
ns
t
WLWH
WR Pulse Width Low
150
ns
t
WLRL
WR Low to RDY/BSY Low
0
1
μ
s
t
WLRH
WR Low to RDY/BSY High
3.7
4.5
ms
t
WLRH_CE
WR Low to RDY/BSY High for Chip Erase
7.5
9
ms
t
XLOL
XTAL1 Low to OE Low
0
ns
t
BVDV
BS1 Valid to DATA valid
0
250
ns
t
OLDV
OE Low to DATA Valid
250
ns
t
OHDZ
OE High to DATA Tri-stated
250
ns
Table 25-14. Parallel Programming Characteristics, V
CC
= 5V ± 10% (Continued)
Symbol
Parameter
Min
Typ
Max
Units
