AT43301
8
An IN Token packet from the host to Endpoint 1 indicates a
request for port change status. If the hub has not detected
any change on its ports, or any changes in itself, then all
bits in this register will be 0 and the Hub Controller will
return a NAK to requests on Endpoint1. If any of bits 0-4 is
1, the Hub Controller will transfer the whole byte. The Hub
Controller will continue to report a status change when
polled until that particular change has been removed by a
ClearPortFeature request from the Host. No status change
will be reported by Endpoint 1 until the AT43301 has been
enumerated and configured by the host.
Oscillator and Phase-Locked-Loop
All the clock signals required to run the AT43301 are
derived from an on-chip oscillator. To reduce EMI and
power dissipation in the system, the AT43301 is designed
to operate with a 6 MHz crystal. An on-chip PLL generates
the high frequency for the clock/data separator of the Serial
Interface Engine. In the suspended state, the oscillator cir-
cuitry is turned off. To assure quick startup, a crystal with a
high Q, or low ESR, should be used. To meet the USB hub
frequency accuracy and stability requirements for hubs, the
crystal should have an accuracy and stability of better than
100 ppm. Even though the oscillator circuit would work with
a ceramic resonator, its use is not recommended because
a resonator would not have the frequency accuracy and
stability.
A 6 MHz series resonance quartz crystal with a load capac-
itance of approximately 10 pF is recommended. The oscil-
lator is a special low-power design and in most cases no
external capacitors and resistors are necessary. If the crys-
tal used cannot tolerate the drive levels of the oscillator, a
series resistor between OSC2 and the crystal pin is recom-
mended.
Status Pin
The status pin, STAT, is provided to allow feedback to the
user. If an LED and a series resistor is connected between
STAT and VCC, the LED will light when the hub is enumer-
ated. During an overcurrent condition, the LED will blink. It
will continue to blink until the host turns off the power to the
ports or until the hub is re-enumerated.
Figure 4. External Oscillator and PLL Circuit
The clock can also be externally sourced. In this case, con-
nect the clock source to the OSC1 pin, while leaving OSC2
pin floating. The switching level at the OSC1 pin can be as
low as 0.47V (see “Electrical Specification” on page 9) and
a CMOS device is required to drive this pin to maintain
good noise margins at the low switching level.
For proper operation of the PLL, an external RC filter con-
sisting of a series RC network of 100
Ω
and 10 nF in parallel
with a 2 nF capacitor must be connected from the LFT pin
to V
SS
.
Power Supply
The AT43301 is powered from the USB bus, but has an
internal voltage regulator to supply the 3.3V operating
power to its circuitry. For proper operation, an external high
quality, low ESR, 0.27 µF, or larger, capacitor should be
connected to the output of the regulator, CEXT1 and
ground. The CEXT1 pin can also be used to supply the
voltage to the 1.5 k
Ω
pull up resistor at Port 0’s DP pin.
To provide the best operating condition for the AT43301,
careful consideration of the power supply connections are
recommended. Use short, low impedance connections to
all power supply lines: V
CC
and V
SS
. Use sufficient decou-
pling capacitance to reduce noise: 0.1 µF of high quality
ceramic capacitor soldered as close as possible to the VCC
and VSS package pins are recommended.
AT43301
OSC1
OSC2
LFT
Y1
6.000 MHz
R1
100
C1
10nF
C2
2nF
U1
