9
32072H–AVR32–10/2012
AT32UC3A3
3.2
Peripheral Multiplexing on I/O lines
3.2.1
Multiplexed Signals
Each GPIO line can be assigned to one of the peripheral functions. The following table
describes the peripheral signals multiplexed to the GPIO lines.
Note that GPIO 44 is physically implemented in silicon but it must be kept unused and config-
ured in input mode.
Table 3-1.
GPIO Controller Function Multiplexing
BGA
144
QFP
144
BGA
100
PIN
G
P
I
O
Supply
PIN
Type
GPIO function
A
B
C
D
G11
122
G8
PA00
0
VDDIO
x3
USART0 - RTS
TC0 - CLK1
SPI1 - NPCS[3]
G12
123
G10
PA01
1
VDDIO
x1
USART0 - CTS
TC0 - A1
USART2 - RTS
D8
15
E1
PA02
2
VDDIO
x1
USART0 - CLK
TC0 - B1
SPI0 - NPCS[0]
G10
125
F9
PA03
3
VDDIO
x1
USART0 - RXD
EIC - EXTINT[4]
ABDAC - DATA[0]
F9
126
E9
PA04
4
VDDIO
x1
USART0 - TXD
EIC - EXTINT[5]
ABDAC - DATAN[0]
F10
124
G9
PA05
5
VDDIO
x1
USART1 - RXD
TC1 - CLK0
USB - ID
F8
127
E8
PA06
6
VDDIO
x1
USART1 - TXD
TC1 - CLK1
USB - VBOF
E10
133
PA07
7
VDDIO
x1
SPI0 - NPCS[3]
ABDAC - DATAN[0]
USART1 - CLK
C11
137
F8
PA08
8
VDDIO
x3
SPI0 - SPCK
ABDAC - DATA[0]
TC1 - B1
B12
139
D8
PA09
9
VDDIO
x2
SPI0 - NPCS[0]
EIC - EXTINT[6]
TC1 - A1
C12
138
C10
PA10
10
VDDIO
x2
SPI0 - MOSI
USB - VBOF
TC1 - B0
D10
136
C9
PA11
11
VDDIO
x2
SPI0 - MISO
USB - ID
TC1 - A2
E12
132
G7
PA12
12
VDDIO
x1
USART1 - CTS
SPI0 - NPCS[2]
TC1 - A0
F11
129
E8
PA13
13
VDDIO
x1
USART1 - RTS
SPI0 - NPCS[1]
EIC - EXTINT[7]
J6
100
K7
PA14
14
VDDIO
x1
SPI0 - NPCS[1]
TWIMS0 - TWALM
TWIMS1 - TWCK
J7
101
J7
PA15
15
VDDIO
x1
MCI - CMD[1]
SPI1 - SPCK
TWIMS1 - TWD
F12
128
E7
PA16
16
VDDIO
x1
MCI - DATA[11]
SPI1 - MOSI
TC1 - CLK2
H7
116
G10
PA17
17
VDDANA
x1
MCI - DATA[10]
SPI1 - NPCS[1]
ADC - AD[7]
K8
115
G8
PA18
18
VDDANA
x1
MCI - DATA[9]
SPI1 - NPCS[2]
ADC - AD[6]
J8
114
H10
PA19
19
VDDANA
x1
MCI - DATA[8]
SPI1 - MISO
ADC - AD[5]
J9
113
H9
PA20
20
VDDANA
x1
EIC - NMI
SSC - RX_FRAME_SYNC
ADC - AD[4]
H9
109
K10
PA21
21
VDDANA
x1
ADC - AD[0]
EIC - EXTINT[0]
USB - ID
H10
110
H6
PA22
22
VDDANA
x1
ADC - AD[1]
EIC - EXTINT[1]
USB - VBOF
G8
111
G6
PA23
23
VDDANA
x1
ADC - AD[2]
EIC - EXTINT[2]
ABDAC - DATA[1]
G9
112
J10
PA24
24
VDDANA
x1
ADC - AD[3]
EIC - EXTINT[3]
ABDAC - DATAN[1]
E9
119
G7
PA25
25
VDDIO
x1
TWIMS0 - TWD
TWIMS1 - TWALM
USART1 - DCD
D9
120
F7
PA26
26
VDDIO
x1
TWIMS0 - TWCK
USART2 - CTS
USART1 - DSR
A4
26
A2
PA27
27
VDDIO
x2
MCI - CLK
SSC - RX_DATA
USART3 - RTS
MSI - SCLK
A3
28
A1
PA28
28
VDDIO
x1
MCI - CMD[0]
SSC - RX_CLOCK
USART3 - CTS
MSI - BS
A6
23
B4
PA29
29
VDDIO
x1
MCI - DATA[0]
USART3 - TXD
TC0 - CLK0
MSI - DATA[0]
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...