563
32072H–AVR32–10/2012
AT32UC3A3
The DTR pin is controlled by the DTR enable and disable bits in CR (CR.DTREN and
CR.DTRDIS). Writing a one to CR.DTRDIS drives DTR high, and writing a one to CR.DTREN
drives DTR low. The RTS pin is controlled automatically.
Detected level changes are reported by the respective Input Change bits in CSR (CSR.RIIC,
CSR.DSRIC, CSR.DCDIC, and CSR.CTSIC). An interrupt request is generated if the corre-
sponding bit in the Interrupt Mask Register is set. The Input Change bits in CSR are
automatically cleared when CSR is read. When the CTS pin goes high, the USART will wait for
the transmitter to complete any ongoing character transmission before automatically disabling it.
25.6.8
ISO7816 Mode
The USART features an ISO7816 compatible mode, enabling interfacing with smart cards and
Security Access Modules (SAM) through an ISO7816 compliant link. T=0 and T=1 protocols, as
defined in the ISO7816 standard, are supported. The ISO7816 mode is selected by writing the
value 0x4 (T=0 protocol) or 0x6 (T=1 protocol) to MR.MODE.
25.6.8.1
ISO7816 Mode Overview
ISO7816 specifies half duplex communication on one bidirectional line. The baud rate is a frac-
tion of the clock provided by the master on the CLK pin (see
). The USART connects to a smart card as shown in
. The TXD pin is bidirec-
tional and is routed to the receiver when the transmitter is disabled. Having both receiver and
transmitter enabled simultaneously may lead to unpredictable results.
Figure 25-20. USART (Master) Connected to a Smart Card
In both T=0 and T=1 modes, the character format is fixed to eight data bits, and one or two stop
bits, regardless of CHRL, MODE9, and CHMODE values. Parity according to specification is
even. If the inverse transmission format is used, where payload data bits are transmitted
inverted on the I/O line, the user can use odd parity and perform an XOR on data headed to
THR and coming from RHR.
25.6.8.2
Baud Rate in ISO 7816 Mode
The ISO7816 specification defines the bit rate with the following formula:
where:
DSR
6
107
From terminal to modem
DCD
8
109
From terminal to modem
RI
22
125
From terminal to modem
Table 25-8.
Circuit References
USART Pin
V.24
CCITT
Direction
CLK
TXD
USART
CLK
I/O
Smart
Card
B
Di
Fi
------
f
×
=
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
