Atmel AT32UC3A3128, Manual

Page: 199 / 1021

199
32072H–AVR32–10/2012
AT32UC3A3
15.6.6.2 TDF optimization enabled (MODE.TDFMODE = 1)
When the MODE.TDFMODE bit is written to one (TDF optimization is enabled), the SMC takes
advantage of the setup period of the next access to optimize the number of wait states cycle to
insert.
Figure 15-21 on page 199 shows a read access controlled by NRD, followed by a write access
controlled by NWE, on Chip Select 0. Chip Select 0 has been programmed with:
NRDHOLD = 4; READMODE = 1 (NRD controlled)
NWESETUP = 3; WRITEMODE = 1 (NWE controlled)
TDFCYCLES = 6; TDFMODE = 1 (optimization enabled).
Figure 15-21. TDF Optimization: No TDF Wait States Are Inserted if the TDF Period Is over when the Next Access Begins
15.6.6.3 TDF optimization disabled (MODE.TDFMODE = 0)
When optimization is disabled, data float wait states are inserted at the end of the read transfer,
so that the data float period is ended when the second access begins. If the hold period of the
read1 controlling signal overlaps the data float period, no additional data float wait states will be
inserted.
Figure 15-22 on page 200 , Figure 15-23 on page 200 and Figure 15-24 on page 201 illustrate
the cases:
• read access followed by a read access on another chip select.
• read access followed by a write access on another chip select.
CLK_SMC
A[AD_MSB:2]
NRD
NWE
NCS0
D[15:0]
Read access on NCS0 (NRD controlled)
Read to Write
Wait State
Write access on NCS0 (NWE controlled)
TDFCYCLES = 6
NWESETUP = 3
NRDHOLD = 4