181
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-3. Memory Connections for Six External Devices
15.6.3
Connection to External Devices
15.6.3.1
Data bus width
A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by
the Data Bus Width field in the Mode Register (MODE.DBW) for the corresponding chip select.
shows how to connect a 512K x 8-bit memory on NCS2.
shows how to connect a 512K x 16-bit memory on NCS2.
15.6.3.2
Byte write or byte select access
Each chip select with a 16-bit data bus can operate with one of two different types of write
access: byte write or byte select access. This is controlled by the Byte Access Type bit in the
MODE register (MODE.BAT) for the corresponding chip select.
Figure 15-4. Memory Connection for an 8-bit Data Bus
NCS[0] - NCS[5]
NRD
NWE
A[AD_MSB:0]
D[15:0]
SMC
NCS5
NCS4
NCS3
NCS2
NCS1
NCS0
8 or 16
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Output Enable
Write Enable
A[AD_MSB:0]
D[15:0] or D[7:0]
SMC
A0
NWE
NRD
NCS[2]
A0
Write Enable
Output Enable
Memory Enable
D[7:0]
D[7:0]
A[18:2]
A[18:2]
A1
A1
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...