Atmel AT32UC3A3128, Manual

Page: 149 / 1021

149
32072H–AVR32–10/2012
AT32UC3A3
13. HSB Bus Matrix (HMATRIX)
Rev: 2.3.0.2
13.1 Features
•
User Interface on peripheral bus
•
Configurable Number of Masters (Up to sixteen)
•
Configurable Number of Slaves (Up to sixteen)
•
One Decoder for Each Master
•
•
Programmable Arbitration for Each Slave
– Round-Robin
– Fixed Priority
•
Programmable Default Master for Each Slave
– No Default Master
– Last Accessed Default Master
– Fixed Default Master
•
One Cycle Latency for the First Access of a Burst
•
Zero Cycle Latency for Default Master
•
One Special Function Register for Each Slave (Not dedicated)
13.2 Overview
The Bus Matrix implements a multi-layer bus structure, that enables parallel access paths
between multiple High Speed Bus (HSB) masters and slaves in a system, thus increasing the
overall bandwidth. The Bus Matrix interconnects up to 16 HSB Masters to
up to 16 HSB Slaves.
The normal latency to connect a master to a slave is one cycle except for the default master of
the accessed slave which is connected directly (zero cycle latency). The Bus Matrix provides 16
Special Function Registers (SFR) that allow the Bus Matrix to support application specific
features.
13.3 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
13.3.1 Clocks
The clock for the HMATRIX bus interface (CLK_HMATRIX) is generated by the Power Manager.
This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to
disable the HMATRIX before disabling the clock, to avoid freezing the HMATRIX in an undefined
state.
13.4 Functional Description
13.4.1 Special Bus Granting Mechanism
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access
requests from some masters. This mechanism reduces latency at first access of a burst or single
transfer. This bus granting mechanism sets a different default master for every slave.