100
32072H–AVR32–10/2012
AT32UC3A3
10.6
User Interface
Table 10-1.
INTC Register Memory Map
Offset
Register
Register Name
Access
Reset
0x000
Interrupt Priority Register 0
IPR0
Read/Write
0x00000000
0x004
Interrupt Priority Register 1
IPR1
Read/Write
0x00000000
...
...
...
...
...
0x0FC
Interrupt Priority Register 63
IPR63
Read/Write
0x00000000
0x100
Interrupt Request Register 0
IRR0
Read-only
N/A
0x104
Interrupt Request Register 1
IRR1
Read-only
N/A
...
...
...
...
...
0x1FC
Interrupt Request Register 63
IRR63
Read-only
N/A
0x200
Interrupt Cause Register 3
ICR3
Read-only
N/A
0x204
Interrupt Cause Register 2
ICR2
Read-only
N/A
0x208
Interrupt Cause Register 1
ICR1
Read-only
N/A
0x20C
Interrupt Cause Register 0
ICR0
Read-only
N/A
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...