2-14
Chapter 2: BIOS information
The following sub-items appear when the item Configure DRAM Timing by
SPD is set to Disabled.
2.4.2 Chipset
The Chipset menu items allow you to change the advanced chipset settings. Select
an item then press Enter to display the sub-menu.
Select Screen
Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit
Advanced Chipset settings
WARNING: Setting wrong values in the sections below
may cause system to malfunction.
Configure DRAM Timing by SPD [Enabled]
Graphic Adapter Priority [AGP/Int. VGA]
Onboard Video Memory [Enabled, 8MB]
Graphics Aperture Size [ 64 MB]
Spread Spectrum [Enabled]
Boot Display Device [Auto]
Flat Panel Type [640x480 LVDS]
TV Standard [Auto]
MPS Revision [1.4]
Set the CPU external
frequency for next
boot.
Configure DRAM Timing by SPD [Enabled]
When this item is enabled, the DRAM timing parameters are set according to the
DRAM SPD (Serial Presence Detect). When disabled, you can manually set the
DRAM timing parameters through the DRAM sub-items. Configuration options:
[Disabled] [Enabled]
DRAM CAS# Latency [2.5 Clocks]
This item controls the latency between the SDRAM read command and the
time the data actually becomes available. Configuration options: [2.0 Clocks]
[2.5 Clocks] [3.0 Clocks]
DRAM RAS# Precharge [4 Clocks]
This item controls the idle clocks after issuing a precharge command to the
DDR SDRAM. Configuration options: [4 Clocks] [3 Clocks]
[2 Clocks]
DRAM RAS# to CAS# Delay [4 Clocks]
This item controls the latency between the DDR SDRAM active command and
the read/write command. Configuration options:
[4 Clocks] [3 Clocks] [2 Clocks]