Asus AAEON GENE-APL6 User Manual Download Page 51 | Manualshive

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Chapter 2

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Hardware Information

37

3.5

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Su

bco

mp
act

Bo

ard

G

ENE

-AP

L6

Pin

Pin Name

Signal Type

Signal Level

51

NC

52

+3.3V

PWR

+3.3V

2.6.12 LPC Port (CN12)

Pin

Pin Name

Signal Type

Signal Level

1

LAD0

I/O

+3.3V

2

LAD1

I/O

+3.3V

3

LAD2

I/O

+3.3V

4

LAD3

I/O

+3.3V

5

+3.3V

PWR

+3.3V

6

LFRAME#

IN

7

LRESET#

OUT

+3.3V

8

GND

GND

9

LCLK

OUT

10

SMB_DATA/I2C_SDA

I/O

11

SMB_CLK/I2C_CLK

OUT

12

SMB_ALERT/SERIRQ

IN

+3.3V

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Summary of Contents for AAEON GENE-APL6

Page 1: ...Last Updated August 20 2021 GENE APL6 3 5 Subcompact Board User s Manual 4th Ed ...

Page 2: ...d in this manual is intended to be accurate and reliable However the original manufacturer assumes no responsibility for its use or for any infringements upon the rights of third parties that may result from its use The material in this document is for product information only and is subject to change without notice While reasonable efforts have been made in the preparation of this document to ass...

Page 3: ...red trademark of Microsoft Corp Intel Pentium and Celeron are registered trademarks of Intel Corporation Intel Atom is a trademark of Intel Corporation ITE is a trademark of Integrated Technology Express Inc IBM PC AT PS 2 and VGA are trademarks of International Business Machines Corporation All other product names or trademarks are properties of their respective owners ...

Page 4: ...g List Before setting up your product please make sure the following items have been shipped Item Quantity GENE APL6 MB 1 Heat Spreader 1 If any of these items are missing or damaged please contact your distributor or sales representative immediately ...

Page 5: ...d descriptions and explanations on the product s hardware and software features if any its specifications dimensions jumper connector settings definitions and driver installation instructions if any to facilitate users in setting up their product Users may refer to the product page at AAEON com for the latest version of this document ...

Page 6: ...transient over voltage 7 Always disconnect this device from any AC supply before cleaning 8 While cleaning use a damp cloth instead of liquid or spray detergents 9 Make sure the device is installed near a power outlet and is easily accessible 10 Keep this device away from humidity 11 Place the device on a solid surface during installation to prevent falls 12 Do not cover the openings on the device...

Page 7: ...usion to the device iii Exposure to moisture iv Device is not working as expected or in a manner as described in this manual v The device is dropped or damaged vi Any obvious signs of damage displayed on the device 18 DO NOT LEAVE THIS DEVICE IN AN UNCONTROLLED ENVIRONMENT WITH TEMPERATURES BEYOND THE DEVICE S PERMITTED STORAGE TEMPERATURES SEE CHAPTER 1 TO PREVENT DAMAGE ...

Page 8: ...plosion if the battery is incorrectly replaced Replace only with the same or equivalent type recommended by the manufacturer Dispose of used batteries according to the manufacturer s instructions and your local government s recycling or disposal directives Attention Il y a un risque d explosion si la batterie est remplacée de façon incorrecte Ne la remplacer qu avec le même modèle ou équivalent re...

Page 9: ...质或元素名称及含量 AAEON Main Board Daughter Board Backplane 部件名称有毒有害物质或元素铅 Pb 汞 Hg 镉 Cd 六价铬 Cr VI 多溴联苯 PBB 多溴二苯醚 PBDE 印刷电路板及其电子组件外部信号连接器及线材 O 表示该有毒有害物质在该部件所有均质材料中的含量均在 SJ T 11363 2006 标准规定的限量要求以下 X 表示该有毒有害物质至少在该部件的某一均质材料中的含量超出 SJ T 11363 2006 标准规定的限量要求备注此产品所标示之环保使用期限系指在一般正常使用状况下 ...

Page 10: ...henyl Ethers PBDE PCB Other Components O O O O O Wires Connectors for External Connections O O O O O O O The quantity of poisonous or hazardous substances or elements found in each of the component s parts is below the SJ T 11363 2006 stipulated requirement X The quantity of poisonous or hazardous substances or elements found in at least one of the component s parts is beyond the SJ T 11363 2006 s...

Page 11: ...tion JP2 18 2 5 3 COM3 Pin8 Function Selection JP3 19 2 5 4 LVDS Port2 Backlight Lightness Control Mode Selection JP4 19 2 5 5 LVDS Port2 Backlight Inverter VCC Selection JP5 19 2 5 6 LVDS Port1 Backlight Inverter VCC Selection JP6 20 2 5 7 LVDS Port1 Backlight Lightness Control Mode Selection JP7 20 2 5 8 Auto Power Button Enable Disable Selection JP8 20 2 5 9 Touch Screen 4 5 8 Wire Selection JP...

Page 12: ... 17 LVDS Port2 Inverter Backlight Connector CN17 45 2 6 18 LVDS Port1 CN18 46 2 6 19 USB 2 0 Port 4 CN19 48 2 6 20 USB 2 0 Port 5 CN20 48 2 6 21 LVDS Port1 Inverter Backlight Connector CN21 49 2 6 22 Touch Screen Connector Optional CN22 50 2 6 23 LAN RJ 45 Port1 CN23 53 2 6 24 LAN RJ 45 Port2 CN24 53 2 6 25 COM Port 1 Wafer Optional CN25 54 2 6 26 Dual USB3 0 Connector CN26 55 2 6 27 COM Port 1 D ...

Page 13: ...iguration 74 3 4 7 SIO Configuration 76 3 4 7 1 Serial Port 1 Configuration 77 3 4 7 2 Serial Port 2 Configuration 78 3 4 7 3 Serial Port 3 Configuration 79 3 4 7 4 Serial Port 4 Configuration 80 3 4 7 5 Parallel Port Configuration 81 3 4 8 Power Management 82 3 4 9 Digital IO Port Configuration 83 3 5 Setup Submenu Chipset 84 3 5 1 North Bridge 85 3 5 1 1 LVDS Panel Configuration 86 3 6 Setup Sub...

Page 14: ...rd GENE APL6 4 1 Driver Download Installation 94 Appendix A I O Information 96 A 1 I O Address Map 97 A 2 Memory Address Map 99 A 3 IRQ Mapping Chart 100 Appendix B Mating Connectors 117 B 1 List of Mating Connectors and Cables 118 ...

Page 15: ...3 5 Subcompact Board GENE APL6 Chapter 1 Chapter 1 Product Specifications ...

Page 16: ... 1 10 GHz up to 2 40 GHz Atom E3950 4C 4T 1 60 GHz up to 2 00GHz Atom E3940 4C 4T 1 60GHz up to 1 80GHz Atom E3930 2C 2T 1 30GHz up to 1 80GHz CPU TDP 6W N4200 N3350 12W E3950 E3940 E3930 Chipset Integrated with Intel SoC Memory Type DDR3L up to 1866MHz SODIMM x 1 ECC Support Non ECC Max Memory Capacity Up to 8GB BIOS UEFI Wake on LAN Yes Watchdog Timer 255 Levels Security TPM 2 0 Optional RTC Bat...

Page 17: ...2V with Intel E3950 DDR3L 1866MHz 8GB Display Controller Intel HD Graphics 500 505 LVDS eDP LVDS1 Dual Channel 18 24bit x 1 LVDS2 Dual Channel 18 24bit x 1 Optional HDMI 1 4b Display Interface VGA x 1 Multiple Display 3 Simultaneous Displays Audio Codec Realtek ALC897 892 Audio Interface Line In Line Out MIC Speaker External I O Ethernet Intel i210 i211 10 100 1000Base RJ 45 x 2 USB USB3 2 Gen 1 x...

Page 18: ... SATA III x 1 5V SATA Power Connector x 1 Audio Audio Header x 1 DIO GPIO 8 bit SMBus I2C I2C SMBus x 1 Default I2C Touch 4 5 8 wire Touch Controller x 1 optional Fan 4 pin DC Fan x 1 SIM Micro SIM x 1 Optional Front Panel HDD LED PWR LED Power Button Buzzer Reset Others eMMC 16GB 32GB 64GB optional Parallel Port SPP EPP ECP x 1 optional function set by BIOS Expansion Mini PCIe mSATA Full size mPC...

Page 19: ...APL6 Expansion BIO Others Mechanical Dimensions 5 75 x 4 146mm x 101 7mm Environment Operating Temperature 32 F 140 F 0 C 60 C Storage Temperature 40 F 176 F 40 C 80 C Operating Humidity 0 90 relative humidity non condensing MTBF 374 567 Certification EMC CE FCC ...

Page 20: ...3 5 Subcompact Board GENE APL6 Chapter 2 Chapter 2 Hardware Information ...

Page 21: ...Chapter 2 Hardware Information 7 3 5 Subcompact Board GENE APL6 2 1 Dimensions Component Side ...

Page 22: ...Chapter 2 Hardware Information 8 3 5 Subcompact Board GENE APL6 Solder Side ...

Page 23: ...Chapter 2 Hardware Information 9 3 5 Subcompact Board GENE APL6 With Heat Spreader ...

Page 24: ...Chapter 2 Hardware Information 10 3 5 Subcompact Board GENE APL6 2 1 1 Dimensions Optional HDMI SKU Component Side ...

Page 25: ...Chapter 2 Hardware Information 11 3 5 Subcompact Board GENE APL6 Solder Side ...

Page 26: ...Chapter 2 Hardware Information 12 3 5 Subcompact Board GENE APL6 With Heat Spreader ...

Page 27: ...Chapter 2 Hardware Information 13 3 5 Subcompact Board GENE APL6 2 2 Jumpers and Connectors Component Side ...

Page 28: ...Chapter 2 Hardware Information 14 3 5 Subcompact Board GENE APL6 2 2 1 Jumpers and Connectors Optional HDMI SKU Component Side ...

Page 29: ...Chapter 2 Hardware Information 15 3 5 Subcompact Board GENE APL6 2 3 Assembly Options Optional Accessory GENE APL6 HSK01 ...

Page 30: ...Chapter 2 Hardware Information 16 3 5 Subcompact Board GENE APL6 2 4 Block Diagram ...

Page 31: ...M2 Pin8 Function Selection JP3 COM3 Pin8 Function Selection JP4 LVDS Port2 Backlight Lightness Control Mode Selection JP5 LVDS Port2 Backlight Inverter VCC Selection and Operating VDD Selection JP6 LVDS Port1 Backlight Inverter VCC Selection and Operating VDD Selection JP7 LVDS Port2 Backlight Lightness Control Mode Selection JP8 Auto Power Button Enable Disable Selection JP9 Touch Screen 4 5 8 wi...

Page 32: ... Function Selection JP2 12V Ring Default 5V 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 3 5 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 3 5 1 2 3 4 5 6 1 3 5 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 3 5 1 2 3 4 5 6...

Page 33: ...ault PWM Mode 2 5 5 LVDS Port2 Backlight Inverter VCC Selection JP5 12V 5V Default 3 3V Default 5V 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 5 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 3 5 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 3 5 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 1 2 3 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6...

Page 34: ...V Default 5V 2 5 7 LVDS Port1 Backlight Lightness Control Mode Selection JP7 VR Mode Default PWM Mode 2 5 8 Auto Power Button Enable Disable Selection JP8 Disable ATX Enable AT Default Note When disabled the power button of JP5 1 2 will be used to power on the system 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 1 2 3 1 2 3 1 2 3 ...

Page 35: ...Hardware Information 21 3 5 Subcompact Board GENE APL6 2 5 9 Touch Screen 4 5 8 Wire Selection JP9 4 8 Wire Mode Default 5 Wire Mode 2 5 10 Clear CMOS Jumper JP10 Normal Default Clear CMOS 1 2 3 1 2 3 1 2 3 1 2 3 ...

Page 36: ... SATA Port CN5 CPU Fan Optional CN6 Audio I O Port CN7 Mini Card Slot Full Sized CN8 COM Port 2 RS232 422 485 CN9 COM Port 3 RS232 422 485 CN10 COM Port 4 CN11 mSATA Slot Half sized CN12 LPC Port CN13 LVDS Port2 CN14 Micro SIM Card Socket CN15 SPI Debug Port CN16 LPT Port or Digital I O Port CN17 LVDS Port2 Inverter Backlight Connector CN18 LVDS Port1 CN19 USB2 0 Port 4 CN20 USB2 0 Port 5 CN21 LVD...

Page 37: ...Subcompact Board GENE APL6 Label Function CN24 LAN RJ 45 Port2 CN25 COM Port 1 Wafer Optional CN26 Dual USB3 0 Connector Port 0 Port 1 CN27 COM Port 1 D SUB 9 CN28 Battery Connector CN29 HDMI Connector CN30 VGA Port DIMM1 DDR3L SO DIMM Slot ...

Page 38: ...harge design is different we recommend restarting 3 seconds after powering off to make sure ATX power is fully discharged or make sure 5V standby power has been discharged to under 2V Note 2 The maximum current rating of Pin 3 5VSB is 0 7A 2 6 2 5V Output for SATA HDD CN2 Pin Pin Name Signal Type Signal Level 1 5V PWR 5V 2 GND GND Note The maximum current rating of Pin 1 5V is 1A 5VSB GND PS_ON 1 ...

Page 39: ...Type Signal Level 1 VIN PWR 9V 36V or 12V 2 GND GND Note 1 There are two types of power input 9V 36V or 12V only Input type can be adjusted in BIOS Note 2 The maximum current rating of Pin 1 VIN is 7A 2 6 4 SATA Port CN4 Pin Pin Name Signal Type Signal Level 1 GND GND 2 SATA_TX DIFF 3 SATA_TX DIFF VIN GND Pin 1 Pin 7 ...

Page 40: ...PL6 Pin Pin Name Signal Type Signal Level 4 GND GND 5 SATA_RX DIFF 6 SATA_RX DIFF 7 GND GND 2 6 5 CPU FAN Optional CN5 Pin Pin Name Signal Type Signal Level 1 GND GND 2 FAN_POWER PWR 12V 3 FAN_TAC IN 4 NC Note The maximum current rating of Pin 2 FAN_POWER is 0 5A ...

Page 41: ...MIC_R IN 3 GND_AUDIO GND 4 LINE_L_IN IN 5 LINE_R_IN IN 6 GND_AUDIO GND 7 LEFT_OUT OUT 8 GND_AUDIO GND 9 RIGHT_OUT OUT 10 5V_AUDIO PWR 5V 2 6 7 Mini Card Slot Full Size CN7 Pin Pin Name Signal Type Signal Level 1 PCIE_WAKE IN 2 3 3VSB PWR 3 3V 3 NC MIC_L 1 10 MIC_R LINE_L_IN LINE_R_IN LEFT_OUT RIGHT_OUT 5V_AUDIO GND_AUDIO GND_AUDIO GND_AUDIO ...

Page 42: ...V 7 PCIE_CLK_REQ IN 8 UIM_PWR PWR 9 GND GND 10 UIM_DATA I O 11 PCIE_REF_CLK DIFF 12 UIM_CLK IN 13 PCIE_REF_CLK DIFF 14 UIM_RST IN 15 GND GND 16 UIM_VPP PWR 17 NC 18 GND GND 19 NC 20 W_DISABLE OUT 3 3V 21 GND GND 22 PCIE_RST OUT 3 3V 23 PCIE_RX DIFF 24 3 3VSB PWR 3 3V 25 PCIE_RX DIFF 26 GND GND 27 GND GND 28 1 5V PWR 1 5V 29 GND GND ...

Page 43: ...gnal Level 30 SMB_CLK I O 3 3V 31 PCIE_TX DIFF 32 SMB_DATA I O 3 3V 33 PCIE_TX DIFF 34 GND GND 35 GND GND 36 USB_D DIFF 37 GND GND 38 USB_D DIFF 39 3 3VSB PWR 3 3V 40 GND GND 41 3 3VSB PWR 3 3V 42 NC 43 GND GND 44 NC 45 NC 46 NC 47 NC 48 1 5V PWR 1 5V 49 NC 50 GND GND 51 NC 52 3 3VSB PWR 3 3V ...

Page 44: ...nformation 30 3 5 Subcompact Board GENE APL6 2 6 8 COM Port 2 CN8 RS232 Pin Pin Name Signal Type Signal Level 1 DCD2 IN 2 DSR2 IN 3 RX2 IN 4 RTS2 OUT 5V 5 TX2 OUT 5V 6 CTS2 IN 7 DTR2 OUT 5V 8 RI2 5V 12V IN 5V 12V 9 GND GND ...

Page 45: ... 7 NC 8 NC 5V 12V PWR 5V 12V 9 GND GND RS422 Pin Pin Name Signal Type Signal Level 1 RS422_TX2 OUT 5V 2 NC 3 RS422_TX2 OUT 5V 4 NC 5 RS422_RX2 IN 6 NC 7 RS422_RX2 IN 8 NC 5V 12V PWR 5V 12V 9 GND GND Note 1 COM2 RS 232 422 485 can be set by BIOS setting Default is RS 232 Note 2 Pin 8 function can be set by JP2 The maximum driving current in power supply mode is 0 5A ...

Page 46: ...nformation 32 3 5 Subcompact Board GENE APL6 2 6 9 COM Port 3 CN9 RS232 Pin Pin Name Signal Type Signal Level 1 DCD3 IN 2 DSR3 IN 3 RX3 IN 4 RTS3 OUT 5V 5 TX3 OUT 5V 6 CTS3 IN 7 DTR3 OUT 5V 8 RI2 5V 12V IN 5V 12V 9 GND GND ...

Page 47: ... 7 NC 8 NC 5V 12V PWR 5V 12V 9 GND GND RS422 Pin Pin Name Signal Type Signal Level 1 RS422_TX3 OUT 5V 2 NC 3 RS422_TX3 OUT 5V 4 NC 5 RS422_RX3 IN 6 NC 7 RS422_RX3 IN 8 NC 5V 12V PWR 5V 12V 9 GND GND Note 1 COM3 RS 232 422 485 can be set by BIOS setting Default is RS 232 Note 2 Pin 8 function can be set by JP3 The maximum driving current in power supply mode is 0 5A ...

Page 48: ...ardware Information 34 3 5 Subcompact Board GENE APL6 2 6 10 COM Port 4 CN10 Pin Pin Name Signal Type Signal Level 1 DCD4 IN 2 DSR4 IN 3 RX4 IN 4 RTS4 OUT 9V 5 TX4 OUT 9V 6 CTS4 IN 7 DTR4 OUT 9V 8 RI4 IN 9 GND GND ...

Page 49: ... 2 6 11 mSATA Slot Half Sized CN11 Pin Pin Name Signal Type Signal Level 1 NC 2 3 3V PWR 3 3V 3 NC 4 GND GND 5 NC 6 NC 7 NC 8 NC 9 GND GND 10 NC 11 NC 12 NC 13 NC 14 NC 15 GND GND 16 NC 17 NC 18 GND GND 19 NC 20 NC 21 GND GND 22 NC 23 SRXP_PRXN DIFF 24 3 3V PWR 3 3V ...

Page 50: ...gnal Type Signal Level 25 SRXN_PRXP DIFF 26 GND GND 27 GND GND 28 NC 29 GND GND 30 NC 31 STXN_PTXN DIFF 32 NC 33 STXP_PTXP DIFF 34 GND GND 35 GND GND 36 NC 37 GND GND 38 NC 39 3 3V PWR 3 3V 40 GND GND 41 3 3V PWR 3 3V 42 NC 43 GND GND 44 NC 45 NC 46 NC 47 NC 48 NC 49 NC 50 GND GND ...

Page 51: ...al Level 51 NC 52 3 3V PWR 3 3V 2 6 12 LPC Port CN12 Pin Pin Name Signal Type Signal Level 1 LAD0 I O 3 3V 2 LAD1 I O 3 3V 3 LAD2 I O 3 3V 4 LAD3 I O 3 3V 5 3 3V PWR 3 3V 6 LFRAME IN 7 LRESET OUT 3 3V 8 GND GND 9 LCLK OUT 10 SMB_DATA I2C_SDA I O 11 SMB_CLK I2C_CLK OUT 12 SMB_ALERT SERIRQ IN 3 3V ...

Page 52: ...3V or 5V by JP5 Driving current supports up to 1A Pin Pin Name Signal Type Signal Level 1 BKL_ENABLE2 OUT 2 BKL_CONTROL2 OUT 3 LCD_PWR2 PWR 3 3V 5V 4 GND GND 5 LVDS2_A_CLK DIFF 6 LVDS2_A_CLK DIFF 7 LCD_PWR2 PWR 3 3V 5V 8 GND GND 9 LVDS2_DA0 DIFF 10 LVDS2_DA0 DIFF 11 LVDS2_DA1 DIFF 12 LVDS2_DA1 DIFF PIN 1 PIN 2 PIN 30 PIN 29 ...

Page 53: ...IFF 14 LVDS2_DA2 DIFF 15 LVDS2_DA3 DIFF 16 LVDS2_DA3 DIFF 17 DDC2_DATA I O 3 3V 18 DDC2_CLK I O 3 3V 19 LVDS2_DB0 DIFF 20 LVDS2_DB0 DIFF 21 LVDS2_DB1 DIFF 22 LVDS2_DB1 DIFF 23 LVDS2_DB2 DIFF 24 LVDS2_DB2 DIFF 25 LVDS2_DB3 DIFF 26 LVDS2_DB3 DIFF 27 LCD_PWR2 PWR 3 3V 5V 28 GND GND 29 LVDS2_B_CLK DIFF 30 LVDS2_B_CLK DIFF ...

Page 54: ...rdware Information 40 3 5 Subcompact Board GENE APL6 2 6 14 Micro SIM Card Socket CN14 Pin Pin Name Signal Type Signal Level 1 UIM_PWR PWR 2 UIM_RST IN 3 UIM_CLK IN 4 NC 5 GND GND 6 UIM_VPP PWR 7 UIM_DATA I O 8 NC ...

Page 55: ...1 3 5 Subcompact Board GENE APL6 2 6 15 BIOS Debug Port CN15 Pin Pin Name Signal Type Signal Level 1 SPI_MISO OUT 2 GND GND 3 SPI_CLK IN 4 3 3VSB PWR 3 3V 5 SPI_MOSI IN 6 SPI_CS IN 7 NC P IN 1 P IN 2 P IN 3 P IN 4 P IN 5 P IN 6 P IN 7 ...

Page 56: ...tting Default is LPT port Note 2 The maximum current rating of Pin 26 5V is 1A LPT Port Pin Pin Name Signal Type Signal Level 1 STROBE IN 2 AFD I O 3 PD0 I O 4 ERROR IN 5 PD1 I O 6 PRINT I O 7 PD2 I O 8 SLIN I O 9 PD3 I O 10 GND GND 11 PD4 I O 12 GND GND 13 PD5 I O STROBE AFD ERROR PRINT SLIN GND GND GND GND GND GND GND GND 5V D0 D1 D2 D3 D4 D5 D6 D7 ACK BUSY PE SLCT ...

Page 57: ...LPT Port Pin Pin Name Signal Type Signal Level 14 GND GND 15 PD6 I O 16 GND GND 17 PD7 I O 18 GND GND 19 ACK IN 20 GND GND 21 BUSY IN 22 GND GND 23 PE IN 24 GND GND 25 SLCT IN 26 5V PWR 5V Digital I O Port Pin Pin Name Signal Type Signal Level 1 NC 2 NC 3 DIO0 I O 5V ...

Page 58: ...t Pin Pin Name Signal Type Signal Level 4 NC 5 DIO1 I O 5V 6 NC 7 DIO2 I O 5V 8 NC 9 DIO3 I O 5V 10 GND GND 11 DIO4 I O 5V 12 GND GND 13 DIO5 I O 5V 14 GND GND 15 DIO6 I O 5V 16 GND GND 17 DIO7 I O 5V 18 GND GND 19 NC 20 GND GND 21 NC 22 GND GND 23 NC 24 GND GND 25 NC 26 5V PWR 5V ...

Page 59: ...tor CN17 Pin Pin Name Signal Type Signal Level 1 BKL_PWR PWR 5V 12V 2 BKL_CONTROL OUT 3 GND GND 4 GND GND 5 BKL_ENABLE OUT 5V Note 1 LVDS LCD_PWR2 can be set to 5V or 12V by JP5 The driving current supports up to 1 5A Note 2 LVDS2 BKL_CONTROL can be set by JP4 BLK_PWR 2 3 4 5 1 BKL_CONTROL GND GND BKL_ENABLE ...

Page 60: ...V by JP6 The driving current supports up to 1 5A Pin Pin Name Signal Type Signal Level 1 BKL_ENABLE OUT 2 BKL_CONTROL OUT 3 LCD_PWR PWR 3 3V 5V 4 GND GND 5 LVDS_A_CLK DIFF 6 LVDS_A_CLK DIFF 7 LCD_PWR PWR 3 3V 5V 8 GND GND 9 LVDS_DA0 DIFF 10 LVDS_DA0 DIFF 11 LVDS_DA1 DIFF 12 LVDS_DA1 DIFF 13 LVDS_DA2 DIFF PIN 1 PIN 2 PIN 30 PIN 29 ...

Page 61: ...el 14 LVDS_DA2 DIFF 15 LVDS_DA3 DIFF 16 LVDS_DA3 DIFF 17 DDC_DATA I O 3 3V 18 DDC_CLK I O 3 3V 19 LVDS_DB0 DIFF 20 LVDS_DB0 DIFF 21 LVDS_DB1 DIFF 22 LVDS_DB1 DIFF 23 LVDS_DB2 DIFF 24 LVDS_DB2 DIFF 25 LVDS_DB3 DIFF 26 LVDS_DB3 DIFF 27 LCD_PWR PWR 3 3V 5V 28 GND GND 29 LVDS_B_CLK DIFF 30 LVDS_B_CLK DIFF ...

Page 62: ...ENE APL6 2 6 19 USB 2 0 Port 4 CN19 Pin Pin Name Signal Type Signal Level 1 5VSB PWR 5V 2 USB_D DIFF 3 USB_D DIFF 4 GND GND 5 GND GND 2 6 20 USB 2 0 Port 5 CN20 Pin Pin Name Signal Type Signal Level 1 5VSB PWR 5V 2 USB_D DIFF 3 USB_D DIFF 4 GND GND 5 GND GND ...

Page 63: ...tor CN21 Pin Pin Name Signal Type Signal Level 1 BKL_PWR PWR 5V 12V 2 BKL_CONTROL OUT 3 GND GND 4 GND GND 5 BKL_ENABLE OUT 5V Note 1 LVDS LCD_PWR2 can be set to 5V or 12V by JP6 The driving current supports up to 1 5A Note 2 LVDS1 BKL_CONTROL can be set by JP7 BLK_PWR 2 3 4 5 1 BKL_CONTROL GND GND BKL_ENABLE ...

Page 64: ...2 Touch Screen Connector Optional CN22 Note Touch mode can be set by BIOS setting 8 Wire Pin Pin Name Signal Type Signal Level 1 GND GND 2 TOP EXCITE IN 3 BOTTOM EXCITE IN 4 LEFT EXCITE IN 5 RIGHT EXCITE IN 6 TOP SENSE IN 7 BOTTOM SENSE IN 8 LEFT SENSE IN 9 RIGHT SENSE IN ...

Page 65: ...Chapter 2 Hardware Information 51 3 5 Subcompact Board GENE APL6 4 Wire Pin Pin Name Signal Type Signal Level 1 GND GND 2 TOP IN 3 BOTTOM IN 4 LEFT IN 5 RIGHT IN 6 NC 7 NC 8 NC 9 NC ...

Page 66: ...Chapter 2 Hardware Information 52 3 5 Subcompact Board GENE APL6 5 Wire Pin Pin Name Signal Type Signal Level 1 GND GND 2 UL Y IN 3 UR H IN 4 LL L IN 5 LR X IN 6 SENSE S IN 7 NC 8 NC 9 NC ...

Page 67: ... Pin Name Signal Type Signal Level 1 MDI0 DIFF 2 MDI0 DIFF 3 MDI1 DIFF 4 MDI2 DIFF 5 MDI2 DIFF 6 MDI1 DIFF 7 MDI3 DIFF 8 MDI3 DIFF 2 6 24 LAN RJ 45 Port2 CN24 Pin Pin Name Signal Type Signal Level 1 MDI0 DIFF 2 MDI0 DIFF 3 MDI1 DIFF 4 MDI2 DIFF 1 ACT LINK LED SPEED LED 8 1 ACT LINK LED SPEED LED 8 ...

Page 68: ...L6 Pin Pin Name Signal Type Signal Level 5 MDI2 DIFF 6 MDI1 DIFF 7 MDI3 DIFF 8 MDI3 DIFF 2 6 25 COM Port 1 Wafer Optional CN25 Pin Pin Name Signal Type Signal Level 1 DCD1 IN 2 DSR1 IN 3 RX1 IN 4 RTS1 OUT 9V 5 TX1 OUT 9V 6 CTS1 IN 7 DTR1 OUT 9V 8 RI1 IN 9 GND GND ...

Page 69: ...Level 1 5VSB PWR 5V 2 USB0_D DIFF 3 USB0_D DIFF 4 GND GND 5 USB0_SSRX DIFF 6 USB0_SSRX DIFF 7 GND GND 8 USB0_SSTX DIFF 9 USB0_SSTX DIFF 10 5VSB PWR 5V 11 USB1_D DIFF 12 USB1_D DIFF 13 GND GND 14 USB1_SSRX DIFF 15 USB1_SSRX DIFF 16 GND GND 17 USB1_SSTX DIFF 18 USB1_SSTX DIFF 10 Port 1 Port 0 11 12 13 1 2 3 4 14 15 16 17 18 5 6 7 8 9 ...

Page 70: ...APL6 2 6 27 COM Port 1 D SUB 9 CN27 Pin Pin Name Signal Type Signal Level 1 DCD IN 2 RX IN 3 TX OUT 9V 4 DTR OUT 9V 5 GND GND 6 DSR IN 7 RTS OUT 9V 8 CTS IN 9 RI IN 2 6 28 Battery CONN CN28 Pin Pin Name Signal Type Signal Level 1 3 3V PWR 3 3V 2 GND GND 1 5 6 9 ...

Page 71: ...in Name Signal Type Signal Level 1 HDMI_TX2 DIFF 2 GND GND 3 HDMI_TX2 DIFF 4 HDMI_TX1 DIFF 5 GND GND 6 HDMI_TX1 DIFF 7 HDMI_TX0 DIFF 8 GND GND 9 HDMI_TX0 DIFF 10 HDMI_CLK DIFF 11 GND GND 12 HDMI_CLK DIFF 13 NC 14 NC 15 DDC_CLK I O 5V 16 DDC_DATA I O 5V 17 GND GND 18 5V PWR 5V 19 HDMI_HPD ...

Page 72: ...n Name Signal Type Signal Level 1 RED OUT 2 GREEN OUT 3 BLUE OUT 4 NC 5 GND GND 6 RED_GND_RTN GND 7 GREEN_GND_RTN GND 8 BLUE_GND_RTN GND 9 5V PWR 5V 10 NC 11 NC 12 DDC_DATA I O 5V 13 HSYNC OUT 14 VSYNC OUT 15 DDC_CLK I O 5V 2 6 31 DDR3L SO DIMM Slot DIMM1 Standard specifications 1 6 10 11 15 5 ...

Page 73: ...3 5 Subcompact Board GENE APL6 Chapter 3 Chapter 3 AMI BIOS Setup ...

Page 74: ...verification routines check the current system configuration against the values stored in the CMOS memory If they do not match an error message will be output and the BIOS setup program will need to be run to set the configuration information in memory There are three situations in which the CMOS settings will need to be set or changed Starting the system for the first time The system hardware has...

Page 75: ...ower is turned off To enter BIOS Setup press Del or F2 immediately while your computer is powering up The function for each interface can be found below Main Date and time can be set here Press Tab to switch between date elements Advanced Access advanced hardware settings and options Chipset Chipset settings and options Security Set admin and user passwords access secure boot options Boot Boot opt...

Page 76: ...Chapter 3 AMI BIOS Setup 62 3 5 Subcompact Board GENE APL6 3 3 Setup Submenu Main ...

Page 77: ...Chapter 3 AMI BIOS Setup 63 3 5 Subcompact Board GENE APL6 3 4 Setup Submenu Advanced ...

Page 78: ...ce TCG EFI protocol and INT1A interface will not be available SHA 1 PCR Bank Disable Enable Optimal Default Failsafe Default Enable or Disable SHA 1 PCR Bank SHA256 PCR Bank Disable Enable Optimal Default Failsafe Default Enable or Disable SHA256 PCR Bank Pending Operation None Optimal Default Failsafe Default TPM Clear Schedule an Operation for the Security Device NOTE Your Computer will reboot d...

Page 79: ...ent Hierarchy Disabled Enabled Optimal Default Failsafe Default Enable or Disable Endorsement Hierarchy TPM2 0 UEFI Spec Version TCG_1_2 TCG_2 Optimal Default Failsafe Default Select the TCG2 Spec Version Support TCG_1_2 the Compatible mode for Win8 Win10 TCG_2 Support new TCG2 protocol and event format for Win10 or later Physical Presence Spec Version 1 2 1 3 Optimal Default Failsafe Default Sele...

Page 80: ... Default Failsafe Default Enable Disable Intel SpeedStep Turbo Mode Disabled Enabled Optimal Default Failsafe Default Turbo Mode Power Limit 1 Enable Disabled Optimal Default Failsafe Default Enabled Enable Disable Power Limit 1 Intel Virtualization Technology Disabled Enabled Optimal Default Failsafe Default When enabled a VMM can utilize the additional hardware capabilities provided by Vanderpoo...

Page 81: ... 67 3 5 Subcompact Board GENE APL6 Options Summary VT d Disabled Optimal Default Failsafe Default Enabled Enable Disable CPU VT d Thermal Monitor Disabled Enabled Optimal Default Failsafe Default Enable Disable Thermal Monitor ...

Page 82: ...e Chipset SATA controller supports the 2 black internal SATA ports up to 3Gb s supported per port SATA GEN SPEED Auto Optimal Default Failsafe Default GEN1 GEN2 GEN3 SATA GEN SPEED SELECTION Port 0 Disabled Enabled Optimal Default Failsafe Default Enable or Disable SATA Port SATA Port 0 Hot Plug Capability Disabled Optimal Default Failsafe Default Enabled If enabled SATA port will be reported as H...

Page 83: ...Chapter 3 AMI BIOS Setup 69 3 5 Subcompact Board GENE APL6 Options Summary mSATA Port Disabled Enabled Optimal Default Failsafe Default Enable or Disable SATA Port ...

Page 84: ... GENE APL6 3 4 4 SCC Configuration Options Summary SCC eMMC Support Disabled Enabled Optimal Default Failsafe Default Enable Disable SCC eMMC Support eMMC Max Speed HS400 Optimal Default Failsafe Default HS200 DDR50 Select the eMMC max Speed allowed ...

Page 85: ...Chapter 3 AMI BIOS Setup 71 3 5 Subcompact Board GENE APL6 3 4 5 PCI Express Configuration ...

Page 86: ...N7 Options Summary PCIE Slot CN7 Disabled Enabled Optimal Default Failsafe Default Control PCIE Slot CN7 Hot Plug Disabled Optimal Default Failsafe Default Enabled PCI Express Hot Plug Enable Disable PCIe Speed Auto Optimal Default Failsafe Default Gen1 Gen2 Configure PCIe Speed ...

Page 87: ...Chapter 3 AMI BIOS Setup 73 3 5 Subcompact Board GENE APL6 3 4 6 Hardware Monitor Options Summary Smart Fan Disable Enable Optimal Default Failsafe Default Enable or Disable Smart Fan ...

Page 88: ...Mode Auto Duty Cycle Mode Optimal Default Failsafe Default Smart Fan Mode Select Temperature Source CPU external Optimal Default Failsafe Default System Select the monitored temperature source for this fan Duty Cycle 1 85 Temperature 1 60 Duty Cycle 2 70 Temperature 2 50 Duty Cycle 3 60 Temperature 3 40 Duty Cycle 4 50 Temperature 4 30 Duty Cycle 5 40 ...

Page 89: ...Chapter 3 AMI BIOS Setup 75 3 5 Subcompact Board GENE APL6 Options Summary Auto fan speed control Fan speed will follow different temperature by different duty cycle 1 100 ...

Page 90: ...Chapter 3 AMI BIOS Setup 76 3 5 Subcompact Board GENE APL6 3 4 7 SIO Configuration ...

Page 91: ...se This Device Disable Enable Optimal Default Failsafe Default Enable or Disable this Logical Device Possible Use Automatic Settings Optimal Default Failsafe Default IO 3F8h IRQ 4 IO 2F8h IRQ 3 Allows user to change Device s Resource settings New settings will be reflected on This Setup Page after System restarts ...

Page 92: ...lt Failsafe Default Enable or Disable this Logical Device Possible Use Automatic Settings Optimal Default Failsafe Default IO 2F8h IRQ 3 IO 3F8h IRQ 4 Allows user to change Device s Resource settings New settings will be reflected on This Setup Page after System restarts Mode RS232 Optimal Default Failsafe Default RS422 RS485 UART RS232 422 485 selection ...

Page 93: ...t Failsafe Default Enable or Disable this Logical Device Possible Use Automatic Settings Optimal Default Failsafe Default IO 3E8h IRQ 11 IO 2E8h IRQ 11 Allows user to change Device s Resource settings New settings will be reflected on This Setup Page after System restarts Mode RS232 Optimal Default Failsafe Default RS422 RS485 UART RS232 422 485 selection ...

Page 94: ...e This Device Disable Enable Optimal Default Failsafe Default Enable or Disable this Logical Device Possible Use Automatic Settings Optimal Default Failsafe Default IO 2E8h IRQ 10 IO 3E8h IRQ 10 Allows user to change Device s Resource settings New settings will be reflected on This Setup Page after System restarts ...

Page 95: ...er 3 AMI BIOS Setup 81 3 5 Subcompact Board GENE APL6 3 4 7 5 Parallel Port Configuration Options Summary Use This Device Disable Enable Optimal Default Failsafe Default Enable or Disable this Logical Device ...

Page 96: ...ntrol Disabled Optimal Default Failsafe Default Enabled Configure power mode for power saving function Restore AC Power Loss Last State Optimal Default Failsafe Default Always On Always Off Specify what state to go to when power is re applied after a power failure G3 state RTC wake system from S5 Disable Optimal Default Failsafe Default Fixed Time Fixed Time System will wake on the hr min sec spec...

Page 97: ...3 3 5 Subcompact Board GENE APL6 3 4 9 Digital IO Port Configuration Options Summary DIO Port Output Input Set DIO as Input or Output Output Level High Optimal Default Failsafe Default Low Set output level when DIO pin is output ...

Page 98: ...Chapter 3 AMI BIOS Setup 84 3 5 Subcompact Board GENE APL6 3 5 Setup Submenu Chipset ...

Page 99: ...Chapter 3 AMI BIOS Setup 85 3 5 Subcompact Board GENE APL6 3 5 1 North Bridge ...

Page 100: ...KUs with two LVDS ports Options Summary LVDS Disabled Enabled Optimal Default Failsafe Default Enable Disabled this panel LVDS Panel Type 640x480 60Hz 800x480 60Hz 800x600 60Hz 1024x600 60Hz 1024x768 60Hz Optimal Default Failsafe Default 1280x768 60Hz 1280x800 60Hz 1280x1024 60Hz 1366x768 60Hz 1440x900 60Hz 1600x1200 60Hz 1920x1080 60Hz ...

Page 101: ...bit 48 bit Select Color Depth Backlight Type Normal Optimal Default Failsafe Default Inverted Select backlight control signal type Backlight Level 0 10 20 30 40 50 60 70 80 Optimal Default Failsafe Default 90 100 Select backlight control level Backlight PWM Freq 100Hz 200Hz 220Hz Optimal Default Failsafe Default 500Hz 1KHz 2 2KHz 6 5KHz Select PWM frequency of backlight control signal ...

Page 102: ...hen the user enters the Setup utility A User Password does not provide access to many of the features in the Setup utility Select the password you wish to set and press Enter In the dialog box enter your password must be between 3 and 20 letters or numbers Press Enter and retype your password to confirm Press Enter again to set the password Removing the Password Select the password you want to rem...

Page 103: ...ed Secure Boot activated when Platform Key PK is enrolled System mode is User Deployed and CSM function is disable Secure Boot Mode Standard Customized Optimal Default Failsafe Default Secure Boot Mode Custom Standard Set UEFI Secure Boot Mode to STANDARD mode or CUSTOM mode this change is effect after save And after reset the mode will return to STANDARD mode ...

Page 104: ... 5 Subcompact Board GENE APL6 3 6 1 1 Key Management Options Summary Provision Factory Default keys Disabled Optimal Default Failsafe Default Enabled Allow to provision factory default Secure Boot keys when System is in Setup Mode ...

Page 105: ...safe Default Enables or disables Quiet Boot option Monitor Mwait Disable Enabled Auto Optimal Default Failsafe Default Enable Disable Monitor Mwait To install Linux OS please set this item to disable Ipv4 PXE Support Disabled Optimal Default Failsafe Default Enabled Enable Ipv4 PXE Boot Support If disabled IPV4 PXE boot option will not be created ...

Page 106: ...Chapter 3 AMI BIOS Setup 92 3 5 Subcompact Board GENE APL6 3 8 Setup Submenu Exit ...

Page 107: ...3 5 Subcompact Board GENE APL6 Chapter 4 Chapter 4 Drivers Installation ...

Page 108: ...e steps below to install them Step 1 Install Chipset Drivers 1 Open the Step1 Chipset folder followed by SetupChipset exe 2 Follow the instructions 3 Drivers will be installed automatically Step 2 Install Graphics Drivers 1 Open the Step2 VGA folder followed by Setup exe 2 Follow the instructions 3 Drivers will be installed automatically Step 3 Install LAN Drivers 1 Click on the Step3 LAN folder a...

Page 109: ...tep 5 Install TXE Driver 1 Open the Step5 TXE folder followed by SetupTXE exe 2 Follow the instructions 3 Drivers will be installed automatically Step 6 Install Touch Driver 1 Open the Step6 Touch folder followed by Setup exe 2 Follow the instructions 3 Drivers will be installed automatically Step 7 Install GPIO Driver 1 Open the Step6 GPIO folder followed by SetupSerialIO exe 2 Follow the instruc...

Page 110: ...3 5 Subcompact Board GENE APL6 Appendix A Appendix A I O Information ...

Page 111: ...Appendix A I O Information 97 3 5 Subcompact Board GENE APL6 A 1 I O Address Map ...

Page 112: ...Appendix A I O Information 98 3 5 Subcompact Board GENE APL6 ...

Page 113: ...Appendix A I O Information 99 3 5 Subcompact Board GENE APL6 A 2 Memory Address Map ...

Page 114: ...Appendix A I O Information 100 3 5 Subcompact Board GENE APL6 A 3 IRQ Mapping Chart ...

Page 115: ...Appendix A I O Information 101 3 5 Subcompact Board GENE APL6 ...

Page 116: ...Appendix A I O Information 102 3 5 Subcompact Board GENE APL6 ...

Page 117: ...Appendix A I O Information 103 3 5 Subcompact Board GENE APL6 ...

Page 118: ...Appendix A I O Information 104 3 5 Subcompact Board GENE APL6 ...

Page 119: ...Appendix A I O Information 105 3 5 Subcompact Board GENE APL6 ...

Page 120: ...Appendix A I O Information 106 3 5 Subcompact Board GENE APL6 ...

Page 121: ...Appendix A I O Information 107 3 5 Subcompact Board GENE APL6 ...

Page 122: ...Appendix A I O Information 108 3 5 Subcompact Board GENE APL6 ...

Page 123: ...Appendix A I O Information 109 3 5 Subcompact Board GENE APL6 ...

Page 124: ...Appendix A I O Information 110 3 5 Subcompact Board GENE APL6 ...

Page 125: ...Appendix A I O Information 111 3 5 Subcompact Board GENE APL6 ...

Page 126: ...Appendix A I O Information 112 3 5 Subcompact Board GENE APL6 ...

Page 127: ...Appendix A I O Information 113 3 5 Subcompact Board GENE APL6 ...

Page 128: ...Appendix A I O Information 114 3 5 Subcompact Board GENE APL6 ...

Page 129: ...Appendix A I O Information 115 3 5 Subcompact Board GENE APL6 ...

Page 130: ...Appendix A I O Information 116 3 5 Subcompact Board GENE APL6 ...

Page 131: ...3 5 Subcompact Board GENE APL6 Appendix B Appendix B Mating Connectors ...

Page 132: ...Vin Connector N A N A Power Cable 1702002010 CN4 SATA Connector Molex 88750 5318 SATA Cable 1709070500 CN5 CPU Fan Connector Molex 22 01 2035 N A N A CN6 Audio Connector Molex 51021 1000 Audio Cable 1709100254 CN8 COM Port2 Connector Molex 51021 0900 Serial Port Cable 1701090150 CN9 COM Port3 Connector Molex 51021 0900 Serial Port Cable 1701090150 CN10 COM Port4 Connector Molex 51021 0900 Serial P...

Page 133: ...HR 5 NA NA CN18 LVDS Connector HIROSE DF13 30DS 1 25C N A N A CN19 USB Port Connector Molex 51021 0500 USB Wafer Cable 1700050207 CN20 USB Port Connector Molex 51021 0500 USB Wafer Cable 1700050207 CN21 LVDS Inverter Connector JST PHR 5 NA NA CN22 Touch Screen Connector JST SHR 9V S B N A N A CN25 COM Port 1 Connector Molex 51021 0900 Serial Port Cable 1701090150 CN28 External RTC Connector Molex ...

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