Asus Aaeon GENE-ADP6 User Manual Download | Manualshive

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Chapter 3

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AMI BIOS Setup

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Options Summary

Remove 'UEFI CA' from DB
Device Guard ready system must not list 'Microsoft UEFI CA' Certificate in Authorized
Signature database (db).
Restore DB defaults
Restore DB variable to factory defaults.

Platform Key (PK)

Details
Export
Update
Delete

Key Exchange Keys

Details
Export
Update
Append
Delete

Authorized Signatures

Details
Export
Update
Append
Delete

Forbidden Signatures

Details
Export
Update
Append
Delete

Authorized TimeStamps

Update
Append

OsRecovery Signatures

Update
Append

Enroll Factory Defaults or load certificates from a file:
1.Public Key Certificate:
    a)EFI_SIGNATURE_LIST
    b)EFI_CERT_X509 (DER)
    c)EFI_CERT_RSA2048 (bin)
    d)EFI_CERT_SHAXXX
2.Authenticated UEFI Variable
3.EFI PE/COFF Image(SHA256)
Key Source: Factory, External, Mixed

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Summary of Contents for Aaeon GENE-ADP6

Page 1: ...Last Updated September 16 2022 GENE ADP6 3 5 Subcompact Board User s Manual 1st Ed ...

Page 2: ...d in this manual is intended to be accurate and reliable However the original manufacturer assumes no responsibility for its use or for any infringements upon the rights of third parties that may result from its use The material in this document is for product information only and is subject to change without notice While reasonable efforts have been made in the preparation of this document to ass...

Page 3: ...rosoft Windows is a registered trademark of Microsoft Corp Intel and Celeron are registered trademarks of Intel Corporation Intel Core is a trademark of Intel Corporation Realtek is a trademark of Realtek Semiconductor Corporation Ubuntu is a trademark of Canonical All other product names or trademarks are properties of their respective owners ...

Page 4: ...6 Packing List Before setting up your product please make sure the following items have been shipped Item Quantity GENE ADP6 MB 1 If any of these items are missing or damaged please contact your distributor or sales representative immediately ...

Page 5: ...d descriptions and explanations on the product s hardware and software features if any its specifications dimensions jumper connector settings definitions and driver installation instructions if any to facilitate users in setting up their product Users may refer to the product page at AAEON com for the latest version of this document ...

Page 6: ...transient over voltage 7 Always disconnect this device from any AC supply before cleaning 8 While cleaning use a damp cloth instead of liquid or spray detergents 9 Make sure the device is installed near a power outlet and is easily accessible 10 Keep this device away from humidity 11 Place the device on a solid surface during installation to prevent falls 12 Do not cover the openings on the device...

Page 7: ...usion to the device iii Exposure to moisture iv Device is not working as expected or in a manner as described in this manual v The device is dropped or damaged vi Any obvious signs of damage displayed on the device 18 DO NOT LEAVE THIS DEVICE IN AN UNCONTROLLED ENVIRONMENT WITH TEMPERATURES BEYOND THE DEVICE S PERMITTED STORAGE TEMPERATURES SEE CHAPTER 1 TO PREVENT DAMAGE ...

Page 8: ...plosion if the battery is incorrectly replaced Replace only with the same or equivalent type recommended by the manufacturer Dispose of used batteries according to the manufacturer s instructions and your local government s recycling or disposal directives Attention Il y a un risque d explosion si la batterie est remplacée de façon incorrecte Ne la remplacer qu avec le même modèle ou équivalent re...

Page 9: ...质或元素名称及含量 AAEON Main Board Daughter Board Backplane 部件名称有毒有害物质或元素铅 Pb 汞 Hg 镉 Cd 六价铬 Cr VI 多溴联苯 PBB 多溴二苯醚 PBDE 印刷电路板及其电子组件外部信号连接器及线材 O 表示该有毒有害物质在该部件所有均质材料中的含量均在 SJ T 11363 2006 标准规定的限量要求以下 X 表示该有毒有害物质至少在该部件的某一均质材料中的含量超出 SJ T 11363 2006 标准规定的限量要求备注此产品所标示之环保使用期限系指在一般正常使用状况下 ...

Page 10: ...henyl Ethers PBDE PCB Other Components O O O O O Wires Connectors for External Connections O O O O O O O The quantity of poisonous or hazardous substances or elements found in each of the component s parts is below the SJ T 11363 2006 stipulated requirement X The quantity of poisonous or hazardous substances or elements found in at least one of the component s parts is beyond the SJ T 11363 2006 s...

Page 11: ... 2 3 4 LVDS Backlight Inverter Voltage Selection JP4 13 2 3 5 LVDS Operating Voltage Selection JP4 14 2 3 6 Clear CMOS Jumper JP5 14 2 3 7 LVDS Backlight Lightness Control Mode Selection JP6 14 2 4 List of Connectors 15 2 4 1 5V Output for SATA HDD CN1 16 2 4 2 SATA Port CN2 17 2 4 3 External 12V Input Optional CN3 18 2 4 4 External Power Input CN4 18 2 4 5 Audio I O Port CN5 19 2 4 6 M 2 B Key Co...

Page 12: ...3 2 4 18 M 2 M Key Connector CN19 33 2 4 19 eDP Connector CN20 34 2 4 20 LVDS Connector CN21 36 2 4 21 eSPI Connector CN22 38 2 4 22 Nano SIM Card Socket CN23 39 2 4 23 RTC Battery Connector CN24 40 2 4 24 4 Pin FAN Connector CN26 40 2 4 25 LAN RJ 45 Port 1 Port 2 CN27 41 2 4 26 LAN Port 1 LED Connector CN28 42 2 4 27 USB 3 2 USB 2 0 Port 3 CN29 43 2 4 28 USB 3 2 USB 2 0 Port1 Port2 CN30 44 2 4 29...

Page 13: ...SATA Configuration 67 3 4 7 Hardware Monitor 68 3 4 7 1 Smart Fan Mode Configuration 69 3 4 8 SIO Configuration 70 3 4 8 1 Serial Port 1 Configuration 71 3 4 8 2 Serial Port 2 Configuration 72 3 4 8 3 Serial Port 3 Configuration 73 3 4 8 4 Serial Port 4 Configuration 74 3 4 9 Serial Port Console Redirection 75 3 4 10 Legacy Console Redirection Settings 76 3 4 11 AAEON BIOS Robot 77 3 4 12 Power Ma...

Page 14: ...t 92 3 9 Setup Submenu MEBx 93 3 9 1 Intel AMT Configuration 94 3 9 2 Redirection features 95 3 9 3 User Consent 96 3 9 4 Power Control 97 Chapter 4 Driver Installation 98 4 1 Driver Download Installation 99 Appendix A I O Information 101 A 1 I O Address Map 102 A 2 Memory Address Map 104 A 3 IRQ Mapping Chart 105 Appendix B Mating Connectors and Cables 108 B 1 Mating Connectors and Cables 109 ...

Page 15: ...3 5 Subcompact Board GENE ADP6 Chapter 1 Chapter 1 Product Specifications ...

Page 16: ... TDP up to 55W i5 1250PE 12C 16T 3 20GHz up to 4 40GHz 28W TDP up to 64W i3 1220PE 8C 12T 3 10GHz up to 4 20GHz 28W TDP up to 64W Celeron 7305E 5C 5T 1 00GHz 15W Chipset Integrated with Intel SoC Memory Type DDR5 4800MHz Dual Channel SODIMM x 2 up to 64GB BIOS UEFI Wake on LAN Yes Watchdog Timer 255 Levels Security TPM 2 0 NPCT750AABYX RTC Battery Lithium Battery 3V 24mAH Dimension L X W 5 75 x 4 ...

Page 17: ...V Typical Intel Core i7 1270 PE DDR5 32GB x 2 7 95A 12V Max Display Controller Intel Iris Xe Graphics Intel UHD Graphics LVDS eDP LVDS Dual Channel 18 24bit x 1 up to 1920 x 1080 eDP 1 4b HBR3 up to 3840 x 2160 Display Interface HDMI 2 1 x 1 up to 8K x 4K 60Hz or 4K2K 120Hz DP 1 4a x 1 up to 7680 x 4320 60Hz 30bpp Multiple Display Up to 4 Simultaneous Displays Audio Codec Realtek ALC897 Audio Inte...

Page 18: ... Video HDMI 2 1 x 1 DP 1 4a x 1 Internal I O USB USB 2 0 x 4 Serial Port COM 1 COM 2 RS232 422 485 supports 5V 12V RI COM 3 COM 4 RS232 422 485 Video LVDS eDP x 1 Inverter x 1 12V 2A SATA SATA 3 0 x 1 5V SATA Power Connector x 1 Audio Audio Header x 1 DIO GPIO 8 Bit SMBus I2C SMBus I2C x1 Default SMBus Touch Fan Smart Fan x 1 SIM Nano SIM x 1 Front Panel PWR LED HDD LED PWR button HW Reset Other ...

Page 19: ...2 x 1 PCIe x2 USB 3 2 SATA USB 2 0 default USB 3 2 SATA E Key 2230 x 1 PCIe USB 2 0 Other FPC x 1 PCI x4 Gen 4 only supports Graphic or NVME Environmental Operating Temperature 32 F 140 F 0 C 60 C Storage Temperature 40 F 185 F 40 C 85 C Operating Humidity 0 90 relative humidity non condensing MTBF Hours 344 735 Certification EMC CE FCC Class A ...

Page 20: ...Chapter 1 Product Specifications 6 3 5 Subcompact Board GENE ADP6 1 2 Block Diagram ...

Page 21: ...3 5 Subcompact Board GENE ADP6 Chapter 2 Chapter 2 Hardware Information ...

Page 22: ...Chapter 2 Hardware Information 8 3 5 Subcompact Board GENE ADP6 2 1 Dimensions Component Side ...

Page 23: ...Chapter 2 Hardware Information 9 3 5 Subcompact Board GENE ADP6 Solder Side ...

Page 24: ...Chapter 2 Hardware Information 10 3 5 Subcompact Board GENE ADP6 2 2 Jumpers and Connectors Top View Front I O View ...

Page 25: ...Chapter 2 Hardware Information 11 3 5 Subcompact Board GENE ADP6 Bottom View ...

Page 26: ... Function JP1 Auto Power Button Enable Disable Selection JP2 COM1 Pin9 Function Selection JP3 COM2 Pin9 Function Selection JP4 LVDS Operating Voltage Selection LVDS Backlight Inverter Voltage Selection JP5 Clear CMOS Jumper JP6 LVDS Backlight Lightness Control Mode Selection 2 3 1 Auto Power Button Enable Disable Selection JP1 Disable Auto Power Button Enable Auto Power Button Default 1 2 3 1 2 3 ...

Page 27: ...tion 13 3 5 Subcompact Board GENE ADP6 2 3 2 COM 1 Pin 9 Function Selection JP2 12V Ring Default 5V 2 3 3 COM 2 Pin 9 Function Selection JP3 12V Ring Default 5V 2 3 4 LVDS Backlight Inverter Voltage Selection JP4 5V Default 12V ...

Page 28: ...compact Board GENE ADP6 2 3 5 LVDS Operating Voltage Selection JP4 3 3V Default 5V 2 3 6 Clear CMOS Jumper JP5 Normal Default Clear CMOS 2 3 7 LVDS Backlight Lightness Control Mode Selection JP6 VR Mode PWM mode Default 1 2 3 1 2 3 1 2 3 1 2 3 ...

Page 29: ...nal CN4 External Power Input CN5 Audio I O Port CN6 M 2 Key B Connector CN7 DDR5 SO DIMM Channel 1 CN9 Front Panel CN10 SO DIMM Channel 2 CN11 COM Port3 Port4 CN12 COM Port1 Port2 CN13 USB 2 0 Port5 Port6 CN14 Digital IO Port CN15 USB 2 0 Port7 Port8 CN16 SPI Flash Programming Port CN17 LVDS Inverter Backlight Connector CN18 M 2 Key E Connector CN19 M 2 Key M Connector CN20 eDP Connector CN21 LVDS...

Page 30: ...RJ 45 Port1 Port2 CN28 LAN Port1 LED Connector CN29 USB 3 2 USB2 0 Port3 CN30 USB 3 2 USB2 0 Port1 Port2 CN31 DP Connector CN33 HDMI Connector CN34 USB Type C CN35 FPC Connector CN36 LAN Port2 LED Connector 2 4 1 5V Output for SATA HDD CN1 Pin Pin Name Signal Type Signal Level 1 V5S PWR 5V 2 GND GND Note The driving current of V5S supports up to 2A ...

Page 31: ...ardware Information 17 3 5 Subcompact Board GENE ADP6 2 4 2 SATA Port CN2 Pin Pin Name Signal Type Signal Level 1 GND GND GND 2 SATA_TX DIFF 3 SATA_TX DIFF 4 GND GND GND 5 SATA_RX DIFF 6 SATA_RX DIFF 7 GND GND GND ...

Page 32: ...ct Board GENE ADP6 2 4 3 External 12V Input Optional CN3 Pin Pin Name Signal Type Signal Level 1 GND GND GND 2 GND GND GND 3 12V PWR 12V 4 12V PWR 12V 2 4 4 External Power Input CN4 Pin Pin Name Signal Type Signal Level 1 12V PWR 12V 2 GND GND GND ...

Page 33: ...Board GENE ADP6 2 4 5 Audio I O Port CN5 Pin Pin Name Signal Type Signal Level 1 RIGHT_OUT OUT 2 MIC_R IN 3 LEFT_OUT OUT 4 MIC_L IN 5 JD_LOUT IN 6 JD_MIC IN 7 GND_AUDIO GND 8 GND_AUDIO GND 9 JD_LIN IN 10 LINE_R_IN IN 11 5V_AUDIO PWR 5V 12 LINE_L_IN IN ...

Page 34: ...Chapter 2 Hardware Information 20 3 5 Subcompact Board GENE ADP6 2 4 6 M 2 B Key Connector CN6 Standard specifications 2 4 7 DDR5 SO DIMM Channel CN7 Standard specifications ...

Page 35: ...ADP6 2 4 8 Front Panel CN9 Pin Pin Name Signal Type Signal Level 1 GND GND GND 2 EXT_PWRBTN IN 3 SATA_LED OUT 4 SATA_LED OUT 5 BUZZER OUT 6 BUZZER OUT 7 GND GND GND 8 PWR_LED OUT 9 GND GND GND 10 HWRST IN 2 4 9 DDR5 SO DIMM Channel 2 CN10 Standard Specifications ...

Page 36: ...t 3 Port 4 CN11 COM Port 3 Port 4 RS 232 Default Pin Pin Name Signal Type Signal Level 1 DCD3 IN 2 DCD4 IN 3 RX3 IN 4 RX4 IN 5 TX3 OUT 9V 6 TX4 OUT 9V 7 DTR3 OUT 9V 8 DTR4 OUT 9V 9 GND GND GND 10 GND GND GND 11 DSR3 IN 12 DSR4 IN 13 RTS3 OUT 9V 14 RTS4 OUT 9V 15 CTS3 IN 16 CTS4 IN ...

Page 37: ... PWR 5V 12V 19 NC NC NC 20 NC NC NC 2 4 10 1 COM Port 3 RS RS 422 RS 485 COM Port 3 RS 422 Pin Pin Name Signal Type Signal Level 9 GND GND GND 1 RS422_TX OUT 9V 3 RS422_TX OUT 9V 5 RS422_RX IN 7 RS422_RX IN COM Port 3 RS 485 Pin Pin Name Signal Type Signal Level 9 GND GND GND 1 RS485_D I O 9V 3 RS485_D I O 9V Note COM 3 RS 232 422 485 can be set by BIOS setting Default is RS 232 ...

Page 38: ...ort 4 RS 422 Pin Pin Name Signal Type Signal Level 10 GND GND GND 2 RS422_TX OUT 9V 4 RS422_TX OUT 9V 6 RS422_RX IN 8 RS422_RX IN COM Port 4 RS 485 Pin Pin Name Signal Type Signal Level 10 GND GND GND 2 RS485_D I O 9V 4 RS485_D I O 9V Note COM 4 RS 232 422 485 can be set by BIOS setting Default is RS 232 ...

Page 39: ...rt1 Port2 CN12 COM Port 1 Port 2 RS 232 Default Pin Pin Name Signal Type Signal Level 1 DCD1 IN 2 DCD2 IN 3 RX1 IN 4 RX2 IN 5 TX1 OUT 9V 6 TX2 OUT 9V 7 DTR1 OUT 9V 8 DTR2 OUT 9V 9 GND GND GND 10 GND GND GND 11 DSR1 IN 12 DSR2 IN 13 RTS1 OUT 9V 14 RTS2 OUT 9V 15 CTS1 IN 16 CTS2 IN ...

Page 40: ...NC NC 20 NC NC NC 2 4 11 1 COM Port 1 RS 422 RS 485 COM Port 1 RS 422 Pin Pin Name Signal Type Signal Level 9 GND GND GND 1 RS422_TX OUT 9V 3 RS422_TX OUT 9V 5 RS422_RX IN 7 RS422_RX IN COM Port 1 RS 485 Pin Pin Name Signal Type Signal Level 9 GND GND GND 1 RS485_D I O 9V 3 RS485_D I O 9V Note COM 3 RS 232 422 485 can be set by BIOS setting Default is RS 232 Note Pin 17 function can be set by JP2 ...

Page 41: ...n Name Signal Type Signal Level 10 GND GND GND 2 RS422_TX OUT 9V 4 RS422_TX OUT 9V 6 RS422_RX IN 8 RS422_RX IN COM Port 1 RS 485 Pin Pin Name Signal Type Signal Level 10 GND GND GND 2 RS485_D I O 9V 4 RS485_D I O 9V Note COM4 RS 232 422 485 can be set by BIOS setting Default is RS 232 Note Pin 18 function can be set by JP3 ...

Page 42: ...SB 2 0 Port 5 Port 6 CN13 Pin Pin Name Signal Type Signal Level 1 5VSB PWR 5V 2 5VSB PWR 5V 3 USB2_5_DN DIFF 4 USB2_6_DN DIFF 5 USB2_5_DP DIFF 6 USB2_6_DP DIFF 7 GND GND GND 8 GND GND GND 9 GND GND GND 10 GND GND GND Note The driving current of 5VSB supports up to 0 5A Port ...

Page 43: ... 2 4 13 Digital IO Port CN14 Pin Pin Name Signal Type Signal Level 1 DIO_0 IN OUT 2 DIO_1 IN OUT 3 DIO_2 IN OUT 4 DIO_3 IN OUT 5 DIO_4 IN OUT 6 DIO_5 IN OUT 7 DIO_6 IN OUT 8 DIO_7 IN OUT 9 V5S PWR 5V 10 GND GND GND Note The driving current of V5S supports up to 0 5A ...

Page 44: ...SB 2 0 Port 7 Port 8 CN15 Pin Pin Name Signal Type Signal Level 1 5VSB PWR 5V 2 5VSB PWR 5V 3 USB2_7_DN DIFF 4 USB2_8_DN DIFF 5 USB2_7_DP DIFF 6 USB2_8_DP DIFF 7 GND GND GND 8 GND GND GND 9 GND GND GND 10 GND GND GND Note The driving current of 5VSB supports up to 0 5A Port ...

Page 45: ...e Information 31 3 5 Subcompact Board GENE ADP6 2 4 15 SPI Flash Programming Port CN16 Pin Pin Name Signal Type Signal Level 1 SPI_MISO OUT 2 GND GND GND 3 SPI_CLK IN 4 V3P3A_SPI PWR 3 3V 5 SPI_MOSI IN 6 SPI_CS IN 7 NC ...

Page 46: ...r CN17 Pin Pin Name Signal Type Signal Level 1 BKL_PWR PWR 5V Default 12V 2 BKL_PWR PWR 5V Default 12V 3 BKL_CONTROL OUT 4 GND GND 5 GND GND 6 BKL_ENABLE OUT 3 3V Note LVDS BKL_PWR can be set to 12V or 5V by JP4 Note LVDS BKL_CONTROL can be set by JP6 Note The driving current of BKL_PWR supports up to 2A ...

Page 47: ...Chapter 2 Hardware Information 33 3 5 Subcompact Board GENE ADP6 2 4 17 M 2 E Key Connector CN18 Standard specifications 2 4 18 M 2 M Key Connector CN19 Standard specifications ...

Page 48: ...al Level 1 VDD PWR 3 3V 2 VDD PWR 3 3V 3 VDD PWR 3 3V 4 GND GND 5 EDP_LANE2_DN DIFF 6 EDP_LANE2_DP DIFF 7 GND GND 8 EDP_LANE1_DN DIFF 9 EDP_LANE1_DP DIFF 10 GND GND 11 EDP_LANE0_DN DIFF 12 EDP_LANE0_DP DIFF 13 GND GND 14 EDP_LANE3_DN DIFF 15 EDP_LANE3_DP DIFF 16 GND GND 17 EDP_AUX_DN DIFF 18 EDP_ AUX _DP DIFF 19 GND GND ...

Page 49: ...al Level 20 EDP_BKLTCTL 21 N A 22 EDP_BKLT_EN 23 EDP_HPD 24 GND GND 25 GND GND 26 GND GND 27 VCC_EDP_BKLT PWR 12V 28 VCC_EDP_BKLT PWR 12V 29 VCC_EDP_BKLT PWR 12V 30 VCC_EDP_BKLT PWR 12V Note The driving current of VCC_EDP_BKLT supports up to 1 2A Note The driving current of VDD supports up to 1A ...

Page 50: ...1 Pin Pin Name Signal Type Signal Level 1 BKL_ENABLE OUT 2 BKL_CONTROL OUT 3 LCD_PWR PWR 3 3V 5V 4 GND GND 5 LVDS_A_CLK DIFF 6 LVDS_A_CLK DIFF 7 LCD_PWR PWR 3 3V 5V 8 GND GND 9 LVDS_DA0 DIFF 10 LVDS_DA0 DIFF 11 LVDS_DA1 DIFF 12 LVDS_DA1 DIFF 13 LVDS_DA2 DIFF 14 LVDS_DA2 DIFF 15 LVDS_DA3 DIFF ...

Page 51: ...l Type Signal Level 16 LVDS_DA3 DIFF 17 DDC_DATA I O 3 3V 18 DDC_CLK I O 3 3V 19 LVDS_DB0 DIFF 20 LVDS_DB0 DIFF 21 LVDS_DB1 DIFF 22 LVDS_DB1 DIFF 23 LVDS_DB2 DIFF 24 LVDS_DB2 DIFF 25 LVDS_DB3 DIFF 26 LVDS_DB3 DIFF 27 LCD_PWR PWR 3 3V 5V 28 GND GND 29 LVDS_B_CLK DIFF 30 LVDS_B_CLK DIFF ...

Page 52: ...N22 Pin Pin Name Signal Type Signal Level 1 ESP_IO0 I O 1 8V 2 ESP_IO1 I O 1 8V 3 ESP_IO2 I O 1 8V 4 ESP_IO3 I O 1 8V 5 V3P3S PWR 3 3V 6 ESPI_CS IN 7 ESPI_RST OUT 3 3V 8 GND GND GND 9 ESPI_CLK OUT 1 8V 10 SMB_DATA I2C_SDA I O 3 3V 11 SMB_CLK I2C_CLK OUT 3 3V 12 SMB_ALERT INT_SERIRQ IN 3 3V ...

Page 53: ... Information 39 3 5 Subcompact Board GENE ADP6 2 4 22 Nano SIM Card Socket CN23 Pin Pin Name Signal Type Signal Level 1 UIM_PWR PWR 2 UIM_RST IN 3 UIM_CLK IN 4 N A N A 5 GND GND GND 6 UIM_VPP PWR 7 UIM_DATA I O 8 N A N A ...

Page 54: ...C Battery Connector CN24 Pin Pin Name Signal Type Signal Level 1 3 3V PWR 3 3V 2 GND GND GND 2 4 24 4 Pin FAN Connector CN26 Pin Pin Name Signal Type Signal Level 1 GND GND GND 2 FAN_POWER PWR 12V 3 FAN_TAC IN 4 FAN_CTL Note The driving current of FAN_POWER supports up to 1A ...

Page 55: ...l 1P1 LAN2_MDI0_P DIFF 1P2 LAN2_MDI0_N DIFF 1P3 LAN2_MDI1_P DIFF 1P4 LAN2_MDI1_N DIFF 1P7 LAN2_MDI2_P DIFF 1P8 LAN2_MDI2_N DIFF 1P9 LAN2_MDI3_P DIFF 1P10 LAN2_MDI3_N DIFF 2P1 LAN1_MDI0_P DIFF 2P2 LAN1_MDI0_N DIFF 2P3 LAN1_MDI1_P DIFF 2P4 LAN1_MDI1_N DIFF 2P7 LAN1_MDI2_P DIFF 2P8 LAN1_MDI2_N DIFF 2P9 LAN1_MDI3_P DIFF 2P10 LAN1_MDI3_N DIFF ...

Page 56: ...re Information 42 3 5 Subcompact Board GENE ADP6 2 4 26 LAN Port 1 LED Connector CN28 Pin Pin Name Signal Type Signal Level 1 LINK1_ACT I O 2 V3P3A PWR 3 3V 3 LAN1_1000 I O 4 LAN1_100 I O 5 LAN1_100 I O 6 LAN1_1000 I O ...

Page 57: ... 27 USB 3 2 USB 2 0 Port 3 CN29 Pin Pin Name Signal Type Signal Level 1 5VSB PWR 5V 2 USB2_3_DN DIFF 3 USB2_3_DP DIFF 4 GND GND GND 5 USB3_3_RXN DIFF 6 USB3_3_RXP DIFF 7 GND GND GND 8 USB3_3_TXN DIFF 9 USB3_3_TXP DIFF Note The driving current of 5VSB supports up to 0 9A ...

Page 58: ...R 5V 2 USB2_1_DN DIFF 3 USB2_1_DP DIFF 4 GND GND GND 5 USB3_1_RXN DIFF 6 USB3_1_RXP DIFF 7 GND GND GND 8 USB3_1_TXN DIFF 9 USB3_1_TXP DIFF 10 5VSB PWR 5V 11 USB2_2_DN DIFF 12 USB2_2_DP DIFF 13 GND GND GND 14 USB3_2_RXN DIFF 15 USB3_2_RXP DIFF 16 GND GND GND 17 USB3_2_TXN DIFF 18 USB3_2_TXP DIFF Note The driving current of 5VSB supports up to 0 9A Port ...

Page 59: ...el 1 DP_TX0_DP DIFF 2 GND GND GND 3 DP_TX0_DN DIFF 4 DP_TX1_DP DIFF 5 GND GND GND 6 DP_TX1_DN DIFF 7 DP_TX2_DP DIFF 8 GND GND GND 9 DP_TX2_DN DIFF 10 DP_TX3_DP DIFF 11 GND GND GND 12 DP_TX3_DN DIFF 13 DP_OB_AUX_EN IN 14 GND GND GND 15 DP_AUX_DP I O 16 GND GND GND 17 DP_AUX_DN I O 18 DP_HPD I O 19 GND GND GND 20 3 3V PWR 3 3V ...

Page 60: ...l Type Signal Level 1 HDMI_TX2 DIFF 2 GND GND GND 3 HDMI_TX2 DIFF 4 HDMI_TX1 DIFF 5 GND GND GND 6 HDMI_TX1 DIFF 7 HDMI_TX0 DIFF 8 GND GND GND 9 HDMI_TX0 DIFF 10 HDMI_CLK DIFF 11 GND GND GND 12 HDMI_CLK DIFF 13 N A N A N A 14 N A N A N A 15 DDC_CLK I O 16 DDC_DATA I O 17 GND GND GND 18 V5S PWR 5V 19 HDMI_HPD IN ...

Page 61: ...Level A1 GND GND GND A2 TCP2_TX0_DP DIFF A3 TCP2_TX0_DN DIFF A4 5VSB PWR 5V A5 CON_CC1 IN A6 USB2_10_DP DIFF A7 USB2_10_DN DIFF A8 CONN_TYPEC1_SBU1 DIFF A9 5VSB PWR 5V A10 TCP2_TXRX1_DN DIFF A11 TCP2_TXRX1_DP DIFF A12 GND GND GND B1 GND GND GND B2 TCP2_TX1_DP DIFF B3 TCP2_TX1_DN DIFF B4 5VSB PWR 5V B5 CONN_TYPEC1_CC2 IN ...

Page 62: ...ct Board GENE ADP6 Pin Pin Name Signal Type Signal Level B6 USB2_10_DP DIFF B7 USB2_10_DN DIFF B8 CONN_TYPEC1_SBU2 DIFF B9 5VSB PWR 5V B10 TCP2_TXRX0_DN DIFF B11 TCP2_TXRX0_DP DIFF B12 GND GND GND Note The driving current of 5VSB supports up to 3A ...

Page 63: ...P3S PWR 3 3V 3 V3P3S PWR 3 3V 4 SMB_DATA I O 5 SMB_CLK OUT 3 3V 6 BUF_PLT_RST OUT 3 3V 7 V3P3A PWR 3 3V 8 GND GND GND 9 PCIE4_B_1_RXP DIFF 10 PCIE4_B_1_RXN DIFF 11 GND GND GND 12 PCIE4_B_3_RXP DIFF 13 PCIE4_B_3_RXN DIFF 14 GND GND GND 15 PCIE4_B_2_RXP DIFF 16 PCIE4_B_2_RXN DIFF 17 GND GND GND 18 PCIE4_B_0_RXP DIFF 19 PCIE4_B_0_RXN DIFF 20 GND GND GND ...

Page 64: ... PCIE4_B_1_TXN DIFF 28 PCIE4_B_1_TXP DIFF 29 GND GND GND 30 PCIE_3_GEN4_CLK_DN DIFF 31 PCIE_3_GEN4_CLK_DP DIFF 32 GND GND GND 33 PCIE4_B_0_TXN DIFF 34 PCIE4_B_0_TXP DIFF 35 GND GND GND 36 V12S PWR 12V 37 V12S PWR 12V 38 V12S PWR 12V 39 V12S PWR 12V 40 V12S PWR 12V Note The driving current of V12S supports up to 2 1A Note The driving current of V3P3A supports up to 0 375A Note The driving current o...

Page 65: ...e Information 51 3 5 Subcompact Board GENE ADP6 2 4 33 LAN Port 2 LED Connector CN36 Pin Pin Name Signal Type Signal Level 1 LINK2_ACT I O 2 V3P3A PWR 3 3V 3 LAN2_1000 I O 4 LAN2_2500 I O 5 LAN2_2500 I O 6 LAN2_1000 I O ...

Page 66: ...Chapter 2 Hardware Information 52 3 5 Subcompact Board GENE ADP6 2 5 Thermal Solutions 2 5 1 Active Cooling Fan GENE ADP6 FAN01 ...

Page 67: ...Chapter 2 Hardware Information 53 3 5 Subcompact Board GENE ADP6 GENE ADP6 FAN01 Assembly ...

Page 68: ...Chapter 2 Hardware Information 54 3 5 Subcompact Board GENE ADP6 2 5 2 Heatspreader GENE ADP6 HSP01 ...

Page 69: ...Chapter 2 Hardware Information 55 3 5 Subcompact Board GENE ADP6 GENE ADP6 HSP01 Assembly ...

Page 70: ...3 5 Subcompact Board GENE ADP6 Chapter 3 Chapter 3 AMI BIOS Setup ...

Page 71: ...he CMOS memory and BIOS NVRAM If system configuration is not found or system configuration data error is detected system will load optimized default and re boot with this default system configuration automatically There are four situations in which you will need to setup system configuration 1 You are starting your system for the first time 2 You have changed the hardware attached to your system 3...

Page 72: ...formation when the power is turned off Entering Setup Power on the computer and press Del or ESC immediately This will allow you to enter Setup Main Set the date use tab to switch between date elements Advanced Enable disable boot option for legacy network devices Chipset Host bridge parameters Boot Enables disable quiet boot option Security Set setup administrator password Save Exit Exit system s...

Page 73: ...Chapter 3 AMI BIOS Setup 59 3 5 Subcompact Board GENE ADP6 3 3 Setup Submenu Main ...

Page 74: ...Chapter 3 AMI BIOS Setup 60 3 5 Subcompact Board GENE ADP6 3 4 Setup Submenu Advanced ...

Page 75: ... hardware capabilities provided by Vanderpool Technology Hyper Threading Disabled Enabled Optimal Default Failsafe Default Enable or Disable Hyper Threading Technology Intel SpeedStep Disabled Enabled Optimal Default Failsafe Default Allows more than two frequency ranges to be supported Turbo Mode Disabled Enabled Optimal Default Failsafe Default Enable or Disable processor Turbo Mode requires EMT...

Page 76: ...62 3 5 Subcompact Board GENE ADP6 Options Summary C states Disabled Enabled Optimal Default Failsafe Default Enable Disable CPU Power Management Allows CPU to go to C states when it s not 100 utilized 3 4 2 PCH FW Configuration ...

Page 77: ...4 3 Firmware Update Configuration Options Summary Me FW Image Re Flash Enabled Disabled Optimal Default Failsafe Default Enable Disable Me FW Image Re Flash function FW Update Disabled Enabled Optimal Default Failsafe Default Enable Disable ME FW Update function ...

Page 78: ... 4 PTT Configuration Options Summary TPM Device Selection dTPM Optimal Default Failsafe Default PTT Selects TPM device PTT or discrete TPM PTT enables PTT in SkuMgr dTPM disables PTT is SkuMgr Warning PTT dTPM will be disabled and all data saved on it will be lost ...

Page 79: ...TCG EFI protocol and INT1A interface will not be available SHA256 PCR Bank Enabled Optimal Default Failsafe Default Disabled Enable or Disable SHA256 PCR Bank SHA384 PCR Bank Enabled Optimal Default Failsafe Default Disabled Enable or Disable SHA384 PCR Bank Pending operation None Optimal Default Failsafe Default TPM Clear Schedule an Operation for the Security Device NOTE Your Computer will reboo...

Page 80: ... Default Failsafe Default Disabled Enable or Disable Endorsement Hierarchy Physical Presence Spec Version 1 3 Optimal Default Failsafe Default 1 2 Select to Tell O S to support PPI Spec Version 1 2 or 1 3 Note some HCK tests might not support 1 3 Device Select Auto TPM 1 2 TPM 2 0 Optimal Default Failsafe Default TPM 1 2 will restrict support to TPM 1 2 devices TPM 2 0 will restrict support to TPM...

Page 81: ...efault Failsafe Default Disabled Enable Disable SATA Device M 2 KEY B CN6 Enabled Optimal Default Failsafe Default Disabled Enable or Disable SATA Port Port 1 CN3 Enabled Optimal Default Failsafe Default Disabled Enable or Disable SATA Port Hot Plug Disabled Optimal Default Failsafe Default Enabled Designates this port as Hot Pluggable ...

Page 82: ...Chapter 3 AMI BIOS Setup 68 3 5 Subcompact Board GENE ADP6 3 4 7 Hardware Monitor Options Summary Smart Fan Disable Enable Optimal Default Failsafe Default Enables or Disables Smart Fan ...

Page 83: ...inear Fan Application Output PWM mode push pull Optimal Default Failsafe Default Fan 1 Smart Fan Control Manual Duty Mode Auto Duty Cycle Mode Optimal Default Failsafe Default Smart Fan Mode Select Temperature Source CPU Temperature System Temperature System Temperature 2 Optimal Default Failsafe Default Select the monitored temperature source for this fan ...

Page 84: ... BIOS Setup 70 3 5 Subcompact Board GENE ADP6 Options Summary Temperature 1 Duty Cycle 1 60 85 Auto fan speed control Fan speed will follow different temperature by different duty cycle 1 100 3 4 8 SIO Configuration ...

Page 85: ...lt Failsafe Default Enable or Disable this Logical Device Possible Use Automatic Settings Optimal Default Failsafe Default IO 3F8h IRQ 4 IO 2F8h IRQ 3 Allows user to change Device s Resource settings New settings will be reflected on This Setup Page after System restarts Mode RS232 Optimal Default Failsafe Default RS422 RS485 UART RS232 422 485 selection ...

Page 86: ...lt Failsafe Default Enable or Disable this Logical Device Possible Use Automatic Settings Optimal Default Failsafe Default IO 3F8h IRQ 4 IO 2F8h IRQ 3 Allows user to change Device s Resource settings New settings will be reflected on This Setup Page after System restarts Mode RS232 Optimal Default Failsafe Default RS422 RS485 UART RS232 422 485 selection ...

Page 87: ...t Failsafe Default Enable or Disable this Logical Device Possible Use Automatic Settings Optimal Default Failsafe Default IO 3E8h IRQ 11 IO 2E8h IRQ 11 Allows user to change Device s Resource settings New settings will be reflected on This Setup Page after System restarts Mode RS232 Optimal Default Failsafe Default RS422 RS485 UART RS232 422 485 selection ...

Page 88: ...t Failsafe Default Enable or Disable this Logical Device Possible Use Automatic Settings Optimal Default Failsafe Default IO 2E8h IRQ 11 IO 3E8h IRQ 11 Allows user to change Device s Resource settings New settings will be reflected on This Setup Page after System restarts Mode RS232 Optimal Default Failsafe Default RS422 RS485 UART RS232 422 485 selection ...

Page 89: ...Serial Port Console Redirection Options Summary Console Redirection Disabled Optimal Default Failsafe Default Enabled Console Redirection Enable or Disable Console Redirection EMS Disabled Optimal Default Failsafe Default Enabled Console Redirection Enable or Disable ...

Page 90: ...nd Legacy OPROM message Resolution 80x24 Optimal Default Failsafe Default 80x25 On Legacy OS the number of Rows and Columns supported redirection Redirect After POST Always Enable Optimal Default Failsafe Default BootLoader When Bootloader is selected then Legacy Console Redirection is disabled before booting to legacy OS When Always Enable is selected then Legacy Console Redirection is enabled fo...

Page 91: ... Timer second 30 Optimal Default Failsafe Default Timer count set to Watch Dog Timer for POST WARNING Do not set to a value equal or shorter than normal POST time otherwise system may never complete POST unless clearing BIOS settings More than 2x normal POST time is suggested Sends watch dog before booting OS Disabled Optimal Default Failsafe Default Enabled Enabled Robot set Watch Dog Timer WDT a...

Page 92: ...hold BIOS from POST Delayed POST DXE phase Disabled Optimal Default Failsafe Default Enabled Enabled Robot holds BIOS before POST completion This allows BIOS POST to start with stable power or start after system is physically warmed up Note Robot does this after Sends watch dog before BIOS POST Delayed time second 10 Optimal Default Failsafe Default Period of time for Robot to hold BIOS from POST ...

Page 93: ... supply mode Restore AC Power Loss Last State Optimal Default Failsafe Default Always On Always Off Select power state when power is re applied after a power failure RTC wake system from S5 Disable Optimal Default Failsafe Default Fixed Time Bypass Fixed Time System will wake on the hr min sec specified Bypass BIOS will not control RTC wake function during system shutdown ...

Page 94: ...AMI BIOS Setup 80 3 5 Subcompact Board GENE ADP6 3 4 13 Digital IO Port Configuration Options Summary DIO Port Output Input Set DIO as Input or Output Output Level High Low Set output level when DIO pin is output ...

Page 95: ...Chapter 3 AMI BIOS Setup 81 3 5 Subcompact Board GENE ADP6 3 5 Setup Submenu Chipset ...

Page 96: ...Chapter 3 AMI BIOS Setup 82 3 5 Subcompact Board GENE ADP6 3 5 1 System Agent SA Configuration Options Summary VT d Disabled Optimal Default Failsafe Default Enabled VT d capability ...

Page 97: ...Chapter 3 AMI BIOS Setup 83 3 5 Subcompact Board GENE ADP6 3 5 2 Memory Configuration ...

Page 98: ... Optimal Default Failsafe Default Enable Disabled this panel LVDS Panel Type 640x480 18bit 60Hz 800x480 18bit 60Hz 800x600 18bit 60Hz 1024x600 18bit 60Hz 1024x768 18bit 60Hz 1024x768 24bit 60Hz Optimal Default Failsafe Default 1280x768 24bit 60Hz 1280x1024 48bit 60Hz 1366x768 24bit 60Hz 1440x900 48bit 60Hz 1600x1200 48bit 60Hz ...

Page 99: ...selecting the appropriate setup item Panel Mode Single Channel Optimal Default Failsafe Default Dual Channel Panel mode selection for Single channel or Dual channel Color Depth 18 bit Optimal Default Failsafe Default 24 bit 36 bit 48 bit Select panel type Backlight Mode BIOS Application Windows Slider Optimal Default Failsafe Default Select backlight control signal type ...

Page 100: ...highlight these items and press Enter a dialog box appears which lets you enter a password You can enter no more than six letters or numbers Press Enter after you have typed in the password A second dialog box asks you to retype the password for confirmation Press Enter after you have retyped it correctly The password is required at boot time or when the user enters the Setup utility Removing the ...

Page 101: ...em is in User mode The mode change requires platform reset Secure Boot Mode Custom Optimal Default Failsafe Default Standard Secure Boot mode options Standard or Custom In Custom mode Secure Boot Policy variables can be configured by a physically present user without full authentication Restore Factory Keys Force System to User Mode Install factory default Secure Boot key databases Reset to Setup ...

Page 102: ...r mode The mode change requires platform reset Restore Factory Keys Force System to User Mode Install factory default Secure Boot key databases Reset to Setup Mode Delete all Secure Boot key databases from NVRAM Export Secure Boot variables Copy NVRAM content of Secure Boot variables to files in a root folder on a file system device Enroll Efi Image Allow the image to run in Secure Boot mode Enrol...

Page 103: ... Delete Key Exchange Keys Details Export Update Append Delete Authorized Signatures Details Export Update Append Delete Forbidden Signatures Details Export Update Append Delete Authorized TimeStamps Update Append OsRecovery Signatures Update Append Enroll Factory Defaults or load certificates from a file 1 Public Key Certificate a EFI_SIGNATURE_LIST b EFI_CERT_X509 DER c EFI_CERT_RSA2048 bin d EFI...

Page 104: ...nu Boot Options Summary Quiet Boot Disabled Enabled Optimal Default Failsafe Default Enable or Disable Quiet Boot option UEFI PXE Support Disabled Optimal Default Failsafe Default Enabled Enable Disable UEFI Network Stack FIXED BOOT ORDER Priorities Sets the system boot order ...

Page 105: ...Chapter 3 AMI BIOS Setup 91 3 5 Subcompact Board GENE ADP6 3 7 1 BBS Priorities ...

Page 106: ... ADP6 3 8 Setup Submenu Save Exit Options Summary Save Changes and Reset Reset the system after saving the changes Discard Changes and Exit Exit system setup without saving any changes Restore Defaults Restore Load Default values for all the setup options ...

Page 107: ...Chapter 3 AMI BIOS Setup 93 3 5 Subcompact Board GENE ADP6 3 9 Setup Submenu MEBx ...

Page 108: ...mmary Password Policy Default Password Only During Setup and Configuration Anytime Optimal Default Failsafe Default Network Access State Network Active Network Inactive Optimal Default Failsafe Default Full Unprovision Changes network state of ME When disabling it will also clear some other settings ...

Page 109: ...ons Summary SOL Disabled Enabled Optimal Default Failsafe Default Enable FW SOL Interface Storage Redirection Disabled Enabled Optimal Default Failsafe Default Enable FW Remote Storage Redirection KVM Features Selection Disabled Enabled Optimal Default Failsafe Default Enable FW KVM Feature ...

Page 110: ...sent Options Summary User Opt in None KVM Optimal Default Failsafe Default ALL Configure When User Consent Should be Required Opt in Configurable from Remote IT Disabled Enabled Optimal Default Failsafe Default Enable Disable Remote Change Capability of User Consent Feature ...

Page 111: ...97 3 5 Subcompact Board GENE ADP6 3 9 4 Power Control Options Summary ME ON in Host Sleep States Mobile ON in S0 Optimal Default Failsafe Default Mobile ON in S0 ME Wake in S3 S4 5 AC only Idle Timeout 15 Timeout Value 1 65536 ...

Page 112: ...3 5 Subcompact Board GENE ADP6 Chapter 4 Chapter 4 Driver Installation ...

Page 113: ...ere you unzipped the Audio Drivers 2 Run the Setup exe in the folder 3 Follow the instructions 4 Drivers will be installed automatically Chipset Driver Windows 10 11 1 Open the folder where you unzipped the Chipset Drivers 2 Run the SetupChipset exe file in the folder 3 Follow the instructions 4 Drivers will be installed automatically Graphics Driver Windows 10 11 1 Open the folder where you unzip...

Page 114: ... folder where you unzipped the Peripheral Drivers 2 Run the SetupSerialIO exe file in the folder 3 Follow the instructions 4 Drivers will be installed automatically ME TXE Drivers Windows 10 11 1 Open the folder where you unzipped the ME TXE Drivers 2 Run the SetupME exe file in the folder 3 Follow the instructions 4 Drivers will be installed automatically SST Drivers Windows 10 11 1 Open the fold...

Page 115: ...3 5 Subcompact Board GENE ADP6 Appendix A Appendix A I O Information ...

Page 116: ...Appendix A I O Information 102 3 5 Subcompact Board GENE ADP6 A 1 I O Address Map ...

Page 117: ...Appendix A I O Information 103 3 5 Subcompact Board GENE ADP6 ...

Page 118: ...Appendix A I O Information 104 3 5 Subcompact Board GENE ADP6 A 2 Memory Address Map ...

Page 119: ...Appendix A I O Information 105 3 5 Subcompact Board GENE ADP6 A 3 IRQ Mapping Chart ...

Page 120: ...Appendix A I O Information 106 3 5 Subcompact Board GENE ADP6 ...

Page 121: ...Appendix A I O Information 107 3 5 Subcompact Board GENE ADP6 ...

Page 122: ...3 5 Subcompact Board GENE ADP6 Appendix B Appendix B Mating Connectors and Cables ...

Page 123: ... ACES 50247 020H0H0 001 170X000231 CN12 COM Port 1 2 ACES 50247 020H0H0 001 170X000231 CN13 USB Port 1 2 ACES 50247 010H0H0 001 170010010D CN14 Digital I O MOLEX 51110 1050 N A CN15 USB Port 3 4 ACES 50247 010H0H0 001 170010010D CN17 LVDS Inverter ACES 50236 006H0H0 001 170X000152 CN20 eDP I PEX 20453 040T 3 170X000313 CN21 LVDS Hirose DF13 30DS 1 25C 170430030Y CN22 I2C SMBUS Debug JST SHR 12V S ...

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