Astronics OMNIBUS II NI PXIe, User Manual

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OMNIBUS II FEATURES
OmniBus II NI PXIe User Manual 4-7
The following Table 4.8 lists the protocols supported on each pin. Users can select
between the two pins on Core A for PPS and PCM IRIG signals.
Note: The timing pins on the OmniBus II family are distinct and not internally
connected as they were in the OmniBus family.
Timing Protocol Core/Pin PPS TSM Config Constant
PPS/PCM IRIG Core A Pin 17 TSMCFG_PPS0
PPS/PCM IRIG Core A Pin 47 TSMCFG_PPS1
Table 4.8—PPS Pinout
4.3.4 10MHz
A 50% duty cycle, 10 MHz sine wave is a method of system synchronization,
usually used to regulate a frequency generator or oscillator. The OB2 can use the
10 MHz signal in master mode (output) or slave
mode (input). When using the 10
MHz in slave mode, the OB2 will continuously monitor the phase of the 10 MHz
input relative the local clock oscillator and adjust the frequency of the local clock
to follow the input 10 MHz signal.
10 MHz Input Characteristics
Min input impedance (at 1 kHz)
10 kΩ
Max input amplitude (V
pk-pk
) 8 V
10 MHz Output Characteristics
Output amplitude (V
pk-pk
) 1.4 V
Max output resistive load 45
Ω
Table 4.9—10 MHz Input/Output Characteristics
The following Table 4.10 lists the pin supporting the 10 MHz protocol.
Note: The timing pins on the OmniBus II family are distinct and not internally
connected as they were in the OmniBus family.
Timing Protocol Core/Pin TSM Config Constant
10MHz Core B Pin 47 TSMCFG_10MHZ
Table 4.10—10 MHz Pinout
4.4 Core Discretes
OB2 products have both input and output discrete capability. OB2 has eight
bidirectional TTL level discretes per core that can be used as either inputs or
outputs. Each discrete output line has a 5-V TTL driver that can source or sink up
to 8 mA and has an individual tristate control; the discrete input receiver is a 5 V