Chapter 10 INTERFACE SETTINGS
461
10.12.5. V-by-One ®HS Unit
V-By-One®HS
CH1
CH2
CH3
CH4
Connector
V-by-One®HSx4 (16Lane)
Dot clock
Number of data lane 1lane
Single clock mode
8 bit : 20 to 85 MHz
10 bit : 20 to 85 MHz
12 bit : 20 to 75 MHz
Number of data lane
2lanes
Single clock mode
8 bit
: 40 to 170 MHz
10 bit
: 40 to 170 MHz
12 bit
: 40 to 150 MHz
Number of data lane
4lanes
Single clock mode
8 bit
: 80 to 340 MHz
10 bit
: 80 to 340 MHz
12 bit
: 80 to 300 MHz
Number of data lane
8lanes
Dual clock mode
*1
8 bit
: 160 to 680 MHz
10 bit
: 160 to 680 MHz
12 bit
: 160 to 600 MHz
Number of data lane
16lanes
Quad clock mode
*2
8 bit
: 320 to 1360 MHz
10 bit
: 320 to 1360 MHz
12 bit
: 320 to 1200 MHz
Output color numbers
RGB each 8/10/12bit
(
RGB/YCbCr supported
)
*1 By using 2 channles:CH1-CH2
(
CH3-CH4
)
, 8 lanes are output.
*2 By using 4 channels: CH1-CH2-CH3-CH4, 16 lanes are output.
10.12.6. SDI Unit
SDI output is available for the below standard timings only.
SMPTE259M, SMPTE 274M, SMPTE 296M
270Mb/s
SMPTE259M
SD-SDI
Interlace
720 x 480, 720 x 525
YCbCr 4:2:2 10bit
525/59.94i,625/50i
1.485Gb/s SMPTE274M
HD-SDI
Interlace
Progressive
Segmented Frame
1920 x 1080
YCbCr 4:2:2 10bit
60i, 59.94i, 50i
30p, 29.97p, 25p, 24p, 23.98p
30PsF, 29.97PsF, 25PsF, 24PsF, 23.98PsF
SMPTE296M
HD-SDI
Progressive
1280 x 720
YCbCr 4:2:2 10bit
60p, 59.94p, 50p, 30p, 29.97p, 25p, 24p, 23.98p
Summary of Contents for VG-876
Page 1: ...Video Signal Generator VG 876 Instruction Manual Ver 3 40 ...
Page 2: ......
Page 30: ...16 ...
Page 57: ...Chapter 3 TIMING DATA SETTINGS 43 ...
Page 103: ...Chapter 4 PATTERN SETTINGS 89 1 2 3 4 5 6 0 ...
Page 134: ...120 GUI Display Selected port ...
Page 135: ...Chapter 4 PATTERN SETTINGS 121 HEX Display Selected port ...
Page 143: ...Chapter 4 PATTERN SETTINGS 129 ...
Page 177: ...Chapter 6 HDCP SETTINGS AND EXECUTION 163 ...
Page 205: ...Chapter 7 VG 876 SYSTEM SETTINGS 191 ...
Page 223: ...Chapter 8 DATA COPYING ERASING 209 ...
Page 237: ...Chapter 9 USEFUL FUNCTIONS 223 ...
Page 336: ...322 10 5 3 Data transfer method Normal MODE 2Lane output ...
Page 338: ...324 Normal MODE 4Lane output ...
Page 376: ...362 Assignment of each lane ...
Page 378: ...364 Assignment of each lane Lane 1 4 Lane 9 12 Lane 5 8 Lane 13 16 ...
Page 380: ...366 Assignment of each lane Lane1 4 Lane9 12 Lane5 8 Lane 13 16 ...
Page 382: ...368 Assignment of each lane Lane1 8 Lane9 16 ...
Page 384: ...370 Assignment of each lane Lane1 8 Lane9 16 ...
Page 386: ...372 Assignment of each lane Lane1 8 Lane9 16 ...
Page 388: ...374 Assignment of each lane Lane1 4 Lane9 12 Lane5 8 Lane 13 16 ...
Page 390: ...376 Assignment of each lane Lane1 4 Lane9 12 Lane5 8 Lane 13 16 ...
Page 392: ...378 Assignment of each lane Lane1 16 ...
Page 453: ...Chapter 10 INTERFACE SETTINGS 439 Connection figure of VM 1876 MX s ...
Page 464: ...450 Reverse Mode Top Bottom Reverse Mode LR TB ...
Page 466: ...452 Reverse Mode Top Bottom Reverse Mode LR TB ...
Page 468: ...454 Reverse Mode Top Bottom Reverse Mode LR TB ...
Page 495: ...Chapter 10 INTERFACE SETTINGS 481 2 When Video Width is 8 bit ...
Page 496: ...482 3 When Video Width is 10 bit ...
Page 501: ...Chapter 10 INTERFACE SETTINGS 487 2 When iTMDS output ...
Page 504: ......
Page 538: ...524 ...