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DRAM Configuration
DRAM Tweaker
Fine tune the DRAM settings by leaving marks in checkboxes. Click OK to confirm and
apply your new settings.
DRAM Timing Configuration
CAS# Latency (tCL)
The time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay and Row Precharge (tRCDtRP)
RAS# to CAS# Delay : The number of clock cycles required between the opening of
a row of memory and accessing columns within it.
Row Precharge: The number of clock cycles required between the issuing of the
precharge command and opening the next row.
RAS# Active Time (tRAS)
The number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
The delay between when a memory chip is selected and when the first active command can
be issued.
Refresh Cycle Time (tRFC)
The number of clocks from a Refresh command until the first Activate command to
the same rank.
Save User Default
Type a profile name and press enter to save your settings as user default.
