[AKD2300]
<KM103501> 2015/02
5
BCLK
FS
DX
MSB
DR
Don't
care
LSB
MSB
LSB
<JST>
BCLK
FS
DX
MSB
DR
Don't care
LSB
MSB
LSB
<DLY>
DSW4-4
Switch Name
Function
DLY/JST
PCM Interface settings3
This switch selects input and output timing of PCM data.
DLY(DIF1 = L)
:
MSB of DX/DR are input/output by next rising edge of BCLK after the
rising edge of FS. (Refer to the Figure 2)
JST(DIF1 = H)
:
MSB of DX/DR are input/output by rising edge of FS. (Refer to the
Figure 2