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Revision B User Manual 

 for the VME-SIO4: Board Revision: A 

General Standards Corporation 

8302A Whitesburg Drive Huntsville, AL 3580, Phone: (256) 880-8787 

12

CHAPTER 2:  THEORY OF OPERATION 

 
 

2.0 

THE BOARD INTERFACE 

 

This board operates as an interface for two Zilog Z16C30s, giving it Quad Channel capabilities.  The Zilogs are 
mapped into the base address of this board and all reads and writes are PIOs. This board does not offer DMA across 
the VMEbus.  All references to DMA in this documentation are in reference to moving data from the external FIFOs 
into the Zilogs or  from the Zilogs into the receive FIFOs, by means of an “onboard only” DMA.  These FIFOs 
operate as additional buffering of 32 K bytes for both transmit and receive. These FIFOs are in addition to the 
internal FIFOs of the Zilog;  however, these FIFOs are not at the same address location.  To implement the use of the 
external FIFOs, the software must first initialize the Zilog to request DMA services for transmit or receive.  When 
the request is made, the onboard logic will either move the data from the transmit FIFO into the Zilog or from the 
Zilog into the receive FIFOs depending on which request was made.   
 

2.1 

INTERRUPTS 

 
The interrupts on this board are divided into two sections: 
 

a.  

Master Board Interrupts:

 For use with conditions on the board, not pertaining to the Zilogs. 

b.  

Zilog Interrupts:

 For use with conditions within the Zilog, not pertaining to the Board. 

 
The interrupts for the onboard logic use the master vector register.  The interrupts for the Zilog use the Zilog vector 
registers.  All interrupts are mapped directly to the VME and they are prioritized via “Round Robin” going from 0 to 
3 and then to the master board.  No two levels of interrupts will occur at the same time.  The interrupt level is 
selected via jumper. 
 

2.2 

DESCRIPTION OF DMA 

 

DMA for all channels is performed in the same manner.  The request is made, that is, one of the transmit or receive 
DMA request signals  go active from the Zilog.  The onboard DMA logic will handshake with the Zilog to either 
acknowledge valid data going to the Zilog or to get receive data from the Zilog.  This activity will continue until the 
Zilog no longer needs DMA service, or the external FIFOs can no longer comply.  If the Zilog no longer wants 
DMA, it will remove its request and the DMA will stop.  The conditions at which the FIFOs can no longer comply 
are when during a transmit request and the transmit FIFO is empty or during a receive request when a receive FIFO 
is full.  Channel 0 and 1 operate using the same Zilog bus, so therefore it must arbitrate between Channel 0 transmit 
and receive, as well as Channel 1 transmit and receive.  This arbitration takes place without any software 
initialization. 
 
If all four (4) DMA requests are active at the same time, this will handshake one word for one request and then 
proceed to the next.  It will start with the receive data and will acknowledge one word for the receive of Channel 0, 
then one word of the receive for Channel 1, then one word for the transmit for Channel 0, then one word of the 
transmit for Channel 1 and then it will start over. 
 
This transmission of data from one point to another will only occur if the FIFO’s are in a valid state, i.e., transmit 
FIFO must not be empty; otherwise the handshake will not take place with the Zilog.  Then, the Zilog will not get an 
acknowledge for its’ transmit request and will get no data.   
 
The same is true for the receive FIFO.  If the receive FIFO is full, the DMA will not remove data from the Zilog.  
Therefore the Zilog will not get an acknowledge, and will not have any data removed from it. 
 
Channels 2 and 3 work in the same way, but work on a different data bus.  Therefore DMAs for Channels 2 and 3, to 
or from the Zilog will not affect Channels 0 and 1.  This means Channel 0 can run at full speed and Channel 2 can 

Summary of Contents for VME-SIO4A

Page 1: ...buy your excess underutilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stock Ready to ship TAR certified secure asset solutions Expert team I Trust guarantee I 100 satisfaction All trademarks brand names and brands appearing herein are the property of th...

Page 2: ...n 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 1 VME SIO4A User Manual Manual Revision B General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Fax 256 880 8788 URL http www generalstandards com E mail techsupport generalstandards com ...

Page 3: ...tion contained in this document General Standards Corporation does not assume any liability arising out of the application or use of any product or circuit described herein nor is any license conveyed under any patent right of any rights of others General Standards Corporation assumes no responsibility resulting from omissions or errors in this manual or from the use of information contained herei...

Page 4: ...pecialized parts used on this board EIA Standard for the RS 422 A Interface EIA order number EIA RS 422A VMEbus Specification Manual also known as IEC 821 BUS and IEEE P10114 D1 2 for information submit request to VITA10229 North Scottsdale Road Suite B Scottsdale AZ 85253 Telephone 602 951 8866 Zilog s USC Universal Serial Controller part number Z16C30 User s Manual and Databook for information s...

Page 5: ... 9 September 30 1997 Section 3 1 5 3 moved D3 7 and D8 15 to end of list deleted D0 7 text Changed heading format created new table of contents Section 2 3 Reworded Section 3 1 2 1 added note about self timed pulse Section 3 1 4 changed reference to is status and is not status to is empty and is not empty Section 3 1 5 1 added almost to bit descriptions D11and D13 Section 3 1 5 3 inserted descript...

Page 6: ...er 15 3 1 2 I O CONTROL REGISTERS 15 3 1 2 1 Channel 0 Control Register same format for Channels 1 3 Control Registers 15 3 1 3 Channel 0 FIFO same format for Channels 1 3 FIFO 16 3 1 4 Channel 0 FIFO Status Register same format for Channels 1 3 FIFO Status Registers 16 3 1 5 INTERRUPT CONTROL STATUS REGISTERS 17 3 1 5 1 Interrupt Control Register 17 3 1 5 2 Interrupt Status Register Dual Purpose ...

Page 7: ...in Control Register Address 01101 32 3 1 6 14 1 Low Offset Address 0x34 32 3 1 6 14 2 High RW Offset Address 0x36 32 3 1 6 15 Misc Interrupt Status Register Address 01110 33 3 1 6 15 1 Low Offset Address 0x38 33 3 1 6 15 2 High Offset Address 0x3A 33 3 1 6 16 status interrupt control Register Address 01111 33 3 1 6 16 1 Low Offset Address 0x3C 33 3 1 6 16 2 High Offset Address 0x3E65 33 3 1 6 17 T...

Page 8: ...Transmit Sync Register Address 11100 39 3 1 6 28 1 Low Offset Address 0x70 39 3 1 6 28 2 High Offset Address 0x72 39 3 1 6 29 Transmit Count Limit Register Address 11101 39 3 1 6 29 1 Low Offset Address 0x74 39 3 1 6 29 2 High Offset Address 0x76 40 3 1 6 30 Transmit Character Count Register Address 11110 40 3 1 6 30 1 Low Offset Address 0x78 40 3 1 6 30 2 High Offset Address 0x7A 40 3 1 6 31 Time...

Page 9: ...r hence this board cannot act as a VME bus master 7 The card also provides for self test loop back for verification of proper operation b The following two modes of loop back testing will be supported 1 internal loop back testing does not drive cable 2 external loop back testing via an external loop back test cable 1 1 FUNCTIONAL DESCRIPTION As shown in the functional block diagram see Figure 1 1 ...

Page 10: ...Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 9 Figure 1 1 1 Functional Block Diagram ...

Page 11: ... been initialized 1 7 DATA TRANSMIT Data is received into the Zilog Z16C30 after which the software may write data to the master FIFOs or to the Zilog depending on how the Z16C30 has been initialized At this point the Zilog can be placed into a transmit mode 1 8 LOOP BACK TESTING The card is designed with sufficient built in loop back testing capability in order to allow software to perform fault ...

Page 12: ...annel 1 Receiver is empty d Channel 2 Receiver is empty e Channel 3 receiver is empty f IRQ Pending g VME Access h Spare LED 1 12 CABLE INTERFACE CONNECTIONS There are four female DB25 cable interface user I O interface connectors mounted at the front edge of the board P3 Channel 0 P4 Channel 1 P5 Channel 2 P6 Channel 3 The pinout is shown below Signal Name Rev N R Rev A Lower TxD RxD Pin 25 Pin 3...

Page 13: ...A DMA for all channels is performed in the same manner The request is made that is one of the transmit or receive DMA request signals go active from the Zilog The onboard DMA logic will handshake with the Zilog to either acknowledge valid data going to the Zilog or to get receive data from the Zilog This activity will continue until the Zilog no longer needs DMA service or the external FIFOs can n...

Page 14: ...it is possible to transmit both If the channel control register is not told to transmit or receive upper and not told to transmit or receive lower then this board will not drive the cable nor will it load the cable i e this channel will be tri stated If an external loopback test is desired to be performed without a cable the software can set it up to do transmit upper or lower and to receive the s...

Page 15: ...16 RW Channel 0 FIFO 0x1A D16 RW Channel 1 FIFO 0x1C D16 RW Channel 2 FIFO 0x1E D16 RW Channel 3 FIFO FIFO 0x20 D16 RO Channel 0 FIFO Status Status 0x22 D16 RO Channel 1 FIFO Status Registers 0x24 D16 RO Channel 2 FIFO Status 0x26 D16 RO Channel 3 FIFO Status Sync Word 0x28 D16 RW Channel 0 Sync Word Register Registers 0x2A D16 RW Channel 1 Sync Word Register 0x2C D16 RW Channel 2 Sync Word Regist...

Page 16: ...ard to generate VME interrupts 0 will disable the board from generating VME interrupts D2 3 Reserved D4 Spare LED On A software controlled bit 1 will turn off the Fail LED 0 will turn on the Fail LED D5 6 Reserved D7 Fail LED On L A software controlled bit 1 will turn off the Fail LED 0 will turn on the Fail LED D8 D15 Reserved 3 1 1 4 Board Status Register D0 D15 Reserved 3 1 2 I O CONTROL REGIST...

Page 17: ...TATUS REGISTER SAME FORMAT FOR CHANNELS 1 3 FIFO STATUS REGISTERS D0 Tx FIFO Empty L 0 indicates that the Tx FIFO is empty 1 indicates that the Tx FIFO is not empty D1 Tx FIFO Almost Empty L 0 indicates that the Tx FIFO is almost empty 1 indicates that the Tx FIFO is not almost empty D2 Tx FIFO Almost Full L 0 indicates that the Tx FIFO is almost full 1 indicates that the Tx FIFO is not almost ful...

Page 18: ...nterrupt 1 will enable this board to generate an interrupt when the Tx FIFO is empty 0 will disable this board from generating an interrupt when the Tx FIFO is empty D6 Enable Channel 3 Tx Sync Detected 1 will enable this board to generate an interrupt when a Tx Sync word is detected 0 will disable this board from generating an interrupt when a Tx Sync word is detected D7 Enable Channel 3 Tx FIFO ...

Page 19: ... has occurred 0 indicates an interrupt has not occurred If this interrupt is not enabled 0 indicates the current status of this interrupt source 1 being the source of the interrupt is present 0 being not true the source of the interrupt is not present D1 Channel 0 Tx FIFO Empty Interrupt If this interrupt is enabled 1 indicates an interrupt has occurred 0 indicates an interrupt has not occurred If...

Page 20: ...s an interrupt has occurred 0 indicates an interrupt has not occurred If this interrupt is not enabled 0 indicates the current status of this interrupt source 1 being the source of the interrupt is present 0 being the source of the interrupt is not present D8 Channel 0 Rx FIFO Not Empty Interrupt If this interrupt is enabled 1 indicates an interrupt has occurred 0 indicates an interrupt has not oc...

Page 21: ...2 Rx FIFO Almost Full Interrupt If this interrupt is enabled 1 indicates an interrupt has occurred 0 indicates an interrupt has not occurred If this interrupt is not enabled 0 indicates the current status of this interrupt source 1 being the source of the interrupt is present 0 being the source of the interrupt is not present D14 Channel 3 Rx FIFO Not Empty Interrupt If this interrupt is enabled 1...

Page 22: ... Enable Channel 1 Rx FIFO Not Empty Interrupt Enable Channel 1 Rx FIFO Almost Full Interrupt 110 Enable Channel 2 Rx FIFO Not Empty Interrupt Enable Channel 2 Rx FIFO Almost Full Interrupt 111 Enable Channel 3 Rx FIFO Not Empty Interrupt Enable Channel 3 Rx FIFO Almost Full Interrupt D3 D7 Software Selectable D8 D15 Reserved 3 1 5 SERIAL CONTROLLER REGISTERS Contact your local Zilog Represenative ...

Page 23: ...nel Load DMA 0 0 1 0 1 Trigger Rx DMA 0 0 1 1 0 Trigger Tx DMA 0 0 1 1 1 Trigger Rx Tx DMA 0 1 0 0 0 Reserved 0 1 0 0 1 Rx FIFO Purge 0 1 0 1 0 Tx FIFO Purge 0 1 0 1 1 Rx Tx FIFO Purge 0 1 1 0 0 Reserved 0 1 1 0 1 Load Rx Character Count 0 1 1 1 0 Load Tx Character Count 0 1 1 1 1 Load RX Tx Character Count 1 0 0 0 0 Reserved 1 0 0 0 1 Load TCO 1 0 0 1 0 Load TC1 1 0 0 1 1 Load TC0 TC1 1 0 1 0 0 S...

Page 24: ...1 Transparent Bisync 1 0 0 0 NBIP 1 0 0 1 802 3 1 0 1 0 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved Rx Submode D7 RW D6 RW D5 RW D4 RW 3 2 1 0 3 1 6 2 2High Offset Address 0x06 Transmitter Mode D3 RW D2 RW D1 RW D0 RW Bit Map 0 0 0 0 Asynchronous 0 0 0 1 Reserved 0 0 1 0 Isochronous 0 0 1 1 Asynchronous with CV 0 1 0 0 Monosync 0 1 0 1 Bisync 0 1 1...

Page 25: ...Loop HDLC Tx Last Character Length D4 RW D3 RW D2 RW Bit Map 1 1 1 7 Bits 1 1 0 6 Bits 1 0 1 5 Bits 1 0 0 4 Bits 0 1 1 3 Bits 0 1 0 2 Bits 0 0 1 1 Bit 0 0 0 0 Bits D0 RO Tx ACK D1 RO Rx ACK 3 1 6 3 2High Offset Address 0x0A D2 RW Clocks Missed Latched Unlatch D3 RW Clocks Missed Latched Unlatch D4 RW DPLL in Sync Quick Sync D5 WO RCC FIFO Clear D6 RO RCC FIFO Valid D7 RO RCC FIFO Overflow DLL Adju...

Page 26: ... 1 6 4 2High Address 00011 Tx Status Block Transfer Offset Address 0x0E D7 RW D6 RW Bit Map 0 0 No Status Block 0 1 One Word Status Block 1 0 Two Word Status Block 1 1 Reserved D4 RW Tx Flag Preamble D5 RW Wait for Tx DMA Trigger Tx Preamble Length D3 RW D2 RW Bit Map 0 0 8 Bits 0 1 16 Bits 1 0 32 Bits 1 1 64 Bits Tx Preamble Pattern All Sync D1 RW D2 RW All Zeros 0 0 All Zeros 0 1 All Ones 1 0 Al...

Page 27: ...T MODE CONTROL REGISTER ADDRESS 00111 3 1 6 8 1Low Offset Address 0x1C Test Register Address D4 RW D3 RW D2 RW D1 RW D0 RW Bit Map 0 0 0 0 0 Null Address 0 0 0 0 1 High Byte of Shifters 0 0 0 1 0 CRC Byte 0 0 0 0 1 1 CRC Byte 1 0 0 1 0 0 Rx FIFO Write 0 0 1 0 1 Clock Multiplexer Outputs 0 0 1 1 0 CTR0 and CTR1 Counters 0 0 1 1 1 Clock Multiplexer Inputs 0 1 0 0 0 DPLL State 0 1 0 0 1 Low Byte of S...

Page 28: ...W Reserved 3 1 6 8 2High Offset Address 0x1E D0 D7 RW Reserved 3 1 6 9 CLOCK MODE CONTROL REGISTER ADDRESS 01000 3 1 6 9 1Low Offset Address 0x20 Receive Clock Source D2 RW D1 RW D0 RW Bit Map 0 0 0 Disabled 0 0 1 RxC Pin 0 1 0 TxC Pin 0 1 1 DPLL Output 1 0 0 BRG0 Output 1 0 1 BRG1 Output 1 1 0 CTR0 Output 1 1 1 CTR1 Output Transmit Clock Source D5 RW D4 RW D3 RW Bit Map 0 0 0 Disabled 0 0 1 RxC P...

Page 29: ... Bit Map 0 0 CTR0 Output 0 1 CTR1 Output 1 0 RxC Pin 1 1 TxC Pin BRG1 Clock Source D3 RW D2 RW Bit Map 0 0 CTR0 Output 0 1 CTR1 Output 1 0 RxC Pin 1 1 TxC Pin CRT0 Clock Source D5 RW D4 RW Description 0 0 BRG0 Output 0 1 BRG1 Output 1 0 RxC Pin 1 1 TxC Pin CTR1 Clock Source D7 RW D6 RW Description 0 0 Disabled 0 1 Disabled 1 0 RxC Pin 1 1 TxC Pin 3 1 6 10 HARDWARE CONFIGURATION REGISTER ADDRESS 01...

Page 30: ...n Control D7 RW D6 RW Bit Map 0 0 3 State Output 0 1 Tx Acknowledge Input 1 0 Output 0 1 1 Output 1 3 1 6 10 2 High Offset Address 0x26 DPLL Mode D1 RW D0 RW Bit Map 0 0 Disabled 0 1 NRZ NRZI 1 0 Biphase Mark Space 1 1 Biphase Level PLL Clock Rate RW D2 RW Bit Map 0 0 32x Clock Mode 0 1 16x Clock Mode 1 0 8x Clock Mode 1 1 Reserved D5 RW Accept Code Violations D4 RW CTR1 Rate Match DPLL CTR0 CTR0 ...

Page 31: ...mit Data 1 0 0 Transmit Status 1 0 1 Receive Data 1 1 0 Receive Status 1 1 1 Not Used D4 D7 IV 4 7 3 1 6 12 I O CONTROL REGISTER ADDRESS 01011 3 1 6 12 1 Low Offset Address 0x2C RxC Pin Control D2 RW D1 RW D0 RW Bit Map 0 0 0 Input Pin 0 0 1 Rx Clock Output 0 1 0 Rx Byte Clock Output 0 1 1 SYNC Output 1 0 0 BRG0 Output 1 0 1 BRG1 Output 1 1 0 CTR0 Output 1 1 1 DPLL Rx Output TxC Pin Control D5 RW ...

Page 32: ...ut 0 1 1 Output 1 TxREQ Pin Control D3 RW D2 RW Bit Map 0 0 3 State Output 0 1 Rx Request Output 1 0 Output 0 1 1 Output 1 DCD Pin Control D5 RW D4 RW Bit Map 0 0 DCD Input 0 1 DCD SYNC Input 1 0 Output 0 1 1 Output 1 CTS Pin Control D7 RW D6 RW Bit Map 0 0 CTS Input 0 1 CTS Input 1 0 Output 0 1 1 Output 1 3 1 6 13 INTERRUPT CONTROL REGISTER ADDRESS 01100 3 1 6 13 1 Low Offset Address 0x30 D0 RW D...

Page 33: ...Transmit Status and Above 1 0 1 Receive Data and Above 1 1 0 Receive Status Only 1 1 1 None D7 RW MIE D6 RW DLC D5 RW NV D4 RW VIS 3 1 6 14 DAISY CHAIN CONTROL REGISTER ADDRESS 01101 3 1 6 14 1 Low Offset Address 0x34 D0 RW Device Status IP D1 RW I O Status IP D2 RW Transmit Data IP D3 RW Transmit Status IP D4 RW Receive Data IP D5 RW Receive Status IP IP Command D7 WO D6 WO Bit Map 0 0 Null Comma...

Page 34: ...3 RW RCC Overflow Latched Unlatch D4 RO CTS D5 RW CTS Latched Unlatch D6 RO DCD D7 RW DCD Latched Unlatch 3 1 6 15 2 High Offset Address 0x3A D0 RO TxREQ D1 RW TxREQ Latched Unlatch D2 RO RxREQ D3 RW RxREQ Latched Unlatch D4 RO TxC D5 RW TxC Latched Unlatch D6 RO RxC D7 RW RxC Latched Unlatch 3 1 6 16 STATUS INTERRUPT CONTROL REGISTER ADDRESS 01111 3 1 6 16 1 Low Offset Address 0x3C D0 RW BRG0 ZC ...

Page 35: ...High Offset Address 0x42 D0 7 RW Tx Rx Data 8 15 3 1 6 18 RECEIVER MODE REGISTER ADDRESS 10001 3 1 6 18 1 Low Offset Address 0x44 Rx Enable D1 RW D0 RW Bit Map 0 0 Disable Immediately 0 1 Disable After Reception 1 0 Enable Without Auto Enables 1 1 Enable With Auto Enables Rx Character Length D4 RW D3 RW D2 RW Bits 0 0 0 8 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 0 5 1 1 0 6 1 1 0 7 D5 RW Rx Parity Enab...

Page 36: ...phase Level 3 1 6 19 RECEIVE COMMAND STATUS REGISTER ADDRESS 10010 3 1 6 19 1 Low Offset Address 0x48 D0 RO Rx Character Available D1 RW Rx Overrun D2 RW Parity Error Frame Abort D3 RO CRC Framing Error D4 RW Rx CV EOT EOF D5 RW Rx Break Abort D6 RW Rx Idle D7 RW Exited Hunt 3 1 6 19 2 High Offset Address 0x4A D0 RO Short Frame CV Polarity D1 RO Residue Code 0 D2 RO Residue code 1 D3 RO Residue Co...

Page 37: ...un IA D2 RW Parity Error Frame Abort IA D3 RW Status on Words D4 RW Rx CV EOT EOF IA D5 RW Rx Break Abort IA D6 RW Rx Idle IA D7 RW Exited Hunt IA 3 1 6 20 2 High Offset Address 0x4E D0 D7 RW Rx FIFO Control and Status Fill Interrupt DMA Level 3 1 6 21 RECEIVE SYNC REGISTER ADDRESS 10100 3 1 6 21 1 Low Offset Address 0x50 D0 D7 RW RSYN 0 7 3 1 6 21 2 High Offset Address 0x52 D0 D7 RW RSYN 0 7 3 1 ...

Page 38: ...ss 0x5E D0 7 RW TC0 0 7 3 1 6 25 TRANSMIT MODE REGISTER ADDRESS 11001 3 1 6 25 1 Low Offset Address 0x64 Tx Enable D1 RW D0 RW Bit Map 0 0 Disable Immediately 0 1 Disable After Transmission 1 0 Enable Without Auto Enables 1 1 Enable With Auto Enables Tx Character Length D4 RW D3 RW D2 RW Bit Maps 0 0 0 8 Bits 0 0 1 1 Bit 0 1 0 2 Bits 0 1 1 3 Bits 1 0 0 4 Bits 1 0 1 5 Bits 1 1 0 6 Bits 1 1 1 7 Bits...

Page 39: ...NRZI Space 1 0 0 Biphase Mark 1 0 1 Biphase Space 1 1 0 Biphase Level 1 1 1 Diff Biphase Level 3 1 6 26 TRANSMIT COMMAND STATUS REGISTER ADDRESS 11010 3 1 6 26 1 Low Offset Address 0x68 D0 RO Tx Buffer Empty D1 RW Tx Underrun D2 RO All Sent D3 RW Tx CRC Sent D4 RW Tx EOF EOT Sent D5 RW Tx Abort Sent D6 RW Tx Idle Sent D7 RW Tx Preamble Sent 3 1 6 26 2 High Offset Address 0x6A Tx Idle Line Conditio...

Page 40: ...hibit 1 1 0 1 Set DLE Inhibit 1 1 1 0 Reset EOF EOM 1 1 1 1 Set EOF EOM 3 1 6 27 TRANSMIT INTERRUPT CONTROL REGISTER ADDRESS 11011 3 1 6 27 1 Low Offset Address 0x6C D0 RW TC1R Read Count TC D1 RW Tx Overrun IA D2 RW Wait for Send Command D3 RW Tx CRC Sent IA D4 RW Tx EOF EOT Sent IA D5 RW Tx Abort Sent IA D6 RW Tx Idle Sent IA D7 RW Tx Preamble Sent IA 3 1 6 27 2 High Offset Address 0x6E D0 7 RW ...

Page 41: ... 7 3 1 6 29 2 High Offset Address 0x76 D0 7 RW TCL 0 7 3 1 6 30 TRANSMIT CHARACTER COUNT REGISTER ADDRESS 11110 3 1 6 30 1 Low Offset Address 0x78 D0 7 RO TCC 0 7 3 1 6 30 2 High Offset Address 0x7A D0 7 RO TCC 0 7 3 1 6 31 TIME CONSTANT 1 REGISTER ADDRESS 11111 3 1 6 31 1 Low Offset Address 0x7C D0 7 RW TC1 0 7 3 1 6 31 2 High Offset Address 0x7E D0 7 RW TC1 0 7 ...

Page 42: ... 14 pin will fit into the socket of U28 thereby changing the on board transmit receive clock 4 1 IRQ LEVEL SELECT JUMPERS J6 These jumpers are used to select or determine the interrupt request level used by this board They use a binary encoded method with jumpers for pins 1 and 2 being the LSB of a 3 bit value If none of the jumpers are in this is a level select of the lowest priority 7 If all the...

Page 43: ...shown below Channel 0 2 Zilog uses the onboard OSC U28 for Transmit and Receive Channel 1 3 Zilog uses the onboard OSC for Transmit and cable Receive clock for Receive Cable Transmit clock will be onboard OSC Description of Jumpers shown above Channel 0 2 Zilog uses the on board OSC for Rcv and will generate and output a transmit clock of a software programmed frequency Channel 1 3 Zilog uses the ...

Page 44: ...l beside or be twisted with the signal If the jumpers are installed in the factory configuration then the following pin outs will apply Table 4 4 1 Pin Out for User Connectors P3 Channel 0 P4 Channel 1 P5 Channel 2 P6 Channel 3 Jumper Pin Signal Name Connector Pin 1 2 LWR Cable TxD RxD 3 3 4 LWR Cable TxD RxD 16 5 6 NC 7 8 LWR Cable Cts DCD 5 9 10 LWR Cable Cts DCD 18 11 12 NC 13 14 NC 15 16 Groun...

Page 45: ...quipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentation Artisan Scientific Corporation dba Artisan Technology Group is not an affiliate representative or authorized distributor for any manufacturer listed herein We re here to make your life easier How...

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