Artesyn BajaPPC-750, User Manual

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3-8 BajaPPC-750: Central Processing Unit
May 2002
The interrupt handler sends a command for the interrupting device to acknowl-
edge the interrupt and deassert 750_INT*.
3.5 Bus Speed
Bit 5 of the Board Configuration Register (see Register Map 3-5) at location
FF98,0020
16
indicates the local bus speed. A configuration resistor determines the
state of this bit (0 = 66 MHz, 1 = 83 MHz).
3.6 Cache Memory
The PPC750 processor has separate, on-chip, 32-kilobyte instruction and data
caches with eight-way, set-associative translation lookaside buffers (TLBs). The
CPU supports the modified/exclusive/invalid (MEI) cache coherency protocol.
Each cache has 128 entries and supports demand-paged virtual memory address
translation and variable-sized block translation. The PPC750 also employs
pseudo-least-recently used (PLRU) replacement algorithms for enhanced perfor-
mance.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CT2 CT1 ETH
J2x
INTD
J2x
INTC
J2x
INTB
J2x
INTA
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
J1x
INTD
J1x
INTC
J1x
INTB
J1x
INTA
LINT
7
LINT
6
LINT
5
LINT
4
LINT
3
LINT
2
LINT
1
LINT
0
ISA
INT
NMI
Register Map 3-4. BajaPPC-750 Interrupt Status
7 6 5 4 3 2 1 0
pwr_up P2_cfg bus_spd parity bank_config reserved
Register Map 3-5. BajaPPC-750 Board Configuration (Bus Speed)