Artesyn ATCA-7475, Installation And Use Manual

Page: 187 / 282

Maps and Registers
ATCA-7475 Installation and Use (6806800S38D)
187
When at least one bit of the Table "Telecom Clock Monitor Out of Range Register" on page 187
is set, the corresponding status bit CLK_MONITOR_OUT_OF_RANGE of Table "Telecom
Interrupt Control/Status Register" on page 165 is also set.
7:5 Reserved 0 r
Table 6-62 Telecom Clock Monitor Out of Range Register
Address: 0x63
Bit Description Default Access
4:0 Frequency of supervised Telecom Clock 0 to 4 is out of range.
Gate Mode:
Corresponding bit is set when the number of positive Clock
edges within the selected time base is:
< Lower limit or
> Upper limit
Period Mode:
Corresponding bit is set when the Clock 0 Period within the
selected time base is:
< Lower limit or
> Upper limit
Clearing bit triggers new sequence of measurements. 0 LPC: r/w1c
7:5 Reserved 0 r
Table 6-63 Telecom Clock Monitor Select Register
Address: 0x64
Bit Description Default Access
2:0 Select supervised Telecom Clocks. See Table "Supervised Telecom
Clocks Reference List" on page 186 .
0-4: Select corresponding clock
5-7: Reserved
0 LPC: r/w
Table 6-61 Telecom Clock Monitor Status Register (continued)
Address: 0x62
Bit Description Default Access