AT32F425
Series Reference Manual
2022.03.30
Page 243
Ver 2.01
Output compare mode:
Set CxOCTRL=2’b001/010/011 to enable output compare mode. In this
case, when the counter value matches the value of the CxDT register, the CxORAW is forced
high, low or toggling.
One-pulse mode:
This is a particular case of PWM mode. Set OCMEN=1 to enable one-pulse
mode. In this mode, the comparison match is performed in the current counting period. The
TMREN bit is cleared as soon as the current counting is completed. Therefore, only one pulse is
output. When configured as in upcounting mode, the configureation must follow the rule:
CVAL<CxDT≤PR; in downcounting mode, CVAL>CxDT is required.
Fast output mode:
Set CxOIEN=1 to enable this mode. If enabled, the CxORAW signal will not
change when the counter value matches the CxDT, but at the beginning of the current counting
period. In other words, the comparison result is advanced, so the comparison result between the
counter value and the TMRx_CxDT register will determine the level of CxORAW in advance.
gives an example of output compare mode (toggle) with C1DT=0x3. When the counter
value is equal to 0x3, C1OUT toggles.
gives an example of the combination between upcounting mode and PWM mode A. The
output signal behaves when PR=0x32 but CxDT is configured with a different value.
gives an example of the combination between upcounting mode and one-pulse PWM
mode B. The counter only counts only one cycle, and the output signal sents only one pulse.
Figure 14-70
C1ORAW toggles when counter value matches the C1DT value
0
1
2
3
...
31
32
0
1
2
3
...
31
32
0
1
2
3
COUNTER
31
32
0
1
...
PR[15:0]
C1ORAW
TMR_CLK
0
DIV[15:0]
32
011
C1OCTRL
[2
：
0]
3
C1DT[15
：
0]
Figure 14-71
Upcounting mode and PWM mode A
0
1
2
3
...
31
32
0
1
2
3
...
31
32
0
1
2
3
COUNTER
31
32
0
1
...
PR[15:0]
C1ORAW
TMR_CLK
0
DIV[15:0]
32
110
C1OCTRL[2
：
0]
3
C1DT[15
：
0]
C1ORAW
0
0
CIDT[15
：
0]
C1ORAW
32
C1DT[15
：
0]
1
C1ORAW
>32
C1DT[15
：
0]
