AT32F425
Series Reference Manual
2022.03.30
Page 168
Ver 2.01
a CS pulse error is detected. At this point, the detected pulse error will be discarded by the SPI. However,
since there is something wrong with the CS signal, the software should disable the SPI slave and re-
configure the SPI master before re-enabling the SPI slave for communication.
13.2.8 Transmitter
The SPI transmitter is clocked by SPI_SCK controller. It can output different data frame formats,
depending on software configuration. There is a SPI_DT register available in the SPI that is used to be
written with the data to be transmitted. When the transmitter is clocked, the contents in the SPI_DT
register are copied into the data buffer (Unlike SPI_DT, it is driven by SPI_SCK, and controlled by
hardware,instead of software), and sent out in order based on the programmed frame format.
Both DMA and CPU can be used for write operation. For DMA transfer, refer to DMA transfer section for
more details. For CPU transfer, attention should be paid to the TDBE bit. The reset value of this bit is 1,
indicating that the SPI_DT register is empty. If the TDBEIE bit is set, an interrupt is generated. After the
data is written, the TDBE is pulled low until the data is moved to the transmit data buffer before the TDBE
is set once again. This means that the user can be allowed to write the data to be transmitted only when
the TDBE is set.
After the transmitter is configured and the SPI is enabled, the SPI is ready for data transmission. Before
going forward, it is necessary for the users to refer to full-duplex / half-duplex chapter to get detailed
configuration information, go to the Chip select controller chapter for specific chip select mode, check
the SPI_SCK controller chapter for information on communication clock, and refer to CRC and DMA
transfer chapter to configure CRC and DMA (if necessary). The recommended configuration procedure
are as follows.
Transmitter configuration procedure:
Configure full-duplex/half-duplex selector
Configure chip select controller
Configure SPI_SCK controller
Configure CRC (if necessary)
Configure DMA transfer (if necessary)
If the DMA transfer mode is not used, the software will check whether to enable transmit data
interrupt (TDBEIE =1) through the TDBE bit.
Configure frame format: select MSB/LSB mmode with the LTF bit, and select 8/16-bit data with
the FBN bit
Enable SPI by setting the SPIEN
13.2.9 Receiver
The SPI receiver is clocked by the SPI_SCK controller. It can output different data frame formats through
software configuration. There is a receive data buffer register, driven by the SPI_SCK, in the SPI receiver.
At the last CLK of each transfer, the data is moved from the shift register to the receive data buffer
register. Then the transmitter sets the receive data complete flag to the SPI logic. When the flag is
detected by the SPI logic, the data in the receive data buffer is copied into the SPI_DT register, with the
RDBF being set. This means that the data is received, and it is already stored into the SPI_DT. In this
case, read access to the SPI_DT register will clear the RDBF bit.
Both DMA and CPU can be used for read operation. For DMA transfer, refer to DMA transfer section for
more details. For CPU transfer, attention should be paid to the RDBE bit. The reset value of this bit is 0,
indicating that the SPI_DT register is empty. If the data is received and moved into the SPI_DT, the
RDBF is set, meaning that there are some data to be read in the SPI_DT register. An interrupt is
generated if the RDBFIE bit is set.
When the next received data is ready to be moved to the SPI_DT register, if the previous received data
is still not read (RDBF=1), then the data overflow occurs. The previous receive data is not lost, but the
next received data will do. At this point, the ROERR is set. An interrupt is generated if the ERRIE is set.
Read SPI_DT register and then the SPI_STS register will clear the ROERR bit. The recommended
configuration procedure is as follows.
