ARTERY AT32F421 Series Reference Manual Download Page 151 | Manualshive

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AT32F421

Series Reference Manual

2022.11.11

Page 151

Rev 2.02

Figure 13-4 Single-wire unidirectional receive only in SPI slave mode

SPI master

SCK

MISO

MOSI

CS

SPI slave

SCK

MISO

MOSI

CS

In SPI master mode, it is necessary to wait until the second-to-last RDBF bit is set and then wait another
SPI_CPK cycle before disabling SPI. The last RDBF must be set before entering power-saving mode
(or gating SPI system clock).
In slave mode, there is no need to check any flag before disabling SPI. However, it is mandatory to wait
until the BF becomes 0 before entering power-saving mode.

Figure 13-5

shows single-wire bidirectional half-duplex mode and SPI IO connection

When the SLBEN is set, the SPI operates in single-wire bidirectional half-duplex mode. In this case,
the SPI supports data reception and transmission alternately. In master mode, the MOSI pin transmits
or receives data, while the IO mapped by MISO is released. In slave mode, the MISO pin transmits or
receives data, but the IO pin mapped by MOSI is released.
The SLBTD bit is used by software to configure transfer direction. When the SLBTD bit is set, the SPI
can be used only for data transmission; when the SLBTD bit is 0, the SPI can be used only for data
reception.

Figure 13-5

Single-wire bidirectional half-duplex mode

SPI master

SCK

MISO

MOSI

CS

SPI slave

SCK

MISO

MOSI

CS

When the SPI is used for data transmission in single-wire bidirectional half-duplex mode (master or
slave), the TDBE bit must be set, and the BF must be 0 before disabling SPI. The power-saving mode
(or gating SPI system clock) cannot be entered unless the SPI is disabled.
In master mode, when the SPI is used for data reception in single-wire bidirectional half-duplex mode, it
is necessary to wait until the second-to-last RDBF is set and then wait another SPI_SCK cycle before
disabling SPI. And the last RDBF must be set before entering power-saving mode (or gating SPI system
clock).

In slave mode, when the SPI is used for data reception in single-wire bidirectional half-duplex mode,
there is no need to check any flags before disabling SPI. However, the BT must be 0 before entering
power-saving mode (or disabling SPI system clock).

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Summary of Contents for AT32F421 Series

Page 1: ... internal reference voltage channel 2 x operational amplifiers DMA 5 channel DMA controller Peripherals supported timers ADC I2 S SPI I2 C and USART Debug mode Serial wire debug SWD and JTAG Up to 39 fast GPIOs All mappable to external interrupt vectors Almost 5 V tolerant All fast I Os registers accessible with fAHB speed Up to 10 Timers TMR 1 x 16 bit 7 channel advanced timer 6 channel PWM outpu...

Page 2: ...ash memory size register 33 1 3 2 Device electronic signature 33 2 Memory resources 34 2 1 Internal memory address map 34 2 2 Flash memory 35 2 3 SRAM memory 35 2 4 Peripheral address map 36 3 Power control PWC 39 3 1 Introduction 39 3 2 Main Features 39 3 3 POR LVR 40 3 4 Power voltage monitor PVM 40 3 5 Power domain 41 3 6 Power saving modes 41 3 7 PWC registers 43 3 7 1 Power control register P...

Page 3: ...ral reset register1 CRM_APB1RST 53 4 3 6 AHB peripheral clock enable register CRM_AHBEN 53 4 3 7 APB2 peripheral clock enable register CRM_APB2EN 54 4 3 8 APB1 peripheral clock enable register CRM_APB1EN 55 4 3 9 Battery powered domain control register CRM_BPDC 56 4 3 10 Control status register CRM_CTRLSTS 56 4 3 11 AHB peripheral reset register CRM_AHBRST 57 4 3 12 PLL configuration register CRM_...

Page 4: ...8 6 Flash address register FLASH_ADDR 76 5 8 7 User system data register FLASH_USD 76 5 8 8 Erase program protection status register FLASH_EPPS 76 5 8 9 Flash security library status register 0 SLIB_STS0 77 5 8 10 Flash security library status register1 SLIB_STS1 77 5 8 11 Security library password clear register SLIB_PWD_CLR 78 5 8 12 Security library additional status register SLIB_MISC_STS 78 5...

Page 5: ... input mode register GPIOx_OMODE x A H 88 6 3 3 GPIO drive capability register GPIOx_ODRVR x A H 88 6 3 4 GPIO pull up pull down register GPIOx_PULL x A H 88 6 3 5 GPIO input data register GPIOx_IDT x A H 89 6 3 6 GPIO output data register GPIOx_ODT x A H 89 6 3 7 GPIO set clear register GPIOx_SCR x A H 89 6 3 8 GPIO write protection register GPIOx_WPR x A H 89 6 3 9 GPIO multiplexed function low ...

Page 6: ...r register EXINT_ SWTRG 97 8 3 6 Interrupt status register EXINT_ INTSTS 97 9 DMA controller DMA 98 9 1 Introduction 98 9 2 Main features 98 9 3 Functional overview 98 9 3 1 DMA configuration 98 9 3 2 Handshake mechanism 99 9 3 3 Arbiter 99 9 3 4 Programmable data transfer width 100 9 3 5 Errors 101 9 3 6 Interrupts 101 9 3 7 Fixed DMA request mapping 101 9 4 DMA registers 102 9 4 1 DMA interrupt ...

Page 7: ...ing DMA 120 11 4 4 SMBus 121 11 4 5 I2 C interrupt requests 122 11 4 6 I2C debug mode 123 11 5 I2C registers 123 11 5 1 Control register1 I2C_CTRL1 123 11 5 2 Control register2 I2C_CTRL2 124 11 5 3 Own address register1 I2C_OADDR1 125 11 5 4 Own address register2 I2C_OADDR2 125 11 5 5 Data register I2C_DT 126 11 5 6 Status register1 I2C_STS1 126 11 5 7 Status register2 I2C_STS2 128 11 5 8 Clock co...

Page 8: ...Start bit and noise detection 141 12 9 Tx Rx swap 142 12 10Interrupt requests 142 12 11I O pin control 143 12 12USART registers 143 12 12 1 Status register USART_STS 144 12 12 2 Data register USART_DT 145 12 12 3 Baud rate register USART_BAUDR 145 12 12 4 Control register1 USART_CTRL1 145 12 12 5 Control register2 USART_CTRL2 146 12 12 6 Control register3 USART_CTRL3 147 12 12 7 Guard time and div...

Page 9: ...rupts 165 13 3 9 IO pin control 165 13 4 SPI registers 166 13 4 1 SPI control register1 SPI_CTRL1 Not used in I2 S mode 166 13 4 2 SPI control register2 SPI_CTRL2 167 13 4 3 SPI status register SPI_STS 168 13 4 4 SPI data register SPI_DT 168 13 4 5 SPICRC register SPI_CPOLY Not used in I2 S mode 168 13 4 6 SPIRxCRC register SPI_RCRC Not used in I2 S mode 169 13 4 7 SPITxCRC register SPI_TCRC 169 1...

Page 10: ... 184 14 2 3 4 TMR output function 186 14 2 3 5 TMR synchronization 190 14 2 3 6 Debug mode 192 14 2 4 TMR3 registers 192 14 2 4 1 Control register1 TMR3_CTRL1 193 14 2 4 2 Control register2 TMR3_CTRL2 194 14 2 4 3 Slave timer control register TMR3_STCTRL 194 14 2 4 4 DMA interrupt enable register TMR3_IDEN 195 14 2 4 5 Interrupt status register TMR3_ISTS 196 14 2 4 6 Software event register TMR3_S...

Page 11: ...nel mode register1 TMR14_CM1 209 14 3 4 6 Channel control register TMR14_CCTRL 212 14 3 4 7 Counter value TMR14_CVAL 212 14 3 4 8 Division value TMR14_DIV 212 14 3 4 9 Period register TMR14_PR 212 14 3 4 10 Channel 1 data register TMR14_C1DT 212 14 3 4 11 Channel input remap register TMR14_RMP 213 14 4 General purpose timer TMR15 214 14 4 1 TMR15 introduction 214 14 4 2 TMR15 main features 214 14 ...

Page 12: ...4 5 2 TMR16 and TMR17 main features 239 14 5 3 TMR16 and TMR17 functional overview 239 14 5 3 1 Count clock 239 14 5 3 2 Counting mode 240 14 5 3 3 TMR input function 241 14 5 3 4 TMR output function 242 14 5 3 5 TMR brake function 245 14 5 3 6 Debug mode 246 14 5 4 TMR16 and TMR17 registers 246 14 5 4 1 TMR16 and TMR17 control register1 TMRx_CTRL1 247 14 5 4 2 TMR16 and TMR17 control register2 TM...

Page 13: ...rrupt enable register TMR1_IDEN 276 14 6 4 5 TMR1 interrupt status register TMR1_ISTS 278 14 6 4 6 TMR1 software event register TMR1_SWEVT 279 14 6 4 7 TMR1 channel mode register1 TMR1_CM1 279 14 6 4 8 TMR1 channel mode register2 TMR1_CM2 281 14 6 4 9 TMR1 Channel control register TMR1_CCTRL 282 14 6 4 10 TMR1 counter value TMR1_CVAL 284 14 6 4 11 TMR1 division value TMR1_DIV 284 14 6 4 12 TMR1 pe...

Page 14: ...er register WDT_DIV 291 16 5 3 Reload register WDT_RLD 292 16 5 4 Status register WDT_STS 292 17 Enhanced real time clock ERTC 293 17 1 ERTC introduction 293 17 2 ERTC main features 293 17 3 ERTC functional overview 293 17 3 1 ERTC clock 293 17 3 2 ERTC initialization 294 17 3 3 ERTC calibration 296 17 3 4 Time stamp 296 17 3 5 Tamper detection 297 17 3 6 Multiplexed function output 297 17 3 7 ERT...

Page 15: ...domain data register ERTC_BPRx 305 18 Analog to digital converter ADC 306 18 1 ADC introduction 306 18 2 ADC main features 306 18 3 ADC structure 306 18 4 ADC functional overview 307 18 4 1 Channel management 307 18 4 1 1 Internal temperature sensor 308 18 4 1 2 Internal reference voltage 308 18 4 2 ADC operation process 308 18 4 2 1 Power on and calibration 308 18 4 2 2 Trigger 309 18 4 2 3 Sampl...

Page 16: ...equence register 3 ADC_OSQ3 321 18 5 12 ADC preempted sequence register ADC_ PSQ 322 18 5 13 ADC preempted data register x ADC_ PDTx x 1 4 322 18 5 14 ADC ordinary data register ADC_ ODT 322 19 Comparator COMP 323 19 1 COMP introduction 323 19 2 Main features 323 19 3 Interrupt management 323 19 4 Design tips 324 19 5 Functional overview 324 19 5 1 Analog comparator 324 19 5 2 Glitch filter 325 19...

Page 17: ...age 17 Rev 2 02 22 Debug DEBUG 332 22 1 Debug introduction 332 22 2 Debug and trace 332 22 3 I O pin control 332 22 4 DEBUG registers 332 22 4 1 DEBUG device ID DEBUG_IDCODE 333 22 4 2 DEBUG control register DEBUG_CTRL 334 23 Revision history 336 ...

Page 18: ...OMUX structure 84 Figure 8 1 External interrupt Event controller block diagram 95 Figure 9 1 DMA block diagram 98 Figure 9 2 Re arbitrate after request acknowledge 99 Figure 9 3 PWIDTH byte MWIDTH half word 100 Figure 9 4 PWIDTH half word MWIDTH word 100 Figure 9 5 PWIDTH word MWIDTH byte 100 Figure 11 1 I2C bus protocol 109 Figure 11 2 I2C function block diagram 110 Figure 11 3 Transfer sequence ...

Page 19: ...ource in master mode 162 Figure 13 19 Audio standard timings 165 Figure 13 20 I2 S interrupts 165 Figure 14 1 Basic timer block diagram 172 Figure 14 2 Counter timing diagram CK_INT divided by 1 172 Figure 14 3 Counter structure 173 Figure 14 4 Overflow event when PRBEN 0 173 Figure 14 5 Overflow event when PRBEN 1 173 Figure 14 6 Counter timing diagram internal clock divided by 4 173 Figure 14 7 ...

Page 20: ...value changing from 1 to 4 204 Figure 14 42 Counter structure 204 Figure 14 43 Overflow event when PRBEN 0 205 Figure 14 44 Overflow event when PRBEN 1 205 Figure 14 45 Input output channel 1 main circuit 205 Figure 14 46 Channel 1 input stage 206 Figure 14 47 Capture compare channel output stage channel 1 206 Figure 14 48 C1ORAW toggles when counter value matches the C1DT value 207 Figure 14 49 U...

Page 21: ...nsertion 245 Figure 14 89 TMR output control 246 Figure 14 90 Example of TMR brake function 246 Figure 14 91 Block diagram of advanced control timer 256 Figure 14 92 Count clock 257 Figure 14 93 Use CK_INT to drive counter with TMRx_DIV 0x0 and TMRx_PR 0x16 257 Figure 14 94 Block diagram of external clock mode A 258 Figure 14 95 Counting in external clock mode A with PR 0x32 and DIV 0x0 258 Figure...

Page 22: ...re 14 122 Example of suspend mode 272 Figure 14 123 Example of trigger mode 272 Figure 15 1 Window watchdog block diagram 287 Figure 15 2 Window watchdog timing diagram 288 Figure 16 1 WDT block diagram 290 Figure 17 1 ERTC block diagram 293 Figure 18 1 ADC1 block diagram 307 Figure 18 2 ADC basic operation process 308 Figure 18 3 ADC power on and calibration 309 Figure 18 4 Sequence mode 310 Figu...

Page 23: ...ster 86 Table 6 3 Multiplexed function configuration for port F using GPIO_F MUX register 86 Table 6 4 Hardware preemption 87 Table 6 5 GPIO register map and reset values 87 Table 8 1 External interrupt Event controller register map and reset value 96 Table 9 1 DMA error event 101 Table 9 2 DMA interrupt requests 101 Table 9 3 DMA requests for each channel 101 Table 9 4 DMA register map and reset ...

Page 24: ...tion versus encoder signals 263 Table 14 16 TMR1 register map and reset value 273 Table 14 17 Complementary output channel CxOUT and CxCOUT control bits with brake function 283 Table 15 1 Minimum and maximum timeout value when PCLK1 72 MHz 288 Table 15 2 WWDT register map and reset value 288 Table 16 1 WDT timeout period LICK 40kHz 291 Table 16 2 WDT register and reset value 291 Table 17 1 ERTC re...

Page 25: ...controller ERTC communication interfaces such as SPI I2C USART CMP 12 bit ADC programmable voltage monitor PVM and other peripherals Cortex M4 processer supports enhanced high performance DSP instruction set including extended single cycle 16 bit 32 bit multiply accumulator MAC dual 16 bit MAC instructions optimized 8 bit 16 bit SIMD operation and saturation operation instructions as shown in Figu...

Page 26: ...annel SRAM Controller Flash Controller 64KB Flash 16KB SRAM APB2 Bridge APB1 Bridge APB2 bus Freq Max 120MHz APB1 us Freq Max 120MHz CRM TMR3 TMR6 TMR14 ERTC PWC USART2 WWDT WDT EXINT TMR1 USART1 I2 C1 2 TMR15 TMR16 17 ADCIF1 ADC1 HICK 48 8MHz LICK 40KHz PLL Max 120MHz LEXT 32KHz POR LVR PVM LDO 1 2V SWD NVIC HCLK FCLK PCLK1 PCLK2 HEXT 4 25MHz Temperature Sensor GPIOA B C F SPI2 I2 S2 SPI1 I2 S1 S...

Page 27: ...Table WIC Interrupts and Power control SW JTAG SBUS DBUS IBUS 1 1 2 Bit band With the help of bit band read and write access to a single bit can be performed in the ordinary way of loading and storing The Cortex M4 memory includes two bit band regions the least significant 1M bytes of SRAM and the least significant 1Mbytes of peripherals In addition to access to bit band addresses their respective...

Page 28: ...bit band address first For a read operation read one word in the bit band region and then move the targeted bit to the right to LSB before returning LSB For a write operation first move the targeted bit to the left to the corresponding bit number then perform a read modify write operation on bit level The address ranges of two memories supporting bit band operations The lowest 1 Mbyte of the SRAM ...

Page 29: ...undesired bits Compare and jump For now you just need do Read the bit status from the bit band alias region Compare and jump Apart from making code more concise its important function is also reflected in multi task environment When it comes to multiple tasks it turns the read modify write operations into a hardware supported atomic operation to avoid the scenario where the read modify write opera...

Page 30: ...INT line 15_4 interrupt 0x0000_005C 8 15 Configurable Reserved 0x0000_0060 9 16 Configurable DMA channel 1 DMA channel 1 global interrupt 0x0000_0064 10 17 Configurable DMA channel 3_2 DMA channel 3_2 global interrupt 0x0000_0068 11 18 Configurable DMA channel 5_4 DMA channel 5_4 global interrupt 0x0000_006C 12 19 Configurable ADC_CMP ADC and CMP global interrupt 0x0000_0070 13 20 Configurable TMR...

Page 31: ...e program execution Get the initial value of the main stack pointer MSP from address 0x0000_0000 Get the initial value of the program counter PC from address 0x0000_0004 This value is a reset vector and LSB must be 1 Then take the instructions from the address corresponding to this value Figure 1 5 Reset process reset Fetch MSP Fetch reset vector Fetch 1st instruction Read address 0x0000_0000 Read...

Page 32: ...a BOOT0 and nBOOT1 are used to determine the specific memory from which CODE starts BOOT1 BOOT0 00 10 CODE starts from the main Flash memory BOOT1 BOOT0 11 CODE starts from Boot code BOOT1 BOOT0 01 CODE starts from SRAM After a system reset or when leaving from Standby mode the pin values of both nBOOT1 and BOOT0 will be relatched When booting from SRAM BOOT status will be latched In this case it ...

Page 33: ...nt resd Reserved 1 3 Device characteristics information Table 1 5 List of abbreviations for registers Register abbr Base address Reset value F_SIZE 0x1FFF F7E0 0xXXXX UID 31 0 0x1FFF F7E8 0xXXXX XXXX UID 63 32 0x1FFF F7EC 0xXXXX XXXX UID 95 64 0x1FFF F7F0 0xXXXX XXXX 1 3 1 Flash memory size register This register contains the information about Flash memory size Bit Abbr Reset value Type Descriptio...

Page 34: ...g Aliased to Flash or system memory according to BOOT pins configuration 0x0000_0000 0x07FF_FFFF 0x0800_0000 Flash Memory 0x0800_FFFF Reserved 0x0801_0000 0x1FFF_E400 Boot Memory User System Data 0x1FFF_F800 0x1FFF_F3FF 0x1FFF_F9FF 0x1FFF_FFFF Reserved Aliased to Flash or system memory or SRAM according to BOOT pins configuration 0x0000_0000 0x1FFF_FFFF 0x2000_0000 SRAM 0x2000_3FFF Reserved Periph...

Page 35: ...memory organization 32 KB The main memory contains only bank 1 32 Kbytes including 32 sectors 1 Kbyte per sector Table 2 2 Flash memory organization 32 KB Block Name Address range Main memory Bank1 32 KB Sector 0 0x0800 0000 0x0800 03FF Sector 1 0x0800 0400 0x0800 07FF Sector 2 0x0800 0800 0x0800 0BFF Sector 31 0x0800 7C00 0x0800 7FFF Information block 4K Boot loader 0x1FFF E400 0x1FFF F3FF 512B U...

Page 36: ...FLASH 0x4002 1400 0x4002 1FFF Reserved 0x4002 1000 0x4002 13FF Clock and reset manage CRM 0x4002 0800 0x4002 0FFF Reserved 0x4002 0400 0x4002 07FF Reserved 0x4002 0000 0x4002 03FF DMA 0x4001 8400 0x4001 7FFF Reserved 0x4001 8000 0x4001 83FF Reserved APB2 0x4001 7C00 0x4001 7FFF Reserved 0x4001 7800 0x4001 7BFF Reserved 0x4001 7400 0x4001 77FF Reserved 0x4001 7000 0x4001 73FF Reserved 0x4001 6C00 0...

Page 37: ...P APB1 0x4000 8000 0x4000 FFFF Reserved 0x4000 7C00 0x4000 7FFF Reserved 0x4000 7800 0x4000 7BFF Reserved 0x4000 7400 0x4000 77FF Reserved 0x4000 7000 0x4000 73FF Power control PWC 0x4000 6800 0x4000 6BFF Reserved 0x4000 6400 0x4000 67FF Reserved 0x4000 6000 0x4000 63FF Reserved 0x4000 5C00 0x4000 5FFF Reserved 0x4000 5800 0x4000 5BFF I2 C2 0x4000 5400 0x4000 57FF I2 C1 0x4000 5000 0x4000 53FF Res...

Page 38: ...s Peripherals 0x4000 1C00 0x4000 1FFF Reserved 0x4000 1800 0x4000 1BFF Reserved 0x4000 1400 0x4000 17FF Reserved 0x4000 1000 0x4000 13FF TMR6 timer 0x4000 0C00 0x4000 0FFF Reserved 0x4000 0800 0x4000 0BFF Reserved 0x4000 0400 0x4000 07FF TMR3 timer 0x4000 0000 0x4000 03FF Reserved ...

Page 39: ...by an embedded LDO in the VDD VDDA domain Figure 3 1 Block diagram of each power supply Wake Up Logic I O Ring VSSA VREF From 2 4 V up to VDDA VREF VDD VDDA VSS VSSA VSS VDD LDO POR VDD Power domain 1 2v Power domain VDD Power domain VDDA Power domain CPU WDT LICK Memory Digital Peripherals PLL HICK PVM sleeping deepsleep LEXT ERTC CRM BPDC Register A D Converter CMP 3 2 Main Features Two power do...

Page 40: ...eset POR and low voltage reset LVR Figure 3 2 Power on reset Low voltage reset waveform Reset VDD VLVR VPOR Temporization tRESTTEMPO VPOR VLVR hysteresis 3 4 Power voltage monitor PVM The PVM is used to monitor the power supply variations It is enabled by setting the PVMEN bit in the power control register PWC_CTRL and the threshold value for voltage monitor is selected with the PVMSEL 2 0 bit Aft...

Page 41: ...e Sleep mode Deepsleep mode and Standby mode to save power Users can select the mode that gives the best compromise according to the low power consumption short startup time and available wakeup sources In addition the power consumption in Run mode can be reduced by slowing down the system clocks or gating the clocks to the APB and AHB peripherals when they are not used Sleep mode The Sleep mode i...

Page 42: ... the interrupt generated on any external interrupt line in Interrupt mode can wake up the system from Deepsleep mode 2 When the Sleep mode is entered by executing a WFE instruction the interrupt generated on any external interrupt line in Event mode can wake up the system from Deepsleep mode When the MCU exits the Deepsleep mode the HICK RC oscillator is enabled and selected as a system clock afte...

Page 43: ... boundary select 000 Unused not configurable 001 2 3 V 010 2 4 V 011 2 5 V 100 2 6 V 101 2 7 V 110 2 8 V 111 2 9 V Bit 4 PVMEN 0x0 rw Power voltage monitoring enable 0 Disabled 1 Enabled Bit 3 CLSEF 0x0 wo Clear SEF flag 0 No effect 1 Clear the SEF flag Note This bit is cleared by hardware after clearing the SEF flag Reading this bit at any time will return all zero Bit 2 CLSWEF 0x0 wo Clear SWEF ...

Page 44: ... by hardware after system reset Bit 7 3 Reserved 0x00 resd Kept at its default value Bit 2 PVMOF 0x0 ro Power voltage monitoring output flag 0 Power voltage is higher than the threshold 1 Power voltage is lower than the threshold Note The power voltage monitor is stopped in Standby mode Bit 1 SEF 0x0 ro Standby mode entry flag 0 Device is not in Standby mode 1 Device is in Standby mode Note This b...

Page 45: ...al ceramic resonator and bypass clock The HEXT crystal ceramic resonator is connected externally to a 4 25 MHz HEXT crystal that produces a highly accurate clock for the system The HEXT clock signal is not released until it becomes stable An external clock source can be provided by HEXT bypass Its frequency can be up to 25 MHz The external clock signal should be connected to the HEXT_IN pin while ...

Page 46: ...n be kept running in Deepsleep mode and Standby mode for watchdog and auto wakeup unit The LICK clock signal is not released before it becomes stable 4 1 2 System clock After a system reset the HICK oscillator is selected as system clock The system clock can make flexible switch among HICK oscillator HEXT oscillator and PLL clock However a switch from one clock source to another occurs only when t...

Page 47: ... then handled by NVIC when the AHB bus resumes 4 1 6 Internal clock output The microcontroller allows the internal clock signal to be output to external CLKOUT pins That is ADCCLK SCLK LICK LEXT HICK HEXT PLLCLK 2 and PLLCLK 4 can be used as CLKOUT clocks 4 1 7 Interrupts The microcontroller specifies a stable flag for each clock source As a result when a clock source is enabled it is possible to ...

Page 48: ...ower on if VDD has been powered off Software reset affects only the battery powered domain 4 3 CRM registers These peripheral registers have to be accessed by bytes 8 bits half words 16 bits or words 32 bits Table 4 1 CRM register map and reset values Register Offset Reset value CRM_CTRL 0x000 0x0000 XX83 CRM_CFG 0x004 0x0000 0000 CRM_CLKINT 0x008 0x0000 0000 CRM_APB2RST 0x00C 0x0000 0000 CRM_APB1...

Page 49: ...nd cleared by software It can also be cleared by hardware when entering Standby or Deepsleep mode When the HEXT clock is used as the system clock this bit cannot be cleared 0 OFF 1 ON Bit 15 8 HICKCAL 0xXX rw High speed internal clock calibration The default value of this field is the initial factory calibration value When the HICK output frequency is 48 MHz it needs adjust 240 kHz design value ba...

Page 50: ...9 010011 PLL x 20 111110 PLL x 63 111111 PLL x 64 Bit 17 PLLHEXTDIV 0x0 rw HEXT division selection for PLL entry clock 0 No division 1 HEXT 2 Bit 16 PLLRCS 0x0 rw PLL reference clock select 0 HICK divided clock 4MHz 1 HEXT clock Bit 28 Bit 15 14 ADCDIV 0x0 rw ADC division The PCLK divided by the following factors serves the ADC 000 PCLK 2 001 PCLK 4 010 PCLK 6 011 PCLK 8 100 PCLK 2 101 PCLK 12 110...

Page 51: ...ar Writing 1 by software to clear CFDF 0 No effect 1 Clear Bit 22 21 Reserved 0x0 resd Kept at its default value Bit 20 PLLSTBLFC 0x0 wo PLL stable flag clear Writing 1 by software to clear PLLSTBLF 0 No effect 1 Clear Bit 19 HEXTSTBLFC 0x0 wo HEXT stable flag clear Writing 1 by software to clear HEXTSTBLF 0 No effect 1 Clear Bit 18 HICKSTBLFC 0x0 wo HICK stable flag clear Writing 1 by software to...

Page 52: ... by words half words and bytes Bit Name Reset value Type Description Bit 31 19 Reserved 0x0000 resd Kept at its default value Bit 18 TMR17ST 0x0 resd TMR17 reset 0 Does not reset TMR17 1 Reset TMR17 Bit 17 TMR16ST 0x0 rw TMR16 set 0 Does not reset TMR16 1 Reset TMR16 Bit 16 TMR15ST 0x0 rw TMR15 reset 0 Does not reset TMR15 1 Reset TMR15 Bit 15 Reserved 0x0 resd Kept at its default value Bit 14 USA...

Page 53: ...11 WWDTRST 0x0 rw WWDT reset 0 Does not reset WWDT 1 Reset WWDT Bit 10 9 Reserved 0x0 resd Kept at its default value Bit 8 TMR14RST 0x0 rw TMR14 reset 0 Does not reset TMR14 1 Reset TMR14 Bit 7 5 Reserved 0x0 resd Kept at its default value Bit 4 TMR6RST 0x0 rw TMR6 reset 0 Does not reset TMR6 1 Reset TMR6 Bit 3 2 Reserved 0x0 resd Kept at its default value Bit 1 TMR3RST 0x0 rw TMR3 reset 0 Does no...

Page 54: ...wait states are inserted until the completion of the peripheral access on APB2 Bit Name Reset value Type Description Bit 31 19 Reserved 0x0000 resd Kept at its default value Bit 18 TMR17EN 0x0 rw TMR17 clock enable 0 Disabled 1 Enabled Bit 17 TMR16EN 0x0 rw TMR16 clock enable 0 Disabled 1 Enabled Bit 16 TMR15EN 0x0 rw TMR15 clock enable 0 Disabled 1 Enabled Bit 15 Reserved 0x0 resd Kept at its def...

Page 55: ...C1EN 0x0 rw I2C1 clock enable 0 Disabled 1 Enabled Bit 20 18 Reserved 0x0 resd Kept at its default value Bit 17 USART2EN 0x0 rw USART2 clock enable 0 Disabled 1 Enabled Bit 16 15 Reserved 0x0 resd Kept at its default value Bit 14 SPI2EN 0x0 rw SPI2 clock enable 0 Disabled 1 Enabled Bit 13 12 Reserved 0x0 resd Kept at its default value Bit 11 WWDTEN 0 rw WWDT clock enable 0 Disabled 1 Enabled Bit 1...

Page 56: ...is reset 00 No clock 01 LEXT 10 LICK 11 HEXT 128 Bit 7 3 Reserved 0x00 resd Kept at its default value Bit 2 LEXTBYPS 0x0 rw Low speed external crystal bypass 0 Disabled 1 Enabled Bit 1 LEXTSTBL 0x0 ro Low speed external oscillator stable Set by hardware after the LEXT is ready 0 LEXT is not ready 1 LEXT is ready Bit 0 LEXTEN 0x0 rw External low speed oscillator enable 0 Disabled 1 Enabled 4 3 10 C...

Page 57: ...s set or cleared by software 0 Does not reset GPIOF 1 Reset GPIOF Bit 21 20 Reserved 0x000 resd Kept at its default value Bit 19 GPIOCRST 0x0 rw GPIOC reset This bit is set or cleared by software 0 Does not reset GPIOC 1 Reset GPIOC Bit 18 GPIOBRST 0x0 rw GPIOB reset This bit is set or cleared by software 0 Does not reset GPIOB 1 Reset GPIOB Bit 17 GPIOARST 0x0 rw GPIOA reset This bit is set or cl...

Page 58: ...n 0xxx Clock output 1000 Clock output divided by 2 1001 Clock output divided by 4 1010 Clock output divided by 8 1011 Clock output divided by 16 1100 Clock output divided by 64 1101 Clock output divided by 128 1110 Clock output divided by 256 1111 Clock output divided by 512 Bit 27 26 Reserved 0x0 resd Kept its default value Bit 25 HICKDIV 0x0 rw HICK 6 divider selection This bit is used to select...

Page 59: ...tep by step system clock switch enable When the system clock source is switched from others to the PLL or when the AHB prescaler is changed from large to small system frequency is from small to large it is recommended to enable the auto step by step system clock switch if the operational target is larger than 108 MHz Once it is enabled the AHB bus is halted by hardware till the completion of the s...

Page 60: ...on block 4KB Boot memory 0x1FFF E400 0x1FFF F3FF 512B user system data 0x1FFF F800 0x1FFF F9FF Main Flash memory contains block 1 only 32 KB including 32 sectors 1K per sector Table 5 2 Flash memory architecture 32 K Block Name Address range Main memory Block 1 32 KB Sector 0 0x0800 0000 0x0800 03FF Sector 1 0x0800 0400 0x0800 07FF Sector 2 0x0800 0800 0x0800 0BFF Sector 31 0x0800 7C00 0x0800 7FFF...

Page 61: ...BOOT1 This bit along with BOOT0 defines boot mode When BOOT0 1 0 Boot from SRAM 1 Boot from boot memory Bit 3 Reserved Bit 2 nSTDBY_RST 0 Reset occurred when entering Standby mode 1 No reset occurred when entering Standby mode Bit 1 nDEPSLP_RST 0 Reset occurred when entering Deepsleep mode 1 No reset occurred when entering Deepsleep mode Bit 0 nWDT_ATO_EN 0 Watchdog is enabled 1 Watchdog is disabl...

Page 62: ...nd erase operation can be performed only when the Flash memory is unlocked Unlock procedure Flash memory block can be unlocked by writing KEY1 0x45670123 and KEY2 0xCDEF89AB to the FLASH_UNLOCK register Note Writing an incorrect key sequence leads to a bus error and locks up the Flash memory until the next reset Lock procedure Flash memory block can be locked again by setting the OPLK bit in the F...

Page 63: ...cedures below Check that no Flash memory operation is ongoing by checking the OBF bit in the FLASH_STS register Set the BANKERS and ERSTR bits in the FLASH_CTRL register to enable mass erase Wait until the OBF bit becomes 0 in the FLASH_STS register Read the EPPERR bit and ODF bit in the FLASH_STS register to verify Note 1 When the boot memory is configured as the Flash memory extension area perfo...

Page 64: ...LASH_STS register Set the FPRGM bit in the FLASH_CTRL register so that the Flash memory programming instructions can be received Write the data word half word byte to be programmed to the designated address Wait until the OBF bit in the FLASH_STS register becomes 0 read the EPPERR PRGMERR and ODF bits to verify Note 1 When the address to be written is not erased in advance the programming operatio...

Page 65: ... OBF bit in FLASH_STS OBF 0 Yes Read EPPERR bit PRGMERR bit and ODF bit in FLASH_STS End 5 2 4 Read operation Flash memory can be accessed through AHB bus of the CPU 5 3 Main Flash memory extension area Boot memory can also be programmed as the extension area of the main Flash memory to store user application code When used as main Flash memory extension area it behaves like the main Flash memory ...

Page 66: ...se Note Writing an incorrect key sequence leads to bus error and locks up the Flash memory until the next reset Lock procedure User system data area is locked again by clearing the USDULKS bit in the FLASH_CTRL register by software 5 4 2 Erase operation Erase operation must be done before programming User system data area can be erased independently To perform erase following the procedures below ...

Page 67: ... 2022 11 11 Page 67 Rev 2 02 Figure 5 4 System data area erase process Start No Check the OBF bit in FLASH_STS OBF 0 Yes Set USDERS 1 and ERSTR 1 in FLASH_CTRL OBF 0 Check the OBF bit in FLASH_STS Read ODF bit in FLASH_STS No Yes End ...

Page 68: ... can be received Write the data half word word to be programmed to the designated address Wait until the OBF bit in the FLASH_STS register becomes 0 read the PRGMERR and ODF bit to verify Note Read operation to the Flash memory during programming halts CPU until the completion of programming The internal HICK must be enabled prior to programming operation Figure 5 5 System data area programming pr...

Page 69: ...he FAP byte is equal to 0xCC the high level Flash memory access protection is enabled after a system reset Once enabled it is not permissible for users to re erase and write the system data area This protection can be unlocked only with hardware by setting the FAP_HL_DIS bit Note 1 The main memory extension area can also be protected 2 If the access protection bit is set in debug mode then the deb...

Page 70: ...ntinually reading large amount of constants But there are some restrictions in system clock frequency Please refer to the AT32F421 data sheet for more details 5 7 Special functions 5 7 1 Security library settings Security library is a defined area protected by a password in the main memory This area is only executable but cannot be read Except for I Code and D code buses written or deleted unless ...

Page 71: ...gs Note The main Flash memory and Flash extension area are not intended to be configured as security library at the same time Security library must be enabled before the Flash access protection is activated To unlock security library follow the steps below Write the previously set security library password to the SLIB_PWD_CLR register Wait until the OBF bit becomes 0 Perform a system reset and the...

Page 72: ...ed with the start address of the sector CRC verify must not cross the main Flash memory and its extension area boundary 5 8 Flash memory registers These peripheral registers must be accessed by words 32 bits Table 5 6 Flash memory interface Register map and reset value Register Offset Reset value FLASH_PSR 0x00 0x0000 0030 FLASH_UNLOCK 0x04 0xXXXX XXXX FLASH_USD_UNLOCK 0x08 0xXXXX XXXX FLASH_STS 0...

Page 73: ...er is enabled Bit 4 PFT_EN 1 rw Prefetch enable 0 Prefetch is disabled 1 Prefetch is enabled Bit 3 HFCYC_EN 0x0 rw Half cycle accelerated access enable 0 Disabled 1 Enabled Note There are some limitations in system clock frequency for this feature refer to the AT32F421 data sheet for details Bit 2 0 WTCYC 0x0 rw Wait cycle The wait states for Flash access depend on the size of the system clock and...

Page 74: ...0 rw1c Erase program protection error This bit is set by hardware when programming the erase program protected Flash memory address It is cleared by writing 1 Bit 3 Reserved 0 resd Kept at its default value Bit 2 PRGMERR 0 rw1c Programming error When the Flash programming address is in non erase state this bit is set by hardware It is cleared by writing 1 Bit 1 Reserved 0 resd Kept at its default ...

Page 75: ...s bit enables EPPERR or PROGERR interrupt 0 Interrupt is disabled 1 Interrupt is enabled Bit 9 USDULKS 0 rw User system data unlock success This bit is set by hardware when the user system data is unlocked successfully indicating that erase program operation to the user system data is allowed This bit is cleared by writing 0 which will re lock the user system data area Bit 7 OPLK 1 rw Operation lo...

Page 76: ...n and FAP 0xCC Bit 25 18 USER_D1 0xFF ro User data 1 Bit 17 10 USER_D0 0xFF ro User data 0 Bit 9 2 SSB 0xFF ro System setting byte Includes the system setting bytes in the loaded user system data area Bit 9 7 Unused Bit 6 nBOOT1 Bit 5 Unused Bit 4 nSTDBY_RST Bit 3 nDEPSLP_RST Bit 2 nWDT_ATO_EN Bit 1 FAP 0 ro Flash access protection Access to Flash memory is not allowed when this bit is set Bit 0 U...

Page 77: ...value Bit 0 BTM_AP_ENF 0 ro Boot memory stores application code enabled flag When this bit is set it indicates that the boot memory can be used as main Flash extension area to store user application code otherwise it is only used for storing system boot code 5 8 10 Flash security library status register1 SLIB_STS1 For Flash memory security library only Bit Register Reset value Type Description Bit...

Page 78: ... Register Reset value Type Description Bit 31 3 Reserved 0x0000 000 resd Kept at its default value Bit 2 SLIB_ULKF 0 ro Security library unlock flag When this bit is set it indicates that sLib related setting registers can be configured Bit 1 SLIB_PWD_OK 0 ro Security library password ok This bit is set by hardware when the password is correct Bit 0 SLIB_PWD_ERR 0 ro Security library password erro...

Page 79: ...curity library password setting only Bit Register Reset value Type Description Bit 31 0 SLIB_PSET_VAL 0x0000 0000 ro sLib password setting value Note This register can be written only after sLib is unlocked It is used to set a password of sLib Writing 0xFFFF_FFFF or 0x0000_0000 has no effect Note All these bits are write only and return 0 when being read 5 8 17 Security library address setting reg...

Page 80: ...rary start sector setting These bits are used to set the security library start sector 00000000000 Sector 0 00000000001 Sector 1 00000000010 Sector 2 00000001111 Sector 15 the last sector of 16KB main Flash memory 00000011111 Sector 31 the last sector of 32KB main Flash memory 00000111111 Sector 63 the last sector of 64KB main Flash memory Note All these bits are write only and return 0 when being...

Page 81: ...curity library code Note All these bits are write only and return no response when being read 5 8 19 Boot memory mode setting register BTM_MODE_SET For boot memory only Bit Register Reset value Type Description Bit 31 8 Reserved 0x000000 resd Kept at its default value Bit 7 0 BTM_MODE_SET 0x00 wo Boot memory mode setting 0XFF Boot memory serves as a system area that stores system boot code Others ...

Page 82: ...e Each pin can be configured as external interrupt input Each pin can be locked 6 2 Functional overview 6 2 1 GPIO structure Each of the GPIO pins can be configured by software as four input modes floating pull up pull down and analog input and four output modes open drain push pull alternate function push pull open drain output Each I O port bit can be programmed freely However I O port registers...

Page 83: ...de large sourcing sinking strength 010 Output mode normal sourcing sinking strength 011 Output mode normal sourcing sinking strength 1xx Output mode Maximum sourcing sinking strength Any value Open drain without pull up pull down 01 1 000 Output mode normal sourcing sinking strength 001 Output mode large sourcing sinking strength 010 Output mode normal sourcing sinking strength 011 Output mode nor...

Page 84: ... and pull down the same as those of general purpose input functions To enable multiplexed function output the port must be configured as multiplexed function output mode and push pull or open drain by setting GPIOx_CFGR or GPIOx_OMODE register In this case the pin is disconnected from GPIO controller and controlled by IOMUX controller instead To achieve bidirectional multiplexed function the port ...

Page 85: ...X PA3 TMR15_CH2 USART2_ RX I2S2_MC LK PA4 SPI1_CS I2S 1_WS USART2_ CK TMR14_ CH1 PA5 SPI1_SCK I2 S1_CK PA6 SPI1_MISO I 2S1_MCLK TMR3_CH 1 TMR1_BKI N I2S2_MC LK TMR16_ CH1 EVENTO UT COMP_O UT PA7 SPI1_MOSI I 2S1_SD TMR3_CH 2 TMR1_CH 1N TMR14_ CH1 TMR17_ CH1 EVENTO UT PA8 CLKOUT USART1_ CK TMR1_CH 1 EVENTO UT USART2 _TX I2C2_SCL PA9 TMR15_BKI N USART1_T X TMR1_CH 2 I2C1_SC L CLKOUT I2C2_SM BA PA10 T...

Page 86: ...MR16_B KIN I2C1_SM BA SPI2_MOSI I 2S2_SD PB6 USART1_TX I2C1_SC L TMR16_C H1N I2S1_MCLK PB7 USART1_RX I2C1_SD A TMR17_C H1N PB8 I2C1_SC L TMR16_C H1 PB9 IR_OUT I2C1_SD A TMR17_C H1 EVENTO UT I2S1_M CLK SPI2_CS I2 S2_WS PB10 I2C2_SC L SPI2_SCK I 2S2_CK PB11 EVENTOUT I2C2_SD A PB12 SPI2_CS I2S 2_WS EVENTO UT TMR1_BKI N TMR15 _BKIN I2C2_SMBA PB13 SPI2_SCK I2 S2_CK TMR1_CH 1N I2C2_S CL PB14 SPI2_MISO I...

Page 87: ... bit Description PA0 PWC_CTRLSTS 8 1 Once enabled PA0 pin acts as WKUP1 function of PWC PB5 PWC_CTRLSTS 13 1 Once enabled PB5 pin acts as WKUP6 function of PWC PB15 PWC_CTRLSTS 14 1 Once enabled PB15 pin acts as WKUP7 function of PWC PC13 PWC_CTRLSTS 9 1 Once enabled PA0 pin acts as WKUP2 function of PWC PC13 ERTC_CTRL 23 21 3 b000 ERTC_CTRL 11 0 ERTC_TAMP 0 0 Once enabled PC13 pin acts as RTC cha...

Page 88: ...ype Description Bit 31 16 Reserved 0x0000 resd Always 0 Bit 15 0 OM 0x0000 rw GPIOx output mode configuration y 0 15 When GPIOx is used as output there are two output modes for selection 0 Push pull reset state 1 Open drain 6 3 3 GPIO drive capability register GPIOx_ODRVR x A H Address offset 0x08 Reset values 0x0C00 0000 for port A 0x00000000 for other ports Bit Register Reset value Type Descript...

Page 89: ...s unchanged which acts as ODT register bit operations 0 No action to the corresponding ODT bits 1 Clear the corresponding ODT bits Bit 15 0 IOSB 0x0000 wo GPIOx set bit The corresponding ODT register bit is set by writing 1 to these bits Otherwise the corresponding ODT register bit remains unchanged which acts as ODT register bit operations 0 No action to the corresponding ODT bits 1 Set the corre...

Page 90: ...ultiplexed function IOs 0000 MUX0 0001 MUX1 0010 MUX2 0011 MUX3 0100 MUX4 0101 MUX5 0110 MUX6 0111 MUX7 1xxx Reserved 6 3 11 GPIO bit clear register GPIOx_CLR x A H Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 0 IOCB 0x0000 wo GPIOx clear bit The corresponding ODT register bit is cleared by writing 1 to these bits Otherwise the correspon...

Page 91: ...and TMR17_OVERFLOW are mapped on DMA channel 1 0x1 Remap 1 DMA request for TMR17_CH1 and TMR17_OVERFLOW is mapped on DMA channel 2 Bit 11 TMR16_DMA_RMP 0x0 rw TMR16 DMA request remap bit This bit is set and cleared by software 0x0 No remap DMA requests for TMR16_CH1 and TMR16_OVERFLOW are remapped on DMA channel 3 0x1 Remap 1 DMA requests for TMR16_CH1 and TMR16_OVERFLOW are remapped on DMA channe...

Page 92: ... after reset X0 Boot from main memory 01 Boot from bootloader memory 11 Boot from internal SRAM 7 2 2 SCFG external interrupt configuration register1 SCFG_ EXINTC1 Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 12 EXINT3 0x0000 rw EXINT3 input source configuration These bits can be read written by software They are used to select the input...

Page 93: ...or the EXINT5 external interrupt 0000 PA 5 0001 PB 5 Bit 3 0 EXINT4 0x0000 rw EXINT4 input source configuration These bits can be read written by software They are used to select the input source for the EXINT4 external interrupt 0000 PA 4 0001 PB 4 7 2 4 SCFG external interrupt configuration register3 SCFG_ EXINTC3 Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at i...

Page 94: ...read written by software They are used to select the input source for the EXINT15 external interrupt 0000 PA 15 0001 PB 15 Bit 11 8 EXINT14 0x0000 rw EXINT14 input source configuration These bits can be read written by software They are used to select the input source for the EXINT14 external interrupt 0000 PA pin14 0001 GPIOB pin14 Bit 7 4 EXINT13 0x0000 rw EXINT13 input source configuration Thes...

Page 95: ... cleared independently Independent status bit on each interrupt Each interrupt can be cleared independently 8 2 Function overview and configuration procedure With up to 22 interrupt lines EXINT_LINE 21 0 Line 18 and Line 20 are reserved EXINT can detect not only GPIO external interrupt sources but also internal sources such as PVM output ERTC alarm and ERTC tamper and time stamp events The GPIO in...

Page 96: ...POLCFG1 0x08 0x0000 0000 EXINT_ POLCFG2 0x0C 0x0000 0000 EXINT_ SWTRG 0x10 0x0000 0000 EXINT_ INTSTS 0x14 0x0000 0000 8 3 1 Interrupt enable register EXINT_INTEN Bit Register Reset value Type Description Bit 31 22 Reserved 0x000 resd Forced to 0 by hardware Bit 21 0 INTENx 0x00000 rw Interrupt enable or disable on line x 0 Interrupt request is disabled 1 Interrupt request is enabled Note Line 18 a...

Page 97: ... on line x When the corresponding bit in EXINT_INTEN register is 1 if the software writes to this bit the hardware sets the corresponding bit in the EXINT_INTSTS automatically to generate an interrupt When the corresponding bit in the EXINT_EVTEN register is 1 if the software writes to this bit the hardware generates an event on the corresponding interrupt line automatically 0 Default value 1 Soft...

Page 98: ...lock diagram Note The number of DMA peripherals in Figure 9 1 may decrease depending on different models 9 3 Functional overview 9 3 1 DMA configuration 1 Set the peripheral address in the DMA_CxPADDR register The initial peripheral address for data transfer remains unchanged during transmission 2 Set the memory address in the DMA_CxMADDR register The initial memory address for data transfer remai...

Page 99: ...neously 9 3 2 Handshake mechanism In P2M and M2P mode the peripherals need to send a request signal to the DMA controller The DMA channel will send a peripheral transfer request single until the signal is acknowledged After the completion of a peripheral transfer the DMA controller sends an acknowledge signal to the peripheral The peripheral then releases its request as soon as it receives the ack...

Page 100: ... 3 PWIDTH byte MWIDTH half word B3 B2 B1 B0 Half word3 Half word2 Half word1 Half word0 4th 3rd 2nd 1st B3 B2 B1 B0 4th 3rd 2nd 1st HW3 HW2 HW1 HW0 AHB Read Sequence AHB Write Sequence Figure 9 4 PWIDTH half word MWIDTH word B7 B5 B6 B4 B3 B1 B2 B0 word3 word2 word1 word0 4th 3rd 2nd 1st HW3 HW2 HW1 HW0 4th 3rd 2nd 1st W3 W2 W1 W0 AHB Read Sequence AHB Write Sequence Figure 9 5 PWIDTH word MWIDTH ...

Page 101: ...abled on a channel at a time The peripheral DMA requests can be independently activated de activated by setting the control bits in the corresponding peripheral registers Table 9 3 DMA requests for each channel Periphe rals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 ADC ADC 1 ADC 2 SPI I2S SPI1 I2S1_RX SPI1 I2S1_TX SPI2 I2S2_RX SPI2 I2S2_TX USART1 USART1_TX 1 USART1_RX 1 USART1_TX 2 USART1_...

Page 102: ... 0x08 0x0000 0000 DMA_C1DTCNT 0x0C 0x0000 0000 DMA_C1PADDR 0x10 0x0000 0000 DMA_C1MADDR 0x14 0x0000 0000 DMA_C2CTRL 0x1C 0x0000 0000 DMA_C2DTCNT 0x20 0x0000 0000 DMA_C2PADDR 0x24 0x0000 0000 DMA_C2MADDR 0x28 0x0000 0000 DMA_C3CTRL 0x30 0x0000 0000 DMA_C3DTCNT 0x34 0x0000 0000 DMA_C3PADDR 0x38 0x0000 0000 DMA_C3MADDR 0x3C 0x0000 0000 DMA_C4CTRL 0x44 0x0000 0000 DMA_C4DTCNT 0x48 0x0000 0000 DMA_C4PA...

Page 103: ...r complete event occurred 1 Transfer complete event occurred Bit 12 GF4 0x0 ro Channel 4 global event flag 0 No transfer error half transfer or transfer complete event occurred 1 Transfer error half transfer or transfer complete event Bit 11 DTERRF3 0x0 ro Channel 3 data transfer error event flag 0 No transfer error occurred 1 Transfer error occurred Bit 10 HDTF3 0x0 ro Channel 3 half transfer eve...

Page 104: ...lear 0 No effect 1 Clear the HDTF5 flag in the DMA_STS register Bit 17 FDTFC5 0x0 rw1c Channel 5 transfer complete flag clear 0 No effect 1 Clear the FDTF5 flag in the DMA_STS register Bit 16 GFC5 0x0 rw1c Channel 5 global interrupt flag clear 0 No effect 1 Clear the DTERRF5 HDTF5 FDTF5 and GF5 in the DMA_STS register Bit 15 DTERRFC4 0x0 rw1c Channel 4 data transfer error flag clear 0 No effect 1 ...

Page 105: ... 0x0 rw1c Channel 1 half transfer flag clear 0 No effect 1 Clear the HDTF1 flag in the DMA_STS register Bit 1 FDTFC1 0x0 rw1c Channel 1 transfer complete flag clear 0 No effect 1 Clear the FDTF1 flag in the DMA_STS register Bit 0 GFC1 0x0 rw1c Channel 1 global interrupt flag clear 0 No effect 1 Clear the DTERRF1 HDTF1 FDTF1 and GF1 in the DMA_STS register 9 4 3 DMA channel x configuration register...

Page 106: ...can only be written when the CHEN bit in the corresponding channel is set 0 The value is decremented by 1 after each DMA transfer Note This register holds the number of data to transfer instead of transfer size The transfer size is calculated by data width 9 4 5 DMA channel x peripheral address register DMA_CxPADDR x 1 5 Access 0 wait state accessible by bytes half words or words Bit Register Rese...

Page 107: ...operation through CRC_DT register Set an initialization value with the CRC_IDT register The value is loaded into CRC_DT register after each CRC reset 10 2CRC registers CRC_DT register can be accessed by bytes 8 bits half words 16 bits or words 32 bits Other registers have to be accessed by words 32 bits Table 10 1 CRC register map and reset value Register Offset Reset value CRC_DT 0x00 0xFFFF FFFF...

Page 108: ...is used to control how to reverse input data 00 No effect 01 Byte reverse 10 Half word reverse 11 Word reverse Bit 4 1 Reserved 0x0 resd Kept at its default value Bit 0 RST 0x0 rw Reset CRC calculation unit Set by software Cleared by hardware To reset CRC calculation unit the data register is set to 0xFFFF FFFF 0 No effect 1 Reset 10 2 4 Initialization register CRC_IDT Bit Register Reset value Typ...

Page 109: ...upport DMA transfer Support SMBus2 protocol PEC generation and verification SMBus reminder capability ARP address resolution protocol Timeout detection PMBus 11 3I2C functional overview I2C bus consists of a data line SDA and clock line SCL It can achieve a maximum of 100 kHz speed in standard mode whereas up to 400kHz in fast mode A frame of data transfer begins with a Start condition and ends wi...

Page 110: ... and slave mode Switching from master mode to slave mode vice versa is supported as well By default the interface operates in slave mode When GENSTART 1 is set Start condition is activated the I2 C bus interface switches from slave mode to master mode and returns to slave mode automatically at the end of data transfer Stop condition is triggered Master transmitter Master receiver Slave transmitter...

Page 111: ...e cannot process data in a timely manner on certain conditions it will pull down SCL line to low level to stop communication in order to prevent data loss Transmitter mode Clock stretching enable If no data is written to the I2C_DT register before the next byte transmission the first SCL rising edge of the next data the I2 C interface will pull down SCL bus and wait until the data is written to th...

Page 112: ...ernal shift register are now empty The TDBE bit is set 1 by hardware 3 EV2 When the data is written to the DT register it is directly moved to the shift register and the SCL bus is released The TDBE bit is still set 1 at this time 4 EV3 The DT register remains empty but the shift register is not Writing to the DT register clears the TDBE bit 5 EV4 After receiving the ACKFAIL event from the master ...

Page 113: ...Reading STS1 and then STS2 by software clears the ADDR7F bit At this point the SCL bus is released and enters receive stage 3 The internal shift register receives the bus data and stores them to DT register 4 EV2 After receiving the bytes the RDBF bit is set to1 Reading the I2C_DT register clears the RDBF bit 5 EV3 After receiving the Stop condition from the master STOPF 1 is activated Reading STS...

Page 114: ...dress head 0b11110xx0 where xx refers to address 9 8 and then address 7 0 followed by the address head 0b11110xx1 where xx refers to address 9 8 the master enters receiver mode Master transmitter Figure 11 5 Transfer sequence of master transmitter Address S 0 A Data1 A SCL Stretch Data2 A DataN A P Master to Slave Slave to Master S Start A Acknowledge P Stop Example I2C Master transfer N bytes to ...

Page 115: ...ars the ADDRHF bit 4 EV2 Address is matched successfully ADDR7F 1 Reading STS1 and then STS2 clears the ADDR7F bit In this case the master enters transmit stage and both DT register and internal shift register are empty The TDBE bit is set 1 by hardware 5 EV3 When the data is written to the DT register it is directly moved to the shift register and the SCL bus is released The TDBE bit is still set...

Page 116: ..._DT register clears the RDBF 5 EV4 Once the second to last byte is received the ACKEN bit must be cleared and the GENSTOP must be set by software 6 EV3 The RDBF bit is set 1 after receiving a byte Reading the I2C_DT register clears the RDBF 7 End of communication 10 bit address mode 1 Generate Start condition GENSTART 1 2 EV1 Start condition is ready STARTF 1 Read STS1 and write the address to DT ...

Page 117: ... Read STS1 and write the address to DT register 3 EV2 Address is matched successfully ADDR7F 1 Reading STS1 and then STS2 clears the ADDR7F bit and the master enters receive stage 4 EV3 The RDBF bit is set 1 after receiving the byte Reading the I2C_DT register clears the RDBF 5 EV4 TDC 1 the contents in the I2C_DT is N 2 and that of the shift register is N 1 The ACKEN is set 0 by software and the ...

Page 118: ...ddress A EV4 EV5 10 bit address Address Head RS SCL Stretch A Data1 NA SCL Stretch P EV2 EV3 7 bit address R W 0 R W 1 R W SCL Stretch EV1 SCL Stretch EV1 SCL Stretch EV1 7 bit address mode 1 Set MACKCTRL 1 in the I2C_CTRL1 register 2 Generate Start condition GENSTART 1 3 EV1 Start condition is ready STARTF 1 Read STS1 and write the address to DT register 4 EV2 Address is matched successfully ADDR...

Page 119: ...10 bit address Address Head RS SCL Stretch A Data1 NA SCL Stretch P EV2 EV3 7 bit address R W 0 R W 1 R W SCL Stretch EV1 SCL Stretch EV1 SCL Stretch EV1 7 bit address mode 1 Generate a Start condition GENSTART 1 2 EV1 Start condition is ready STARTF 1 Read STS1 and write the address to DT register 3 EV2 Address is matched successfully ADDR7F 1 Clear the ACKEN bit reading STS1 and then STS2 clears...

Page 120: ... 9 Master transmitter Once the TDC flag is set the STOP condition is generated indicating that transfer is complete Slave transmitter Once the ACKFAIL flag is set clear the ACKFAIL flag transfer is complete Reception using DMA 1 Set the peripheral address DMA_CxPADDR I2C_DT address 2 Set the memory address DMA_CxMADDR memory address 3 The transmission directions set from peripheral to memory DTD 0...

Page 121: ...cation of these protocols SMBus address resolution protocol ARP SMBus address conflicts can be resolved by dynamically assigning a new unique address to each device Refer to SMBus 2 0 protocol for more information about ARP Setting the ARPEN bit can enable the I2C interface to recognize the default device address 0b1100001x However unique device identifier UDID and the detailed protocol implementa...

Page 122: ...DMA mode The PEC is sent automatically after the completion of the last byte transfer For example if the number of data to be transferred is 8 then DMA_TCNTx 8 must be set PEC reception Common mode The PECTRA bit is set after the last RDBF event The PECTRA must be set before the ACK pulse of the current byte is received DMA mode The last byte is automatically checked as PECVAL during reception For...

Page 123: ...2 C peripheral is at reset state Note This bit can be used only when the BUSYF bit is 1 and no Stop condition is detected on the bus Bit 14 Reserved 0x0 resd Kept at its default value Bit 13 SMBALERT 0x0 rw SMBus alert pin set This bit is set or cleared by software It is cleared by hardware when I2CEN 0 0 SMBus alert pin high 1 SMBus alert pin low Bit 12 PECTEN 0x0 rw Request PEC transfer enable T...

Page 124: ...solution protocol enable 0 Disabled 1 Enabled SMBus host response to host address 0001000x SMBus slave response to default device address 0001100x Bit 3 SMBMODE 0x0 rw SMBus device mode 0 SMBus slave 1 SMBus host Bit 2 Reserved 0x0 resd Forced to be 0 by hardware Bit 1 PERMODE 0x0 rw I2 C peripheral mode 0 I2 C mode 1 SMBus mode Bit 0 I2CEN 0x0 rw I2 C peripheral enable 0 Disabled 1 Enabled All bi...

Page 125: ...VER 1 PECERR 1 TMOUT 1 ALERTF 1 Bit 7 0 CLKFREQ 0x00 rw I2 C input clock frequency Correct input clock frequency must be set to generate correct timings The range allowed is between 2 MHz and 120 MHz 2 2MHz 3 3MHz 120 120MHz 11 5 3 Own address register1 I2C_OADDR1 Bit Register Reset value Type Description Bit 15 ADDR1MODE 0x0 rw Address mode 0 7 bit address 1 10 bit address Bit 14 10 Reserved 0x00...

Page 126: ...t cannot be read 11 5 6 Status register1 I2C_STS1 Bit Register Reset value Type Description Bit 15 ALERTF 0x0 rw0c SMBus alert flag In SMBus host mode 0 No SMBus alert 1 SMBus alert event is received In SMBus slave mode It indicates the receiving status of the default device address 0001100x 0 Default device address is not received 1 Default device address is received This bit is cleared by softwa...

Page 127: ...d or by writing data when the TDC is set since the data register is still empty at this time Bit 6 RDBF 0x0 ro Receive data buffer full flag 0 Data register is empty 1 Data register is full data received This flag is cleared when the DT register is read The RDBF bit is not set at ARLOST event Bit 5 Reserved 0x0 resd Kept at its default value Bit 4 STOPF 0x0 ro Stop condition generation complete fl...

Page 128: ...when PECEN is reset Bit 7 ADDR2F 0x0 ro Received address 2 flag 0 Received address matches the contents of OADDR1 1 Received address matches the contents of OADDR2 Cleared when a Stop Start condition is received or by hardware when I2CEN 0 Bit 6 HOSTADDRF 0x0 ro SMBus host address reception flag 0 SMBus host address is not received 1 SMBus host address is received Cleared when a Stop Start conditi...

Page 129: ... standard mode High level SPEED x TI2C_CLK Low level SPEED x TI2C_CLK In fast mode DUTYMODE 0 High level SPEED x TI2C_CLK x 1 Low level SPEED x TI2C_CLK x 2 DUTYMODE 1 High level SPEED x TI2C_CLK x 9 Low level SPEED x TI2C_CLK x 16 The minimum value allowed in standard mode is 4 In fast mode the minimum value allowed is 1 The CLKCTRL register can be configured only when the I2C is disabled I2CEN 0...

Page 130: ... protocol defined in ISO7816 3 standard and CTS RTS Clear To Send Request To Send hardware flow operation The USART also supports silent mode that allows multi processor communication and can be woken up by a programmable idle frames or ID matching so as to build up a USART network Meanwhile high speed communication is possible by using DMA Figure 12 1 USART block diagram USART interrupt control l...

Page 131: ...able frame format Programmable data word length 8 bits or 9 bits Programmable stop bits support 1 or 2 stop bits Programmable parity control transmitter with parity bit transmission capability and receiver with received data parity check capability Programmable DMA multi buffer communication Programmable separate enable bits for transmitter and receiver Programmable output CLK phase polarity and f...

Page 132: ...on USART mode selector allows USART to work in different operation modes through software configuration so as to enable data exchanges between USART and peripherals with different communication protocols USART supports NRZ standard format Mark Space by default It also supports LIN Local Interconnection Network IrDA SIR Serial Infrared Asynchronous Smartcard protocol in ISO7816 3 standard RS 232 CT...

Page 133: ... asserted high after the guard time counter reaches the value programmed in the SCGT 7 0 bit The Smartcard is a single wire half duplex communication protocol The SCNACKEN bit is used to select whether to send NACK when a parity error occurs This is to indicate to the Smarcard that the data has not been correctly received Figure 12 3 Smartcard frame format Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6...

Page 134: ...icating request to stop data transfer at the end of current frame CTS the USART transmitter checks the CTS input before sending next frame The next data is sent if CTS is active when low if CTS becomes inactive when high during transmission it stops sending at the end of current transfer Figure 12 5 Hardware flow control RX pin RTS frame0 frame1 RTS follow control CTS TX pin frame0 frame1 CTS foll...

Page 135: ...are enabled Select CK pin high or low in idle state by setting the CLKPOL bit 1 or 0 Whether to sample data on the second or the first edge of the clock depends on the CLKPHA bit 1 or 0 The LBCP bit 1 or 0 is used to select whether to output clock on the last data bit And the ISDIV 4 0 is used to select the required clock output frequency Figure 12 7 8 bit format USART synchronous mode Bit 0 Bit 1...

Page 136: ...Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Start bit Stop bit 9 bit word length DBN 1 Next Start bit Clock Start bit Next Data frame PEN 1 Parity bit Data frame Idle frame Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Start bit Stop bit 8 bit word length DBN 0 Next Start bit Clock Start bit Next Data frame PEN 1 Parity bit Data frame Idle frame The STOPBN bit is used to program one bit STOP...

Page 137: ...el Select a DMA channel from DMA channel map table described in DMA chapter 2 Configure the destination of DMA transfer Configure the USART_DT register address as the destination address bit of DMA transfer in the DMA control register Data will be sent to this address after transmit request is received by DMA 3 Configure the source of DMA transfer Configure the memory address as the source of DMA ...

Page 138: ... data bit width should not be less than 16 PCLK periods that is the DIV value must be greater than 16 12 6 2 Configuration User can program the desired baud rate by setting different system clocks and writing different values into the USART_BAUDR register The calculation format is as follows TX RX 𝑏𝑎𝑢𝑑 𝑟𝑎𝑡𝑒 𝑓𝐶𝐾 DIV Where 𝑓𝐶𝐾 refers to the system clock of USART i e PCLK1 PCLK2 Note 1 Tthe USART_BAU...

Page 139: ... Refer to 12 2 Full duplex half duplex selector 3 Mode configuration Refer to 12 3 Mode selector 4 Frame format configuration Refer to 12 4 USART frame format and configuration 5 Interrupt configuration Refer to 12 10 Interrupt requests 6 DMA transfer configuration To use DMA mode for data transfer the DMATEN bit bit 7 in the USART_CTRL3register should be set and the DMA register should be configu...

Page 140: ... 5 Interrupt configuration Refer to 12 10 Interrupt requests 6 Reception using DMA To use DMA mode for data reception the DMAREN bit should be set and the DMA register should be configured accordingly 7 Baud rate configuration Refer to 12 6 Baud rate generation 8 Receiver enable REN bit is set Character reception The RDBF bit is set It indicates that the content of the shift register is transferre...

Page 141: ...ampling over start bit and noise detection Sampled value 3 5 7 Sampled value 8 9 10 NERR bit Start bit validity 000 000 0 Valid 001 010 100 001 010 100 1 Valid 001 010 100 000 1 Valid 000 001 010 100 1 Valid 111 110 101 011 Any value 1 Invalid Any value 111 110 101 011 1 Invalid Note If the sampling values on the 3rd 5th 7th 8th 9th and 10th bits do not match the above mentioned requirements the U...

Page 142: ...X USART_TX USART_RX USART_RX USART USART TRPSWAP 0 TRPSWAP 1 Note The SWAP USART_CTRL2 15 can be modified only when the USART is disabled UEN 0 12 10 Interrupt requests USART interrupt generator serves as a control center of USART interrupts It is used to monitor the interrupt source inside the USART in real time and to define the generation of interrupts by configuring the corresponding interrupt...

Page 143: ... is used as an I O for data transmission and reception CK Transmitter clock output The output CLK phase polarity and frequency are programmable CTS Transmitter input Send enable signal in hardware flow control mode RTS Receiver output Send request signal in hardware flow control mode 12 12 USART registers These peripheral registers must be accessed by words 32 bits Table 12 5 USART register map an...

Page 144: ... This bit is set by hardware when the data is transferred from the shift register to the USART_DT register It is cleared by software Option 1 read USART_DT register Option 2 write 0 to this bit 0 Data is not received 1 Data is received Bit 4 IDLEF 0x0 ro Idle flag This bit is set by hardware when an idle line is detected It is cleared by software Read USART_DT register followed by a USART_DT read ...

Page 145: ...USART divider 12 12 4Control register1 USART_CTRL1 Bit Register Reset value Type Description Bit 31 14 Reserved 0x00000 resd Forced 0 by hardware Bit 13 UEN 0x0 rw USART enable 0 USART is disabled 1 USART is enable Bit 12 DBN 0x0 rw Data bit num This bit is used to program the number of data bits 0 8 data bits 1 9 data bits Bit 11 WUM 0x0 rw Wakeup mode This bit determines the way to wake up silen...

Page 146: ...s cleared by hardware after wake up When address mismatches this bit is set by hardware to enter mute mode again 0 Receiver is in active mode 1 Receiver is in mute mode Bit 0 SBF 0x0 rw Send brake frame This bit is used to send a brake frame It can be set or cleared by software Generally speaking it is set by software and cleared by hardware at the end of brake frame transmission 0 No brake frame ...

Page 147: ...ep at its default value Bit 6 BFIEN 0x0 rw Brake frame interrupt enable 0 Disabled 1 Enabled Bit 5 BFBN 0x0 rw Brake frame bit num This bit is used to select 11 bit or 10 bit brake frame 0 10 bit brake frame 1 11 bit brake frame Bit 4 Reserved 0x0 resd Keep at its default value Bit 3 0 ID 0x0 rw USART identification Configurable USART ID Note These three bits CLKPOL CLKPHA and LBCP cannot be chang...

Page 148: ...ror overflow error or noise error occurs 0 Error interrupt is disabled 1 Error interrupt is enabled 12 12 7Guard time and divider register USART_GDIV Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Forced 0 by hardware Bit 15 8 SCGT 0x00 rw Smartcard guard time value This field specifies the guard time value The transmission complete flag is set after this guard time in sm...

Page 149: ...roller SPI_STS BF ROE RR MME RR CCE RR TUER R ACS TDBE RDBF Communication controller CS controller SWCSEN SWCSIL SLBEN SLBTD ORA MDIV 3 0 CLKPOL CLKPHA MSTEN Transmitter logic Transmission CRC unit CCEN NTC LTF SPIEN FBN MOSI MISO SCK CS Full Duplex Harf duplex selector Receiver logic Receipt CRC unit Receive transmit date shift logic Interrupt generator ERRIE TDBEIE RDBFIE LTF SPIEN FBN Main feat...

Page 150: ...l duplex mode when the SLBEN bit and the ORA bit are both 0 In this case the SPI supports data transmission and reception simultaneously IO connection is as follows Figure 13 2 SPI two wire unidirectional full duplex connection SPI master SCK MISO MOSI CS SPI slave SCK MISO MOSI CS In either master or slave mode it is necessary to wait until the RDBF bit and TDBE bit is set as well as BF 0 before ...

Page 151: ... IO pin mapped by MOSI is released The SLBTD bit is used by software to configure transfer direction When the SLBTD bit is set the SPI can be used only for data transmission when the SLBTD bit is 0 the SPI can be used only for data reception Figure 13 5 Single wire bidirectional half duplex mode SPI master SCK MISO MOSI CS SPI slave SCK MISO MOSI CS When the SPI is used for data transmission in si...

Page 152: ... is set the SPIEN and MSTEN bits cannot be set by software The MMERR bit is cleared by read or write access to the SPI_STS register followed by write operation to the SPI_CTRL1 register In slave mode with CS being as an input SWCSEN 1 the CS software control is enabled The SPI judges the CS signal with the SWCSIL bit instead of CS pin When SWCSIL 0 the slave is selected for data reception and tran...

Page 153: ...oftware receives the last data when the second to last data is received 13 2 6 DMA transfer The SPI supports write and read operations with DMA Refer to the following configuration procedure Special attention should be paid to when the CRC calculation and check is enabled the number of data transferred by DMA is configured as the number of the data to be transferred The number of data read with DM...

Page 154: ... the TDBE is set After the transmitter is configured and the SPI is enabled the SPI is ready for data transmission Before going forward it is necessary for the users to refer to full duplex half duplex chapter to get detailed configuration information go to the Chip select controller chapter for specific chip select mode check the SPI_SCK controller chapter for information on communication clock a...

Page 155: ... MSB LSB mode with the LTF bit and select 8 16 bit data with the FBN bit Enable SPI by setting the SPIEN Enable SPI by setting the SPIEN 13 2 9 Motorola mode This section describes the SPI communication timings which includes full duplex and half duplex master slave timings Full duplex communication master mode Configured as follows MSTEN 1 Master enable SLBEN 0 Full duplex mode CLKPOL 0 CLKPHA 0 ...

Page 156: ...r transmit MOSI 0xaa 0xcc 0xaa Figure 13 8 Slave full duplex communications SCK BF flag CS MOSI 1 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 TDBE flag Drive Transmit buffer empty and software can write data Half duplex communication slave receive Configured as follows MSTEN 0 Slave enable SLBEN 1 Single line bidirectional mode SLBTD 0 Receive mode CLKPOL 0 CLKPHA 0 SCK idle output low use the f...

Page 157: ...lf duplex communication master receive Configured as follows MSTEN 1 Master enable SLBEN 1 Single line bidirectional mode SLBTD 0 Receive enable CLKPOL 0 CLKPHA 0 SCK idle output low use the first edge for sampling FBN 0 8 bit frame Master receive 0xaa 0xcc 0xaa Figure 13 11 Master half duplex receive SCK BF flag CS MOSI 1 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 BF flag remains low RDBF flag...

Page 158: ...s to use PA13 14 as SPI2 it is necessary to insert a delay for code download prior to GPIO remap 13 2 12Precautions CRC value is obtained by software reading DT register at the end of CRC reception 13 3I2S functional description 13 3 1 I2 S introduction The I2 S can be configured by software as master reception transmission and slave reception transmission supporting four kinds of audio protocols ...

Page 159: ...of 256x Fs audio sampling frequency 13 3 2 Operation mode selector The SPI used as I2S selector offers multiple operation modes for selection namely slave device transmission slave device reception master device transmission and master device reception This is done by software configuration Slave device transmission Set the I2SMSEL bit and OPERSEL 1 0 00 the I2S will work in slave device transmiss...

Page 160: ...e configuration to select the desired audio protocol with the data bits and channel bits being controlled by the audio protocol selector Besides the user can also select the data bits and channel bits through software configuration Meanwhile the audio protocol selector manages the WS controller output or detect the WS signal that meets the protocol requirements Select audio protocol by setting the...

Page 161: ...nt from the channel bit Each channel requires one read write operation from to the SPI_DT register and the number of DMA transfer is 1 The 16 bits LSB are the significant bits while the first 16 bit data MSB are forced to 0 by hardware LSB aligned standard 24 bit data and 32 bit channel The data bit is different from the channel bit Each channel requires two read write operations from to the SPI_D...

Page 162: ... 0 16025 0 16 58 1 16025 0 16 120 No 11025 170 0 11029 0 04 85 0 11029 0 04 120 No 8000 234 1 7995 0 05 117 1 8012 0 16 120 Yes 96000 2 1 93750 2 34 2 1 937500 2 34 120 Yes 48000 5 0 46875 2 34 5 0 46875 2 34 120 Yes 44100 5 1 42613 3 37 5 1 42613 3 37 120 Yes 32000 7 1 31250 2 34 7 1 31250 2 34 120 Yes 22050 10 1 22321 1 23 10 1 22321 1 23 120 Yes 16000 14 1 16163 1 02 14 1 16163 1 02 120 Yes 110...

Page 163: ...annel map table described in DMA chapter Configure the destination of DMA transfer Configure the SPI_DT register address as the destination address bit of DMA transfer in the DMA control register Data will be sent to this address after transmit request is received by DMA Configure the source of DMA transfer Configure the memory address as the source of DMA transfer in the DMA control register Data...

Page 164: ...hannel ACS 0 or the right channel ACS 1 TUERR bit indicates whether an underrun occurs TUERR 1 means an underrun error occurs on the transmitter An interrupt is generated when the ERRIE is set Read write operation to the SPI_DT register is different under different audio protocols data bits and channel bits Refer to the audio protocol selector section for more information Pay more attention to the...

Page 165: ...6CK 16CK 13 3 8 Interrupts Figure 13 20 I2 S interrupts RDBF RDBFIE TDBE TDBEIE ROERR TUERR ERRIE I2S interrupt 13 3 9 IO pin control The I2 S needs three pins for transfer operation namely the SD WS and CK The MCLK pin is also required if need to provide main clock for peripherals The I2 S shares some pins with the SPI described as follows SD Serial data mapped on the MOSI pin for bidirectional d...

Page 166: ...only mode 1 Transmit only mode Bit 13 CCEN 0x0 rw RC calculation enable 0 Disabled 1 Enabled Bit 12 NTC 0x0 rw Transmit CRC next When this bit is set it indicates that the next data transferred is CRC value 0 Next transmitted data is the normal value 1 Next transmitted data is CRC value Bit 11 FBN 0x0 rw Frame bit num This bit is used to configure the number of data frame bit for transmission rece...

Page 167: ...t clock edge 1 Data capture starts from the second clock edge Note The SPI_CTRL1 register must be 0 in I2 S mode 13 4 2 SPI control register2 SPI_CTRL2 Bit Register Reset value Type Description Bit 15 9 Reserved 0x00 resd Forced to be 0 by hardware Bit 8 MDIV 0x0 rw Master clock frequency division Refer to the MDIV 2 0 of the SPI_CTRL1 register Bit 7 TDBEIE 0x0 rw Transmit data buffer empty interr...

Page 168: ...SPI_STS register 0 No underload error 1 Underload error occurs Note This bit is only used in I2 S mode Bit 2 ACS 0x0 ro Audio channel state This bit indicates the status of the current audio channel 0 Left channel 1 Right channel Note This bit is only used in I2 S mode Bit 1 TDBE 0x1 ro Transmit data buffer empty 0 Transmit data buffer is not empty 1 Transmit data buffer is not empty Bit 0 RDBF 0x...

Page 169: ...rmat is set to 8 bit data only the 8 bit LSB 7 0 are calculated based on CRC8 standard when 16 bit data bit is selected follow CRC16 standard Note This register is only used in SPI mode 13 4 8 SPI_I2S configuration register SPI_I2SCTRL Bit Register Reset value Type Description Bit 15 12 Reserved 0x0 resd Forced to be 0 by hardware Bit 11 I2SMSEL 0x0 rw I2 S mode select 0 SPI mode 1 I2 S mode Bit 1...

Page 170: ... 32 bit by hardware 0 16 bit wide 1 32 bit wide 13 4 9 SPI_I2S prescaler register SPI_I2SCLKP Bit Register Reset value Type Description Bit 15 12 Reserved 0x0 resd Forced to be 0 Bit 9 I2SMCLKOE 0x0 rw I2 S Master clock output enable 0 Disabled 1 Enabled Bit 8 I2SODD 0x0 rw Odd factor for I2 S division 0 Actual divider factor I2SDIV 2 1 Actual divider factor I2SDIV 2 1 Bit 11 10 Bit 7 0 I2SDIV 0x0...

Page 171: ...35 O 4 O O O General purpose timer TMR3 16 Up Down Up Down X 1 65535 O 4 O O X TMR14 16 Up X 1 65535 X 1 X X X TMR15 16 Up O 1 65535 O 2 O X O TMR16 TMR17 16 Up O 1 65535 O 1 X X O Basic timer TMR6 16 Up X 1 65535 O X X X X Timer type Timer Counter bit Count mode PWM output Single pulse output Comple mentary output Dead time Encoder interface connection Interfacing with hall sensors Linkage periph...

Page 172: ...ounting period The value in the TMRx_PR is immediately moved to the shadow register by default When the periodic buffer is enabled PRBEN 1 the value in the TMRx_PR register is transferred to the shadow register only at an overflow event The TMRx_DIV register is used to configure the counting frequency The counter counts once every count clock period DIV 15 0 1 Similar to the TMRx_PR register when ...

Page 173: ...w event with the OVFIF bit being set to 1 If the overflow event is disabled the register is no longer reloaded with the preload and re loaded value after counter overflow occurs otherwise the prescaler and re loaded value will be updated at an overflow event Figure 14 4 Overflow event when PRBEN 0 0 1 2 3 31 32 0 1 2 3 31 32 0 1 2 3 COUNTER 31 32 0 1 32 PR 15 0 OVFIF TMR_CLK 0 DIV 15 0 22 Clear Cl...

Page 174: ...t be accessed by word 32 bits In Table 14 2 all the TMR6 registers are mapped to a 16 bit addressable space Table 14 2 TMR6 register map and reset value Register Offset Reset value TMRx_CTRL1 0x00 0x0000 TMRx_CTRL2 0x04 0x0000 TMRx_IDEN 0x0C 0x0000 TMRx_ISTS 0x10 0x0000 TMRx_SWEVT 0x14 0x0000 TMRx_CVAL 0x24 0x0000 TMRx_DIV 0x28 0x0000 TMRx_PR 0x2C 0x0000 ...

Page 175: ...s generated by any of the following events Counter overflow Setting the OVFSWTR bit Overflow event generated from the slave controller 1 OEV event is disabled If the OVFSWTR bit is set or a hardware reset is generated from the slave controller the counter and the prescaler are reinitialized Note This bit is set and cleared by software Bit 0 TMREN 0x0 rw TMR enable 0 Disabled 1 Enabled 14 1 4 2TMR6...

Page 176: ...T Bit Register Reset value Type Description Bit 15 1 Reserved 0x0000 resd Kept at its default value Bit 0 OVFSWTR 0x0 rw0c Overflow event triggered by software An overflow event is trigged by software 0 No effect 1 Generate an overflow event by software write operation 14 1 4 6TMR6 counter value TMRx_CVAL Bit Register Reset value Type Description Bit 15 0 CVAL 0x0000 rw Counter value 14 1 4 7TMR6 ...

Page 177: ...2 TMRx_CH1 TMRX_EXT Polarity selection edge detector prescaler Reset mode Encoder interface TMRx_DIV CNT counter CH4 edge detector C4DT CH4 filter CH3 edge detector CH3 filter C4IFP4 C4IFP3 C4IRAW C3IFP4 C3IFP3 C3IRAW CH2 edge detector CH2 filter C2IFP2 C2IFP1 C2IRAW C1IFP2 CH1 edge detector CH1 filter C1IFP1 C1IRAW STCI STCI STCI STCI C4IN C3IN DIV C3IN C2IN DIV C2IN C1IN DIV C1IN C4C 0 C3DT C3C ...

Page 178: ...b111 external clock mode A is selected Set the STIS 2 0 bit to select TRGIN signal to drive the counter to start counting The external clock sources include C1INC STIS 3 b100 channel 1 rising edge and falling edge C1IFP1 STIS 3 b101 channel 1 signal with filtering and polarity selection C2IFP2 STIS 3 b110 channel 2 signal with filtering and polarity selection and EXT STIS 3 b111 external input sig...

Page 179: ...TCTRL register Set counter counting frequency by setting the DIV 15 0 bit in the TMRx_DIV register Set counter counting period by setting the PR 15 0 bit in the TMRx_PR register Enable counter by setting the TMREN bit in the TMRx_CTRL1 register Figure 14 10 Block diagram of external clock mode A TMRx_EXT ESF filter EXT C1INC C1IFP1 C2IPF2 TMRx_CH2 C2DF C2P C2CP filter edge dector TMRx_CH1 C1DF C1P...

Page 180: ...e modified at any time but it takes effect only when the next overflow event occurs The internal trigger input configuration process is as follows Set the TMRx_PR register to set counting period Set the TMRx_DIV register to set counting frequency Set the TWCMSEL 1 0 bit in the TMRx_CTRL1 register to set counting mode Set the STIS 2 0 bit range 3 b000 3 b011 in the TMRx_STCTRL register to select in...

Page 181: ...rflow event source By default counter overflow underflow setting OVFSWTR bit and the reset signal generated by the slave timer controller in reset mode trigger the generation of an overflow event When the OVFS bit is set only counter overflow underflow triggers an overflow event Setting the TMREN bit TMREN 1 enables the timer to start counting Base on synchronization logic however the actual enabl...

Page 182: ... counting mode In up down counting mode the counter counts up down alternatively When the counter counts from the value programmed in the TMRx_PR register down to 1 an underflow event is generated and then restarts counting from 0 When the counter counts from 0 to the value of the TMRx_PR register 1 an overflow event is generated and then restarts counting from the value of the TMRx_PR register Th...

Page 183: ...counting direction is dependent on the edge direction of C1IFP1 and the level of C2IFP2 Encoder mode B SMSEL 3 b010 the counter counts on C2IFP2 rising edge and falling edge and the counting direction is dependent on the edge direction of C2IFP2 and the level of C1IFP1 Encoder mode C SMSEL 3 b011 the counter counts on C1IFP1 and C2IFP2 rising edge and falling edge and the counting direction is dep...

Page 184: ...utputs the pre processed CxIRAW Set the C1INSEL bit to select the source of C1IRAW from TMRx_CH1 or the XOR ed TMRx_CH1 TMRx_CH2 and TMRx_CH3 and the sources of C2IRAW C3IRAW and C4IRAW are TMRx_CH2 TMRx_CH3 and TMRx_CH4 respectively CxIRAW inputs digital filter and outputs a filtered signal CxIF Set the sampling frequency and sampling times of digital filter by setting the CxDF bit CxIF inputs ed...

Page 185: ...er value and the CxRF is set to 1 To capture the rising edge of C1IN input following the procedure below Set C1C 01 in the TMR3_CM1 register to select the C1IN as channel 1 input Set the filter bandwidth of C1IN signal CxDF 3 0 Set the active edge on the C1IN channel by writing C1P 0 rising edge in the TMR3_CCTRL register Program the capture frequency division of C1IN signal C1DIV 1 0 Enable chann...

Page 186: ...ster The period and duty of channel 1 input signal can be calculated through C1DT and C2DT respectively Figure 14 24 PWM input mode configuration C1P 0 C1CP 0 edge detector C1IF C1IN C1IFP1 pos C2IFP1 STCI C1C 2 b01 C1IRAW filter C1DF C1EN Capture trigger C1INC IS3 IS2 IS1 CI2FP2 STIS 3 b101 Trigger mode Hang mode Reset mode SMSEL 3 b110 C2P 1 C2CP 0 edge detector C2IN C1IFP2 neg C2IFP2 STCI C2EN ...

Page 187: ...register to enable TMRx output Set the corresponding GPIO of TMR output channel as the multiplexed mode Set the TMREN bit in the TMRx_CTRL1 register to enable TMRx counter PWM mode B Set CxOCTRL 3 b111 to enable PWM mode B In upcounting when TMRx_C1DT TMRx_CVAL C1ORAW outputs low otherwise outputs high In downcounting when TMRx_C1DT TMRx_CVAL C1ORAW outputs high otherwise outputs low Forced output...

Page 188: ... The counter only counts only one cycle and the output signal sends only one pulse Figure 14 27 C1ORAW toggles when counter value matches the C1DT value 0 1 2 3 31 32 0 1 2 3 31 32 0 1 2 3 COUNTER 31 32 0 1 PR 15 0 C1ORAW TMR_CLK 0 DIV 15 0 32 011 C1OCTRL 2 0 3 C1DT 15 0 Figure 14 28 Upcounting mode and PWM mode A 0 1 2 3 31 32 0 1 2 3 31 32 0 1 2 3 COUNTER 31 32 0 1 PR 15 0 C1ORAW TMR_CLK 0 DIV 1...

Page 189: ...puts C1ORAW signal PTOS 3 b101 TRGOUT outputs C2ORAW signal PTOS 3 b110 TRGOUT outputs C3ORAW signal PTOS 3 b111 TRGOUT outputs C4ORAW signal CxORAW clear When the CxOSEN bit is set to 1 the CxORAW signal for a given channel is cleared by applying a high level to the EXT input The CxORAW signal remains unchanged until the next overflow event This function can only be used in output capture or PWM ...

Page 190: ... 32 0 PR 15 0 CI1F1 TMR_CLK 0 DIV 15 0 32 101 STIS 2 0 OVFIF TRGIF 100 SMSEL 2 0 Slave mode Suspend mode In this mode the counter is controlled by a selected trigger input The counter starts counting when the trigger input is high and stops as soon as the trigger input is low Figure 14 33 Example of suspend mode 0 1 2 3 4 5 6 7 8 9 COUNTER A B C D 10 PR 15 0 TMR_CLK 0 DIV 15 0 32 101 STIS 2 0 101 ...

Page 191: ... counting period TMRx_PR register Configure the slave timer trigger input signal TRGIN as master timer output STIS 2 0 in the TMRx_STCTRL register Configure the slave timer to use external clock mode A SMSEL 2 0 3 b111 in the TMRx_STCTRL register Set TMREN 1 in both master timer and slave timer to enable them Using master timer to start slave timer Configure master timer output signal TRGOUT as an...

Page 192: ... slave timer as trigger mode SMSEL 3 b110 in the TMR2_STCTRL register Figure 14 37 Starting master and slave timers synchronously by an external trigger COUNTER PR 15 0 TMREN TMR_CLK 0 DIV 15 0 32 22 PR 15 0 TRGIN 1 21 22 0 1 2 3 21 COUNTER 0 1 2 3 22 0 0 DIV 15 0 TMR_CLK Master TMR Slave TMR 1 31 32 0 1 2 3 31 0 1 2 3 32 0 TMR_EN 14 2 3 6 Debug mode When the microcontroller enters debug mode Cort...

Page 193: ...ately the output flag bit is set only when the counter counts down 10 Two way counting mode2 count up and down alternately the output flag bit is set only when the counter counts up 11 Two way counting mode3 count up and down alternately the output flag bit is set when the counter counts up down Bit 4 OWCDIR 0x0 rw One way count direction 0 Up 1 Down Bit 3 OCMEN 0x0 rw One cycle mode enable This b...

Page 194: ...gh or rising edge 1 Low or falling edge Bit 14 ECMBEN 0x0 rw External clock mode B enable This bit is used to enable external clock mode B 0 Disabled 1 Enabled Bit 13 12 ESDIV 0x0 rw External signal divide This field is used to select the frequency division of an external trigger 00 Normal 01 Divided by 2 10 Divided by 4 11 Divided by 8 Bit 11 8 ESF 0x0 rw External signal filter This field is used...

Page 195: ...he TRGIN input 111 External clock mode A Rising edge of the TRGIN input clocks the counter Note Please refer to count mode section for the details on encoder mode A B C 14 2 4 4 DMA interrupt enable register TMR3_IDEN Bit Register Reset value Type Description Bit 15 Reserved 0x0 resd Kept at its default value Bit 14 TDEN 0x0 rw Trigger DMA request enable 0 Disabled 1 Enabled Bit 13 Reserved 0x0 re...

Page 196: ...trigger event occurs 1 Trigger event is generated Trigger event an active edge is detected on TRGIN input or any edge in suspend mode Bit 5 Reserved 0x0 resd Kept at its default value Bit 4 C4IF 0x0 rw0c Channel 4 interrupt flag Please refer to C1IF description Bit 3 C3IF 0x0 rw0c Channel 3 interrupt flag Please refer to C1IF description Bit 2 C2IF 0x0 rw0c Channel 2 interrupt flag Please refer to...

Page 197: ...e mode Bit Register Reset value Type Description Bit 15 C2OSEN 0x0 rw Channel 2 output switch enable Bit 14 12 C2OCTRL 0x0 rw Channel 2 output control Bit 11 C2OBEN 0x0 rw Channel 2 output buffer enable Bit 10 C2OIEN 0x0 rw Channel 2 output enable immediately Bit 9 8 C2C 0x0 rw Channel 2 configuration This field is used to define the direction of the channel 2 input or output and the selection of ...

Page 198: ...ut or output and the selection of input pin when C1EN 0 00 Output 01 Input C1IN is mapped on C1IFP1 10 Input C1IN is mapped on C2IFP1 11 Input C1IN is mapped on STCI This mode works only when the internal trigger input is selected by STIS Input capture mode Bit Register Reset value Type Description Bit 15 12 C2DF 0x0 rw Channel 2 digital filter Bit 11 10 C2IDIV 0x0 rw Channel 2 input divider Bit 9...

Page 199: ... used to define the direction of the channel 1 input or output and the selection of input pin when C4EN 0 00 Output 01 Input C4IN is mapped on C4IFP4 10 Input C4IN is mapped on C3IFP4 11 Input C4IN is mapped on STCI This mode works only when the internal trigger input is selected by STIS Bit 7 C3OSEN 0x0 rw Channel 3 output switch enable Bit 6 4 C3OCTRL 0x0 rw Channel 3 output control Bit 3 C3OBEN...

Page 200: ...r to C1P description Bit 6 Reserved 0x0 resd Kept at its default value Bit 5 C2P 0x0 rw Channel 2 polarity Please refer to C1P description Bit 4 C2EN 0x0 rw Channel 2 enable Please refer to C1EN description Bit 3 C1CP 0x0 rw Channel 1 complementary polarity Please refer to C1P description Bit 2 Reserved 0x0 resd Kept at its default value Bit 1 C1P 0x0 rw Channel 1 polarity When the channel 1 is co...

Page 201: ...diately depends on the C1OBEN bit and the corresponding output is generated on C1OUT as configured 14 2 4 14 Channel 2 data register TMR3_C2DT Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 0 C2DT 0x0000 rw Channel 2 data register When the channel 2 is configured as input mode The C2DT is the CVAL value stored by the last channel 2 input e...

Page 202: ...DMA control register TMR3_DMACTRL Bit Register Reset value Type Description Bit 15 13 Reserved 0x0 resd Kept at its default value Bit 12 8 DTB 0x00 rw DMA transfer bytes This field defines the number of DMA transfers 00000 1 byte 00001 2 bytes 00010 3 bytes 00011 4 bytes 10000 17 bytes 10001 18 bytes Bit 7 5 Reserved 0x0 resd Kept at its default value Bit 4 0 ADDR 0x00 rw DMA transfer address offs...

Page 203: ...IRAW C1IN DIV C1IFP1 C1IN C1DT C1C 0 IN MODE C1C 0 OUT MODE C1DT Compare C1ORAW Output1 control C1OUT CK_INT from CRM DIV counter preload Overflow event TMRx_CH1 CNT counter Capture 14 3 3 TMR14 functional overview 14 3 3 1Count clock The counter of TMR14 can be clocked by the internal clock CK_INT Figure 14 39 Count clock CK_INT form CRM DIV_counter CK_CNT CNT_counter Internal clock CK_INT By def...

Page 204: ...t Set OVFEN 1 in the TMRx_CTRL1 to disable generation of update events The OVFS bit in the TMRx_CTRL1 register is used to select overflow event source By default counter overflow underflow setting OVFSWTR bit and the reset signal generated by the slave timer controller in reset mode trigger the generation of an overflow event When the OVFS bit is set only counter overflow underflow triggers an ove...

Page 205: ... then outputs the signal CxIFPx after edge selection The edge selection is controlled by CxP and CxCP bits and can be selected as rising edge falling edge or both edges active CxIFPx inputs the capture signal selector and then outputs the signal CxIN after selection The capture signal selector is controlled by the CxC bits The source of CxIN can be set as CxIFPx The CyIFPx x y is the CyIFPy from c...

Page 206: ...MR output consists of a comparator and an output controller It is used to program the period duty cycle and polarity of the output signal Figure 14 47 Capture compare channel output stage channel 1 Output mode controller C1ORAW Output enable circuit C1OUT CVAL C1DT CVAL C1DT CVAL C1DT Compare Polarity selection Output mode Write CxC 1 0 2 b00 to configure the channel as output to implement multipl...

Page 207: ... 011 to enable output compare mode In this case when the counter value matches the value of the CxDT register the CxORAW is forced high low or toggling Figure 14 48 gives an example of output compare mode toggle with C1DT 0x3 When the counter value is equal to 0x3 C1OUT toggles Figure 14 49 gives an example of the combination between upcounting mode and PWM mode A The output signal behaves when PR...

Page 208: ...ffer enable 0 Period buffer is disabled 1 Period buffer is enabled Bit 6 3 Reserved 0x0 resd Kept at its default value Bit 2 OVFS 0x0 rw Overflow event source This bit is used to select overflow event or DMA request sources 0 Counter overflow setting the OVFSWTR bit or overflow event generated by slave timer controller 1 Only counter overflow generates an overflow event Bit 1 OVFEN 0x0 rw Overflow...

Page 209: ...5 2 Reserved 0x0000 resd Kept at its default value Bit 1 C1SWTR 0x0 wo Channel 1 event triggered by software This bit is set by software to generate a channel 1 event 0 No effect 1 Generate a channel 1 event Bit 0 OVFSWTR 0x0 wo Overflow event triggered by software This bit is set by software to generate an overflow event 0 No effect 1 Generate an overflow event 14 3 4 5 Channel mode register1 TMR...

Page 210: ...are the CVAL with C1DT before generating an output 1 No need to compare the CVAL and C1DT An output is generated immediately when a trigger event occurs Bit 1 0 C1C 0x0 rw Channel 1 configuration This field is used to define the direction of the channel 1 input or output and the selection of input pin when C1EN 0 00 Output 01 Input C1IN is mapped on C1IFP1 10 Reserved 11 Reserved Input capture mod...

Page 211: ...es 10 An input compare is generated every 4 active edges 11 An input compare is generated every 8 active edges Note the divider is reset once C1EN 0 Bit 1 0 C1C 0x0 rw Channel 1 configuration This field is used to define the direction of the channel 1 input or output and the selection of input pin when C1EN 0 00 Output 01 Input C1IN is mapped on C1IFP1 10 Reserved 11 Reserved ...

Page 212: ...s connected to the standard CxOUT channel depends on the CxOUT channel state and the GPIO and IOMUX registers 14 3 4 7 Counter value TMR14_CVAL Bit Register Reset value Type Description Bit 15 0 CVAL 0x0000 rw Counter value 14 3 4 8 Division value TMR14_DIV Bit Register Reset value Type Description Bit 15 0 DIV 0x0000 rw Divider value The counter clock frequency fCK_CNT fTMR_CLK DIV 15 0 1 DIV con...

Page 213: ... Channel input remap register TMR14_RMP Bit Register Reset value Type Description Bit 15 0 Reserved 0x00 resd Kept at its default value Bit 1 0 TMR14_CH1_IRMP 0x0 rw TMR14 channel 1 input remap 00 TMR14 channel 1 input is connected to GPIO 01 ERTC_CLK 10 HEXT 32 11 CLK_OUT ...

Page 214: ...ock control CSS Clock Security System TMRx_BRK TMRx_CH2 TMRx_CH1 Polarity selection Reset mode TMRx_DIV CNT counter CH2 edge detector CH2 filter C2IFP2 C2IFP1 C2IRAW C1IFP2 CH1 edge detector CH1 filter C1IFP1 C1IRAW STCI STCI C2IN DIV C2IN C1IN DIV C1IN C2DT C2C 0 C1DT C1C 0 IN MODE IN MODE C2C 0 C1C 0 OUT MODE OUT MODE C2DT C1DT CNT counter C2ORAW C1ORAW Output2 control Output1 control C2OUT C1CO...

Page 215: ...IFP2 STIS 3 b110 channel 2 signal after filtering and polarity selection To use external clock mode A follow the configuration steps as below Configure the external clock source TRGIN When TMRx_CH1 is selected as the TRGIN configure the channel 1 input filter by setting the C1DF 3 0 bit in the TMRx_CM1 register and channel 1 input polarity by setting the C1P C1CP in the TMRx_CCTRL register When TM...

Page 216: ...gister to set counting period Set the TMRx_DIV register to set counting frequency Set the STIS 2 0 bit range 3 b000 3 b011 in the TMRx_STCTRL register and select internal trigger Set SMSEL 2 0 3 b111 in the TMRx_STCTRL register and select external clock mode A Set the TMREN bit in the TMRx_CTRL1 register to enable TMRx counter Table 14 9 TMR15 internal trigger connection Slave timer IS0 STIS 000 I...

Page 217: ...event TMRx_PR Preload Overflow event PR_shadow 1 0 TMRx_DIV Preload PRBEN DIV_shadow 0 1 PRBEN DIV_counter CNT_counter RPR_counter RPR_shadow Preload TMRx_RPR CNT_overflow TMR_CLK DIV_overflow Upcounting mode Set CMSEL 1 0 2 b00 and OWCDIR 1 b0 in the TMRx_CTRL1 register to enable upcounting mode In upcounting mode the counter counts from 0 to the value programmed in the TMRx_PR register restarts ...

Page 218: ...tive CxIFPx inputs capture signal selector and outputs the signal CxIN after selection The capture signal selector is controlled by the CxC bits The source of CxIN can be set as CxIFPx CyIFPx or STCI The CyIFPx x y is the CyIFPy from channel y and handled by channel x edge detector for example the C1IFP2 is the C1IFP1 from channel 1 and then handled by channel 2 edge detector and STCI derives from...

Page 219: ...frequency division of C1IN signal C1DIV 1 0 Enable channel 1 input capture C1EN 1 If needed enable the relevant interrupt or DMA request by setting the C1IEN bit in the TMR15_IDEN register or the C1DEN bit in the TMR15_IDEN register PWM input The PWM input mode applies to channel 1 and channel 2 To enable this mode map the C1IN and C2IN to the same TMRx_CHx and configure the CxIFPx of channel 1 2 ...

Page 220: ... 0 1 2 COUNTER C1C CH1 0x1 reset counter and C1DT capture C1P 0x0 C2C 0x2 C2P 0x1 STIS 0x5 SMSEL 0x6 0xA 0x4 C1DT C2DT 0x0 C2DT capture 3 4 5 6 7 8 9 A 0 1 2 14 4 3 4 TMR output function The TMR output consists of a comparator and an output controller It is used to program the period duty cycle and polarity of the output signal The advanced control timer output function varies from one channel to ...

Page 221: ...le channel output Set the OEN bit in the TMRx_BRK register to enable TMRx output Set the corresponding GPIO of TMR output channel as the multiplexed mode Set the TMREN bit in the TMRx_CTRL1 register to enable TMRx counter PWM mode B Set CxOCTRL 3 b111 to enable PWM mode B In upcounting when TMRx_C1DT TMRx_CVAL C1ORAW outputs low otherwise outputs high In downcounting when TMRx_C1DT TMRx_CVAL C1ORA...

Page 222: ...ves an example of the combination between upcounting mode and one pulse PWM mode B The counter only counts only one cycle and the output signal sends only one pulse Figure 14 66 C1ORAW toggles when counter value matches the C1DT value 0 1 2 3 31 32 0 1 2 3 31 32 0 1 2 3 COUNTER 31 32 0 1 PR 15 0 C1ORAW TMR_CLK 0 DIV 15 0 32 011 C1OCTRL 2 0 3 C1DT 15 0 Figure 14 67 Upcounting mode and PWM mode A 0 ...

Page 223: ...e insertion The channel 1 of the TMR15 timer contains a set of reverse channel output This function is enabled by the CxCEN bit and its polarity is defined by CxCP Refer to Table 14 11 for more information about the output state of CxOUT and CxCOUT The dead time is activated when switching to IDLEF state OEN falling down to 0 Setting both CxEN and CxCEN bits and using DTC 7 0 bit to insert dead ti...

Page 224: ...t is disabled otherwise the output enable remains high When complementary outputs are used The outputs are first put in reset state that is inactive state depending on the polarity This is done asynchronously so that it works even if no clock is provided to the timer If the timer clock is still active then the dead time generator is activated The CxIOS and CxCIOS bits are used to program the level...

Page 225: ...CP polarity select CxP polarity select DTC dead time CxORAW OR BRKEN break trigger break enable OEN break event AND overflow event AOEN auto enable BRK TMRx_BRK BRKV polarity selection Clock failure event From clock control CSS Clock Security System 1 0 GPIO output enable TMRx_BRK 1 0 OR AND 0 1 AND OR FCSODIS CxCEN CxEN OR AND FCSOEN FCSOEN CxCE GPIO output enable TMR_CHx TMR_CHxC Figure 14 71 Ex...

Page 226: ... Example of suspend mode 0 1 2 3 4 5 6 7 8 9 COUNTER A B C D 10 PR 15 0 TMR_CLK 0 DIV 15 0 32 101 STIS 2 0 101 SMSEL 2 0 CI1F1 TMR_EN CNT_CLK Slave mode Trigger mode The counter can start counting on the rising edge of a selected trigger input TMR_EN 1 Figure 14 74 Example of trigger mode 0 1 2 3 4 5 COUNTER PR 15 0 TMR_CLK 0 DIV 15 0 32 101 STIS 2 0 110 SMSEL 2 0 CI1F1 TMR_EN 6 7 9 10 A B 30 31 0...

Page 227: ... TMR15_CTRL1 Bit Register Reset value Type Description Bit 15 10 Reserved 0x0 resd Kept at its default value Bit 9 8 CLKDIV 0x0 rw Clock divider 00 Normal 01 Divided by 2 10 Divided by 4 11 Reserved Bit 7 PRBEN 0x0 rw Period buffer enable 0 Period buffer is disabled 1 Period buffer is enabled Bit 6 4 Reserved 0x0 resd Kept at its default value Bit 3 OCMEN 0x0 rw One cycle mode enable This bit is u...

Page 228: ... 0x0 rw Channel control bit refresh select For channels with complementary output when the channel control bit has buffer feature 0 Refresh channel control bit by setting the HALL bit 1 Refresh channel control bit by setting the HALL or with the rising edge of TRGIN Bit 1 Reserved 0x0 resd Kept at its default value Bit 0 CBCTRL 0x0 rw Channel buffer control For channels with complementary output 0...

Page 229: ...it 14 TDEN 0x0 rw Trigger DMA request enable 0 Disabled 1 Enabled Bit 13 HALLDE 0x0 rw HALL DMA request enable 0 Disabled 1 Enabled Bit 12 11 Reserved 0x0 resd Kept at its default value Bit 10 C2DEN 0x0 rw Channel 2 DMA request enable 0 Disabled 1 Enabled Bit 9 C1DEN 0x0 rw Channel 1 DMA request enable 0 Disabled 1 Enabled Bit 8 OVFDEN 0x0 rw Overflow event DMA request enable 0 Disabled 1 Enabled ...

Page 230: ...ve edge is detected on TRGIN input or any edge in suspend mode Bit 5 HALLIF 0x0 rw0c HALL interrupt flag This bit is set by hardware and cleared by writing 0 at a trigger event 0 No HALL event occurred 1 HALL event occurred HALL event CxEN CxCEN and CxOCTRL have been updated Bit 4 3 Reserved 0x0 resd Kept at its default value Bit 2 C2IF 0x0 rw0c Channel 2 interrupt flag Please refer to C1IF descri...

Page 231: ...WTR 0x0 wo Overflow event triggered by software This bit is set by software to generate an overflow event 0 No effect 1 Generate an overflow event 14 4 4 7 TMR15 channel mode register1 TMR15_CM1 The channel can be used in input capture mode or output compare mode The direction of a channel is defined by the corresponding CxC bits All the other bits of this register have different functions in inpu...

Page 232: ...put level is not only subject to the changes of C1ORAW but also the output polarity set by CCTRL Bit 3 C1OBEN 0x0 rw Channel 1 output buffer enable 0 Buffer function of TMR15_C1DT is disabled The new value written to the TMR15_C1DT takes effect immediately 1 Buffer function of TMR15_C1DT is enabled The value to be written to the TMR15_C1DT is stored in the buffer register and can be sent to the TM...

Page 233: ...𝐼𝑁𝐺 f𝐶𝐾_𝐼𝑁𝑇 N 2 1001 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐷𝑇𝑆 8 N 8 0010 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐶𝐾_𝐼𝑁𝑇 N 4 1010 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐷𝑇𝑆 16 N 5 0011 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐶𝐾_𝐼𝑁𝑇 N 8 1011 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐷𝑇𝑆 16 N 6 0100 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐷𝑇𝑆 2 N 6 1100 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐷𝑇𝑆 16 N 8 0101 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐷𝑇𝑆 2 N 8 1101 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐷𝑇𝑆 32 N 5 0110 f𝑆𝑀𝑃𝐿𝐼𝑁𝐺 f𝐷𝑇𝑆 4 N 6 1110 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐷𝑇𝑆 32 N 6 0111 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐷𝑇𝑆 4 N 8 1111 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐷𝑇𝑆 32 N 8 Bit 3 2 C1IDIV 0x0 rw Channel 1 input d...

Page 234: ...dge for input signals Refer to C1P description Bit 2 C1CEN 0x0 rw Channel 1 complementary enable 0 Channel 1 complementary output disabled 1 Channel 1 complementary output enabled Bit 1 C1P 0x0 rw Channel 1 polarity When the channel 1 is configured as output mode 0 C1OUT is active high 1 C1OUT is active low When the channel 1 is configured as input mode C1CP works with C1P bit to define the active...

Page 235: ... CxOUT CxORAW xor CxP Cx_EN 1 Off state Output enabled with inactive level CxCOUT CxCP CxCEN 1 1 1 1 CxORAW polarity dead time Cx_EN 1 CxORAW inverted polarity dead time CxCEN 1 0 0 X 0 0 Output disabled corresponding IO disconnected from timer and IO floating Asynchronously CxOUT CxP Cx_EN 0 CxCOUT CxCP CxCEN 0 If the clock is present after a dead time CxOUT CxIOS CxCOUT CxCIOS assuming that CxIO...

Page 236: ...on rate of overflow events An overflow event is generated when the repetition counter reaches 0 14 4 4 13 TMR15 channel 1 data register TMR15_C1DT Bit Register Reset value Type Description Bit 15 0 C1DT 0x0000 rw Channel 1 data register When the channel 1 is configured as input mode The C1DT is the CVAL value stored by the last channel 1 input event C1IN When the channel 1 is configured as output ...

Page 237: ...UT and CxCOUT outputs 0 Disabled 1 Enabled Bit 14 AOEN 0x0 rw Automatic output enable OEN is set automatically at an overflow event 0 Disabled 1 Enabled Bit 13 BRKV 0x0 rw Brake input validity This bit is used to select the active level of a brake input 0 Brake input is active low 1 Brake input is active high Bit 12 BRKEN 0x0 rw Brake enable This bit is used to enable brake input 0 Brake input is ...

Page 238: ...EN FCSODIS FCSOEN and DTC 7 0 can all be write protected Thus it is necessary to configure write protection when writing to the TMRx_BRK register for the first time 14 4 4 16 TMR15 DMA control register TMR15_DMACTRL Bit Register Reset value Type Description Bit 15 13 Reserved 0x0 resd Kept at its default value Bit 12 8 DTB 0x00 rw DMA transfer bytes This field defines the number of DMA transfers 0...

Page 239: ...event Support TMR burst DMA transfer Figure 14 75 Block diagram of general purpose TMR16 and TMR17 BRK Clock failure event From clock control CSS Clock Security System TMRx_BRK TMRx_CH1 Polarity selection TMRx_DIV CNT counter CH1 edge detector CH1 filter C1IRAW C1IN DIV C1IFP1 C1IN C1DT C1C 0 IN MODE C1C 0 OUT MODE C1DT CNT counter C1ORAW Output1 control C1COUT C1OUT Dead time DTC DIV counter RPR ...

Page 240: ...by default Set OVFEN 1 in the TMRx_CTRL1 to disable generation of update events The OVFS bit in the TMRx_CTRL1 register is used to select overflow event source By default counter overflow underflow setting OVFSWTR bit and the reset signal generated by the slave timer controller in reset mode trigger the generation of an overflow event When the OVFS bit is set only counter overflow underflow trigge...

Page 241: ...FIF 14 5 3 3 TMR input function Each of timers TMR16 and TMR17 has one independent channel that can be configured as input or output As input each channel input signal is processed as below TMRx_CHx outputs the pre processed CxIRAW Set the C1INSEL bit to select TMRx_CHx as the source of CxIRAW CxIRAW inputs to the digital filter and outputs a filtered signal CxIF Set the sampling frequency and sam...

Page 242: ...e TMRx_CxDT register overwrites the recorded value with the current counter value and the CxRF is set to 1 To capture the rising edge of C1IN input following the configuration procedure mentioned below Set C1C 01 in the TMRx_CM1 register to select the C1IN as channel 1 input Set the filter bandwidth of C1IN signal CxDF 3 0 Set the active edge on the C1IN channel by writing C1P 0 rising edge in the...

Page 243: ...mode Set CxOCTRL 3 b100 101 to enable forced output mode In this case the CxORAW is forced to be the programmed level irrespective of the counter value Despite this the channel flag bit and DMA request still depend on the compare result Output compare mode Set CxOCTRL 3 b001 010 011 to enable output compare mode In this case when the counter value matches the value of the CxDT register the CxORAW ...

Page 244: ...s a set of reverse channel output This function is enabled by the CxCEN bit and its polarity is defined by CxCP Refer to Table 14 13 for more information about the output state of CxOUT and CxCOUT The dead time is activated when switching to IDLEF state OEN falling down to 0 Setting both CxEN and CxCEN bits and using DTC 7 0 bit to insert dead time of different durations After the dead time insert...

Page 245: ...ut is disabled otherwise the output enable remains high When complementary outputs are used The outputs are first put in reset state that is inactive state depending on the polarity This is done asynchronously so that it works even if no clock is provided to the timer If the timer clock is still active then the dead time generator is activated The CxIOS and CxCIOS bits are used to program the leve...

Page 246: ...ime CxORAW OR BRKEN break trigger break enable OEN break event AND overflow event AOEN auto enable BRK TMRx_BRK BRKV polarity selection Clock failure event From clock control CSS Clock Security System 1 0 GPIO output enable TMRx_BRK 1 0 OR AND 0 1 AND OR FCSODIS CxCEN CxEN OR AND FCSOEN FCSOEN CxCE GPIO output enable TMR_CHx TMR_CHxC Figure 14 90 Example of TMR brake function CxORAW Delay Delay De...

Page 247: ... 0x0 rw One cycle mode enable This bit is use to select whether to stop counting at an update event 0 The counter does not stop at an update event 1 The counter stops at an update event Bit 2 OVFS 0x0 rw Overflow event source This bit is used to select overflow event or DMA request sources 0 Counter overflow setting the OVFSWTR bit or overflow event generated by slave timer controller 1 Only count...

Page 248: ...nabled Bit 7 BRKIE 0x0 rw Brake interrupt enable 0 Disabled 1 Enabled Bit 6 Reserved 0x0 resd Kept at its default value Bit 5 HALLIEN 0x0 rw HALL interrupt enable 0 Disabled 1 Enabled Bit 4 2 Reserved 0x0 resd Kept at its default value Bit 1 C1IEN 0x0 rw Channel 1 interrupt enable 0 Disabled 1 Enabled Bit 0 OVFIEN 0x0 rw Overflow interrupt enable 0 Disabled 1 Enabled 14 5 4 4 TMR16 and TMR17 inter...

Page 249: ...d 0x0 resd Kept at its default value Bit 5 HALLSWTR 0x0 wo HALL event triggered by software This bit is set by software to generate a HALL event 0 No effect 1 Generate a HALL event Note This bit acts only on channels that have complementary output Bit 4 2 Reserved 0x0 resd Kept at its default value Bit 1 C1SWTR 0x0 wo Channel 1 event triggered by software This bit is set by software to generate a ...

Page 250: ...x_C1DT is stored in the buffer register and can be sent to the TMRx_C1DT register only on an overflow event Bit 2 C1OIEN 0x0 rw Channel 1 output enable immediately In PWM mode A or B this bit is used to accelerate the channel 1 output s response to the trigger event 0 Need to compare the CVAL with C1DT before generating an output 1 No need to compare the CVAL and C1DT An output is generated immedi...

Page 251: ...annel 1 input divider 00 No divider An input capture is generated at each active edge 01 An input compare is generated every 2 active edges 10 An input compare is generated every 4 active edges 11 An input compare is generated every 8 active edges Note the divider is reset once C1EN 0 Bit 1 0 C1C 0x0 rw Channel 1 configuration This field is used to define the direction of the channel 1 input or ou...

Page 252: ... or output is disabled 1 Input or output is enabled Table 14 13 Complementary output channel CxOUT and CxCOUT control bits with brake function Control bit Output state 1 OEN bit FCSODIS bit FCSOEN bit CxEN bit CxCEN bit CxOUT output state CxCOUT output state 1 X 0 0 0 Output disabled no driven by the timer CxOUT 0 Cx_EN 0 Output disabled no driven by the timer CxCOUT 0 CxCEN 0 0 0 1 Output disable...

Page 253: ... 5 4 9 TMR16 and TMR17 division value TMRx_DIV Bit Register Reset value Type Description Bit 15 0 DIV 0x0 rw Divider value The counter clock frequency fCK_CNT fTMR_CLK DIV 15 0 1 The value of this register is transferred to the actual prescaler register when an overflow event occurs 14 5 4 10 TMR16 and TMR17 period register TMRx_PR Bit Register Reset value Type Description Bit 15 0 PR 0x0 rw Perio...

Page 254: ...tatus when holistic output disable This bit acts on the channels that have complementary output It is used to set the channel state when the timer is inactive and MOEN 0 0 CxOUT CxCOUT outputs are disabled 1 CxOUT CxCOUT outputs are enabled Output idle level Bit 9 8 WPC 0x0 rw Write protection configuration This field is used to enable write protection 00 Write protection is OFF 01 Write protectio...

Page 255: ...bytes 10001 18 bytes Bit 7 5 Reserved 0x0 resd Kept at its default value Bit 4 0 ADDR 0x00 rw DMA transfer address offset ADDR is defined as an offset starting from the address of the TMRx_CTRL1 register 00000 TMRx_CTRL1 00001 TMRx_CTRL2 00010 TMRx_STCTRL 14 5 4 15 TMR16 and TMR17 DMA data register TMRx_DMADT Bit Register Reset value Type Description Bit 15 0 DMADT 0x0000 rw DMA data register A wr...

Page 256: ... Security System TMRx_BRK TMRx_CH4 TMRx_CH3 TMRx_CH2 TMRx_CH1 TMRX_EXT Polarity selection Polarity selection edge detector prescaler Reset mode Encoder interface TMRx_DIV CNT counter CH4 edge detector C4DT CH4 filter CH3 edge detector CH3 filter C4IFP4 C4IFP3 C4IRAW C3IFP4 C3IFP3 C3IRAW CH2 edge detector CH2 filter C2IFP2 C2IFP1 C2IRAW C1IFP2 CH1 edge detector CH1 filter C1IFP1 C1IRAW STCI STCI ST...

Page 257: ...External clock TRGIN EXT The counter clock can be provided by two external clock sources namely TRGIN and EXT signals When SMSEL 3 b111 external clock mode A is selected Set the STIS 2 0 bit to select TRGIN signal to drive the counter to start counting The external clock sources include C1INC STIS 3 b100 channel 1 rising edge and falling edge C1IFP1 STIS 3 b101 channel 1 signal with filtering and ...

Page 258: ...ty by setting the ESP bit in the TMRx_STCTRL register Set external signal frequency division by setting the ESDIV 1 0 bit in the TMRx_STCTRL register Set external signal filter by setting the ESF 3 0 bit in the TMRx_STCTRL register Enable external clock mode B by setting the ECMBEN bit in the TMRx_STCTRL register Set counter counting frequency by setting the DIV 15 0 bit in the TMRx_DIV register S...

Page 259: ...counting Each timer consists of a 16 bit prescaler which is used to generate the CK_CNT that enables the counter to count The frequency division relationship between the CK_CNT and TMR_CLK can be adjusted by setting the value of the TMRx_DIV register The prescaler value can be modified at any time but it takes effect only when the next overflow event occurs The internal trigger input is configured...

Page 260: ...MRx_CTRL1 to disable generation of update events The OVFS bit in the TMRx_CTRL1 register is used to select overflow event source By default counter overflow underflow setting OVFSWTR bit and the reset signal generated by the slave timer controller in reset mode trigger the generation of an overflow event When the OVFS bit is set only counter overflow underflow triggers an overflow event Setting th...

Page 261: ...Clear Up down counting mode Set CMSEL 1 0 2 b00 in the TMRx_CTRL1 register to enable the up down counting mode In this mode the counter counts up down alternatively When the counter counts from the value programmed in the TMR1_PR register down to 1 an underflow event is generated and then restarts counting from 0 when the counter counts from 0 to the value of the TMR1_PR register 1 an overflow eve...

Page 262: ...verflow An overflow event is generated only when the repetition counter reaches 0 The frequency of the overflow event can be adjusted by setting the repetition counter value Figure 14 104 OVFIF in upcounting mode and up down counting mode 0 1 2 3 31 32 0 1 2 3 31 32 0 1 2 3 COUNTER 31 32 0 1 2 RPR 7 0 2 1 0 RPR_CNT overflow OVFIF 2 0 1 2 3 31 32 31 30 2F 1 0 1 2 3 COUNTER 31 32 31 2F 2 RPR 7 0 2 1...

Page 263: ... direction is dependent on the C1IFP1 edge direction C2IFP2 level and C2IFP2 edge direction C1IFP1 level To use the encoder mode follow the configuration steps as below Set the C1DF 3 0 bit in the TMRx_CM1 register to set channel 1 input signal filtering set the C1P bit in the TMRx_CCTRL register to set channel 1 input signal active level Set the C2DF 3 0 bit in the TMRx_CM1 register to set channe...

Page 264: ...active CxIFPx inputs capture signal selector and then outputs the signal CxIN after setection The capture signal selector is controlled by the CxC bits The source of CxIN can be set as CxIFPx CyIFPx or STCI The CyIFPx x y is the CyIFPy from channel y and handled by channel x edge detector for example the C1IFP2 is the C1IFP1 from channel 1 and then handled by channel 2 edge detector and STCI deriv...

Page 265: ...the C1DEN bit in the TMR1_IDEN register Timer Input XOR function The timer input pins TMR1_CH1 TMR1_CH2 and TMR1_CH3 are connected to the channel 1 selected by setting the C1INSE in the TMRx_CTRL2 register through an XOR gate The XOR gate can be used to connect Hall sensors For example connect the three XOR inputs to the three Hall sensors respectively so as to calculate the position and speed of ...

Page 266: ...10 PWM input mode A 0 1 2 3 4 5 6 7 8 9 A 0 1 2 COUNTER C1C CH1 0x1 reset counter and C1DT capture C1P 0x0 C2C 0x2 C2P 0x1 STIS 0x5 SMSEL 0x6 0xA 0x4 C1DT C2DT 0x0 C2DT capture 3 4 5 6 7 8 9 A 0 1 2 14 6 3 4 TMR output function The TMR output consists of a comparator and an output controller It is used to program the period duty cycle and polarity of the output signal Figure 14 111 Output stage fo...

Page 267: ...able TMRx output Set the corresponding GPIO of TMR output channel as the multiplexed mode Set the TMREN bit in the TMRx_CTRL1 register to enable TMRx counter PWM mode B Set CxOCTRL 3 b111 to enable PWM mode B In upcounting when TMRx_C1DT TMRx_CVAL C1ORAW outputs low otherwise outputs high In downcounting when TMRx_C1DT TMRx_CVAL C1ORAW outputs high otherwise outputs low Forced output mode Set CxOC...

Page 268: ...ng mode and one pulse PWM mode B The counter only counts only one cycle and the output signal sends only one pulse Figure 14 113 C1ORAW toggles when counter value matches the C1DT value 0 1 2 3 31 32 0 1 2 3 31 32 0 1 2 3 COUNTER 31 32 0 1 PR 15 0 C1ORAW TMR_CLK 0 DIV 15 0 32 011 C1OCTRL 2 0 3 C1DT 15 0 Figure 14 114 Upcounting mode and PWM mode A 0 1 2 3 31 32 0 1 2 3 31 32 0 1 2 3 COUNTER 31 32 ...

Page 269: ...channel is cleared by applying a high level to the EXT input The CxORAW signal remains unchanged until the next overflow event This function can only be used in output capture or PWM modes and does not work in forced mode Figure 14 117 shows the example of clearing CxORAW When the EXT input is high the CxORAW signal which was originally high is driven low when the EXT is low the CxORAW signal outp...

Page 270: ...n be the brake input pin or a clock failure event The polarity is controlled by the BRKV bit When a brake event occurs there are the following actions The OEN bit is cleared asynchronously and the channel output state is selected by setting the FCSODIS bit This function works even if the MCU oscillator is off Once OEN 0 the channel output level is defined by the CxIOS bit If FCSODIS 0 the timer ou...

Page 271: ... event From clock control CSS Clock Security System OR BRKV polarity selection BRKEN break trigger break enable OEN break event AND overflow event AOEN auto enable CxCP polarity select CxP polarity select DTC dead time CxORAW OR BRKEN break trigger break enable OEN break event AND overflow event AOEN auto enable BRK TMRx_BRK BRKV polarity selection Clock failure event From clock control CSS Clock ...

Page 272: ...on as the trigger input is low Figure 14 122 Example of suspend mode 0 1 2 3 4 5 6 7 8 9 COUNTER A B C D 10 PR 15 0 TMR_CLK 0 DIV 15 0 32 101 STIS 2 0 101 SMSEL 2 0 CI1F1 TMR_EN CNT_CLK Slave mode Trigger mode The counter can start counting on the rising edge of a selected trigger input TMR_EN 1 Figure 14 123 Example of trigger mode 0 1 2 3 4 5 COUNTER PR 15 0 TMR_CLK 0 DIV 15 0 32 101 STIS 2 0 11...

Page 273: ...T 0x3C 0x0000 TMR1_C4DT 0x40 0x0000 TMR1_BRK 0x44 0x0000 TMR1_DMACTRL 0x48 0x0000 TMR1_DMADT 0x4C 0x0000 14 6 4 1 TMR1 control register1 TMR1_CTRL1 Bit Register Reset value Type Description Bit 15 10 Reserved 0x00 resd Kept at its default value Bit 9 8 CLKDIV 0x0 rw Clock division 00 Normal 01 Divided by 2 10 Divided by 4 11 Reserved Bit 7 PRBEN 0x0 rw Period buffer enable 0 Period buffer is disab...

Page 274: ...he counter does not stop at an update event 1 The counter stops at an update event Bit 2 OVFS 0x0 rw Overflow event source This bit is used to select overflow event or DMA request sources 0 Counter overflow setting the OVFSWTR bit or overflow event generated by slave timer controller 1 Only counter overflow generates an overflow event Bit 1 OVFEN 0x0 rw Overflow event enable 0 Enabled 1 Disabled B...

Page 275: ... 011 Compare pulse 100 C1ORAW signal 101 C2ORAW signal 110 C3ORAW signal 111 C4ORAW signal Bit 3 DRS 0x0 rw DMA request source 0 Capture compare event 1 Overflow event Bit 2 CCFS 0x0 rw Channel control bit flash selection This bit only acts on channels with complementary output If the channel control bits are buffered 0 Control bits are updated by setting the HALL bit 1 Control bits are updated by...

Page 276: ...ction 1 IS1 010 Internal selection 2 IS2 011 Internal selection 3 IS3 100 C1IRAW input detector C1INC 101 Filtered input 1 C1IF1 110 Filtered input 2 C1IF2 111 External input EXT Refer to Table 14 14 for details on ISx for each timer Bit 3 COSSEL 0x0 rw Channel output switch selection This field is used to select the switch source of CxORAW 0 Select EXT as the switch source of CxORAW 1 Select CxOR...

Page 277: ...led Bit 8 OVFDEN 0x0 rw Overflow event DMA request enable 0 Disabled 1 Enabled Bit 7 BRKIE 0x0 rw Brake interrupt enable 0 Disabled 1 Enabled Bit 6 TIEN 0x0 rw Trigger interrupt enable 0 Disabled 1 Enabled Bit 5 HALLIEN 0x0 rw HALL interrupt enable 0 Disabled 1 Enabled Bit 4 C4IEN 0x0 rw Channel 4 interrupt enable 0 Disabled 1 Enabled Bit 3 C3IEN 0x0 rw Channel 3 interrupt enable 0 Disabled 1 Enab...

Page 278: ...n TRGIN input or any edge in suspend mode Bit 5 HALLIF 0x0 rw0c HALL interrupt flag This bit is set by hardware on HALL event It is cleared by writing 0 0 No Hall event occurs 1 Hall event is detected HALL even CxEN CxCEN and CxOCTRL are updated Bit 4 C4IF 0x0 rw0c Channel 4 interrupt flag Please refer to C1IF description Bit 3 C3IF 0x0 rw0c Channel 3 interrupt flag Please refer to C1IF descriptio...

Page 279: ...fect 1 Generate an overflow event 14 6 4 7 TMR1 channel mode register1 TMR1_CM1 The channel can be used in input capture mode or output compare mode The direction of a channel is defined by the corresponding CxC bits All the other bits of this register have different functions in input and output modes The CxOx describes its function in output mode when the channel is in output mode while the CxIx...

Page 280: ...ediately In PWM mode A or B this bit is used to accelerate the channel 1 output s response to the trigger event 0 Need to compare the CVAL with C1DT before generating an output 1 No need to compare the CVAL and C1DT An output is generated immediately when a trigger event occurs Bit 1 0 C1C 0x0 rw Channel 1 configuration This field is used to define the direction of the channel 1 input or output an...

Page 281: ...TMR1 channel mode register2 TMR1_CM2 The channel can be used in input capture mode or output compare mode The direction of a channel is defined by the corresponding CxC bits All the other bits of this register have different functions in input and output modes The CxOx describes its function in output mode when the channel is in output mode while the CxIx describes its function in output mode when...

Page 282: ... when C3EN 0 00 Output 01 Input C3IN is mapped on C3IFP3 10 Input C3IN is mapped on C4IFP3 11 Input C3IN is mapped on STCI This mode works only when the internal trigger input is selected by STIS 14 6 4 9 TMR1 Channel control register TMR1_CCTRL Bit Register Reset value Type Description Bit 15 14 Reserved 0x0 resd Kept its default value Bit 13 C4P 0x0 rw Channel 4 polarity Please refer to C1P desc...

Page 283: ...d no driven by the timer CxCOUT 0 CxCEN 0 0 1 1 CxORAW polarity dead time Cx_EN 1 CxORAW inverted polarity dead time CxCEN 1 1 0 0 Output disabled no driven by the timer CxOUT CxP Cx_EN 0 Output disabled no driven by the timer CxCOUT CxCP CxCEN 0 1 0 1 Off state Output enabled with inactive level CxOUT CxP Cx_EN 1 CxORAW polarity CxCOUT CxORAW xor CxCP CxCEN 1 1 1 0 CxORAW polarity CxOUT CxORAW xo...

Page 284: ...t Register Reset value Type Description Bit 15 8 Reserved 0x00 rw Kept at its default value Bit 7 0 RPR 0x00 rw Repetition of period value This field is used to reduce the generation rate of overflow events An overflow event is generated when the repetition counter reaches 0 14 6 4 14 TMR1 channel 1 data register TMR1_C1DT Bit Register Reset value Type Description Bit 15 0 C1DT 0x0000 rw Channel 1...

Page 285: ... Type Description Bit 15 OEN 0x0 rw Output enable This bit acts on the channels as output It is used to enable CxOUT and CxCOUT outputs 0 Disabled 1 Enabled Bit 14 AOEN 0x0 rw Automatic output enable OEN is set automatically at an overflow event 0 Disabled 1 Enabled Bit 13 BRKV 0x0 rw Brake input validity This bit is used to select the active level of a brake input 0 Brake input is active low 1 Br...

Page 286: ...an all be write protected Thus it is necessary to configure write protection when writing to the TMRx_BRK register for the first time 14 6 4 19 TMR1 DMA control register TMR1_DMACTRL Bit Register Reset value Type Description Bit 15 13 Reserved 0x0 resd Kept at its default value Bit 12 8 DTB 0x00 rw DMA transfer bytes This field defines the number of DMA transfers 00000 1 byte 00001 2 bytes 00010 3...

Page 287: ...ster Figure 15 1 Window watchdog block diagram EN 7 bit window value WIN 6 0 Prescaler 1 2 4 8 7 bit counter CNT 6 0 PCLK 4096 CNT 0x40 reset reload at CNT WIN reset To prevent system reset the counter must be reloaded only when its value is less than the value stored in the window register and greater than 0x40 The WWDT counter is clocked by a divided APB1_CLK with the division factor being defin...

Page 288: ...CortexTM M4 core halted the WWDT counter stops counting by setting the WWDT_PAUSE in the DEBUG module 15 5WWDT registers These peripheral registers must be accessed by word 32 bits Table 15 2 WWDT register map and reset value Register name Offset Reset value WWDT_CTRL 0x00 0x7F WWDT_CFG 0x04 0x7F WWDT_STS 0x08 0x00 15 5 1 Control register WWDT_CTRL Bit Register Reset value Type Description Bit 31 ...

Page 289: ...vided by 8192 10 PCLK1 divided by 16384 11 PCLK1 divided by 32768 Bit 6 0 WIN 0x7F rw Window value If the counter is reloaded while its value is greater than the window register value a reset is generated The counter must be reloaded between 0x40 and WIN 6 0 15 5 3 Status register WWDT_STS Bit Register Reset value Type Description Bit 31 1 Reserved 0x0000 0000 resd Kept at its default value Bit 0 ...

Page 290: ...lue 0xAAAA at regular intervals to reload the counter value to avoid the WDT reset WDT write protected The WDT_DIV and WDT_RLD registers are write protected Writing the value 0x5555 to the WDT_CMD register will unlock write protection The update status of these two registers are indicated by the DIVF and RLDF bits in the WDT_STS register If a different value is written to the WDT_CMD register thes...

Page 291: ...D 0x08 0x0000 0FFF WDT_STS 0x0C 0x0000 0000 16 5 1 Command register WDT_CMD Reset in Standby mode Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 0 CMD 0x0000 wo Command register 0xAAAA Reload counter 0x5555 Unlock write protected WDT_DIV and WDT_RLD 0xCCCC Enable WDT If the hardware watchdog has been enabled ignore this operation 16 5 2 Di...

Page 292: ... can be read only when RLDF 0 16 5 4 Status register WDT_STS Reset in Standby mode Bit Register Reset value Type Description Bit 31 2 Reserved 0x0000 0000 resd Kept at its default value Bit 1 RLDF 0x0 ro Reload value update complete flag 0 Reload value update complete 1 Reload value update is in process The reload register WDT_RLD can be written only when RLDF 0 Bit 0 DIVF 0x0 ro Division value up...

Page 293: ... registers 4 x interrupts alarm A periodic auto wakeup tamper detection and time stamp Multiplexed function output calibration clock output alarm events or wakeup events Multiplexed function input reference clock input one channel tamper detection and time stamp Figure 17 1 ERTC block diagram PCLK1 1 2V power domain ERTC registers APB interface VBAT domain Not powered in Standby mode LEXT LICK HEX...

Page 294: ...1 Enable power interface clock by setting PWCEN 1 in the CRM_APB1EN register 2 Unlock write protection of the battery powered domain by setting BPWEN 1 in the PWC_CTRL register 3 Write 0xCA and 0x53 to the ERTC_WP register in sequence Writing an incorrect key will activate the write protection again Table 17 1 lists the ERTC registers that can be configured only after the write protection is unloc...

Page 295: ... ERTC_DATE register is read For example reading the ERTC_SBS register will lock the values in the ERTC_TIME and ERTC_DATE registers In the case of DREN 1 the ERTC will perform direct read access to the ERTC clock and calendar located in the battery powered domain with the PCLK1 avoiding the occurrence of errors caused by time synchronization In this mode the UPDF flag is cleared by hardware To ens...

Page 296: ...t 8 or 16 second digital calibration period through the CAL8 and CAL16 bits The 8 second period takes priority over 16 second In other words when both 8 second and 16 second are enabled 8 second calibration period prevails The CALUPDF flag in the ERTC indicates the calibration status During the configuration of ERTC_SCAL registers the CALUPDF bit is set indicating that the calibration value is bei...

Page 297: ...ether to activate a time stamp on a tamper event TPTSEN 1 6 According to your needs enable a tamper interrupt TPIEN 1 7 Enable TMAP1 by setting TP1EN 1 While configuring edge detection mode the following two points deserve our attention 1 If a rising edge is configured to enable tamper detection and the tamper detection pin turns to high level before tamper detection is enabled then a tamper event...

Page 298: ...es around eight APB1_CLK clock cycles of APB1 ERTC registers are 16 bit addressable registers Table 17 4 ERTC register map and reset values Register name Offset Reset value ERTC_TIME 0x00 0x0000 0000 ERTC_DATE 0x04 0x0000 2101 ERTC_CTRL 0x08 0x0000 0000 ERTC_STS 0x0C 0x0000 0007 ERTC_DIV 0x10 0x007F 00FF ERTC_ALA 0x1C 0x0000 0000 ERTC_WP 0x24 0x0000 0000 ERTC_SBS 0x28 0x0000 0000 ERTC_TADJ 0x2C 0x...

Page 299: ...it 3 0 DU 0x1 rw Date units 17 4 3 ERTC control register ERTC_CTRL Bit Register Reset value Type Description Bit 31 24 Reserved 0x00 resd Kept at its default value Bit 23 CALOEN 0x0 rw Calibration output enable 0 Calibration output disabled 1 Calibration output enabled Bit 22 21 OUTSEL 0x0 rw Output source selection 00 Output source disabled 01 Alarm clock A 10 Alarm clock B 11 Wakeup events Bit 2...

Page 300: ...rence clock detection enable 0 Reference clock detection disabled 1 Reference clock detection enabled Bit 3 TSEDG 0x0 rw Timestamp trigger edge 0 Rising edge 1 Falling edge Bit 2 0 Reserved 0x0 resd Kept at its default value 17 4 4 ERTC initialization and status register ERTC_STS Bit Register Reset value Type Description Bit 31 17 Reserved 0x0000 resd Kept at its default value Bit 16 CALUPDF 0x0 r...

Page 301: ...r initialization flag 0 Calendar has not been initialized 1 Calendar has been initialized This bit is set when the calendar year filed ERTC_DATE is different from 0 It is cleared when the year is 0 Bit 3 TADJF 0x0 ro Time adjustment flag 0 No time adjustment 1 Time adjustment is in progress This bit is automatically set when a write access to the ERTC_TADJ register is performed It is automatically...

Page 302: ...value will re activate write protection 17 4 8 ERTC subsecond register ERTC_SBS Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 0 SBS 0x0000 ro Sub second value Subsecond is the value in the DIVB counter Clock frequency ERTC_CLK DIVA 1 17 4 9 ERTC time adjustment register ERTC_TADJ Bit Register Reset value Type Description Bit 31 ADD1S 0x0 ...

Page 303: ...e Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 0 SBS 0x0000 ro Sub second value Note The content of this register is valid only when the TSF is set in the ERTC_STS register It is cleared when TSF bit is reset 17 4 13ERTC smooth calibration register ERTC_SCAL Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 ADD ...

Page 304: ...d after 8 consecutive samples Bit 10 8 TPFREQ 0x0 rw Tamper detection frequency 0 ERTC_CLK 32768 1 ERTC_CLK 16384 2 ERTC_CLK 8192 3 ERTC_CLK 4096 4 ERTC_CLK 2048 5 ERTC_CLK 1024 6 ERTC_CLK 512 7 ERTC_CLK 256 Bit 7 TPTSEN 0x0 rw Tamper detection timestamp enable 0 Tamper detection timestamp disabled 1 Tamper detection timestamp enabled Save timestamp on a tamper event Bit 6 3 Reserved 0x0 resd Kept...

Page 305: ...is compared 2 SBS 1 0 are compared 3 SBS 2 0 are compared 14 SBS 13 0 are compared 15 SBS 14 0 are compared Bit 23 15 Reserved 0x000 rw Kept at its default value Bit 14 0 SBS 0x0000 rw Sub second value 17 4 16ERTC battery powered domain data register ERTC_BPRx Bit Register Reset value Type Description Bit 31 0 DT 0x0000 0000 rw Battery powered domain data BPR_DTx registers are powered on by VBAT s...

Page 306: ...C power supply Refer to the data sheet for more information ADC input range VREF VIN VREF In terms of digital control Regular channels and preempted channels with different priority Regular channels and preempted channels both have their own trigger detection circuit Each channel can independently define its own sampling time Conversion sequence management mechanism supports multiple channel conve...

Page 307: ...dinary data register 16 bits EXINT15 Temp sensor Input pin description VDDA Analog supply ADC analog supply VSSA Analog supply ground ADC analog supply ground ADCx_IN Analog input signal channels Refer to the data sheet for details on the input pins and voltage limits 18 4ADC functional overview 18 4 1 Channel management Analog signal channel input There are 18 analog signal channel inputs for eac...

Page 308: ...ence voltage The internal reference voltage of the typical value 1 2 V is connected to ADC1_IN17 It is mandatory to enable the ITSRVEN bit in the ADC_CTRL2 register before the internal reference channel conversion The converted data of such channel can be used to calculate the external reference voltage 18 4 2 ADC operation process Figure 18 2 shows the basic operation process of the ADC It is rec...

Page 309: ... channel conversion is triggered by ordinary channel triggers while the preempted channel conversion is triggered by preempted ones After the OCTEN or PCTEN bit is set in the ADC_CTRL2 register the ADC starts conversion after a trigger source is detected The conversion can be triggered by software writing to the OCSWTRG and PCSWTRG bits in the ADC_CTRL2 register or by external events The external ...

Page 310: ...equence and total number of the preempted channels After the sequence mode is enabled a single trigger event enables the conversion of a group of channels in order The ordinary channels start converting from the QSN1 while the preempted channels starts from the PSNx where x 4 PCLEN Figure 18 4 shows an example of the behavior in sequence mode Figure 18 4 Sequence mode ADC_IN5 ADC_IN0 ADC_IN5 OCLEN...

Page 311: ...inary channel trigger CCE flag set PCLEN 1 PSN3 ADC_IN14 PSN4 ADC_IN1 ADC_IN14 ADC_IN1 CCE and PCCE flag set ADC_IN5 ADC_IN0 CCE flag set ADC_IN14 Sampling Conversion 18 4 3 4 Partition mode The partition mode of the ordinary group can be enabled by setting the OCPEN bit in the ADC_CTRL1 register In this mode the ordinary group conversion sequence length OCLEN bit in the ADC_OSQ1 register is divid...

Page 312: ...GN bit in the ADC_CTRL2 register selects the alignment of data right aligned or left aligned In addition the converted data of the preempted group is decreased by the offset written in the ADC_PCDTOx register Thus the result may be a negative value marked by SIGN as shown in Figure 18 8 Figure 18 8 Data alignment SIGN SIGN SIGN SIGN DT 11 DT 10 DT 9 DT 8 DT 7 DT 6 DT 5 DT 4 DT 3 DT 2 DT 1 DT 0 SIG...

Page 313: ...CCS preempted channel conversion start flag PCCE preempted channel conversion end flag OCCE ordinary channel conversion end flag and VMOR voltage monitor out of range PCCE CCE and VMOR have their respective interrupt enable bits Once the interrupt bits are enabled the corresponding flag is set and an interrupt is sent to CPU 18 5ADC registers Table 18 2 lists ADC register map and their reset value...

Page 314: ...eempted group Bit 0 VMOR 0x0 rw0c Voltage monitoring out of range flag This bit is set by hardware and cleared by software writing 0 0 Voltage is within the value programmed 1 Voltage is outside the value programmed 18 5 2 ADC control register1 ADC_CTRL1 Accessible by words Bit Register Reset value Type Description Bit 31 24 Reserved 0x00 resd Kept at its default value Bit 23 OCVMEN 0x0 rw Voltage...

Page 315: ...ring out of range interrupt disabled 1 Voltage monitoring out of range interrupt enabled Bit 5 CCEIEN 0x0 rw Channel conversion end interrupt enable 0 Channel conversion end interrupt disabled 1 Channel conversion end interrupt enabled Bit 4 0 VMCSEL 0x00 rw Voltage monitoring channel select This filed is valid only when the VMSGEN is enabled 00000 ADC_IN0 channel 00001 ADC_IN1 channel 01111 ADC_I...

Page 316: ...OCDMAEN 0x0 rw DMA transfer enable of ordinary channels 0 Disabled 1 Enabled Bit 7 4 Reserved 0x0 resd Kept at its default value Bit 3 ADCALINIT 0x0 rw Initialize A D calibration This bit is set by software and cleared by hardware It is cleared after the calibration registers are initialized 0 No initialization occurred or initialization completed 1 Enable initialization or initializations is ongo...

Page 317: ...ion of channel ADC_IN17 000 1 5 cycles 001 7 5 cycles 010 13 5 cycles 011 28 5 cycles 100 41 5 cycles 101 55 5 cycles 110 71 5 cycles 111 239 5 cycles Bit 20 18 CSPT16 0x0 rw Sample time selection of channel ADC_IN16 000 1 5 cycles 001 7 5 cycles 010 13 5 cycles 011 28 5 cycles 100 41 5 cycles 101 55 5 cycles 110 71 5 cycles 111 239 5 cycles Bit 17 15 CSPT15 0x0 rw Sample time selection of channel...

Page 318: ...239 5 cycles Bit 2 0 CSPT10 0x0 rw Sample time selection of channel ADC_IN10 000 1 5 cycles 001 7 5 cycles 010 13 5 cycles 011 28 5 cycles 100 41 5 cycles 101 55 5 cycles 110 71 5 cycles 111 239 5 cycles 18 5 5 ADC sampling time register 2 ADC_SPT2 Accessible by words Bit Register Reset value Type Description Bit 31 30 Reserved 0x0 resd Kept at its default value Bit 29 27 CSPT9 0x0 rw Sample time ...

Page 319: ...0x0 rw Sample time selection of channel ADC_IN5 000 1 5 cycles 001 7 5 cycles 010 13 5 cycles 011 28 5 cycles 100 41 5 cycles 101 55 5 cycles 110 71 5 cycles 111 239 5 cycles Bit 14 12 CSPT4 0x0 rw Sample time selection of channel ADC_IN4 000 1 5 cycles 001 7 5 cycles 010 13 5 cycles 011 28 5 cycles 100 41 5 cycles 101 55 5 cycles 110 71 5 cycles 111 239 5 cycles Bit 11 9 CSPT3 0x0 rw Sample time ...

Page 320: ... x ADC_ PCDTOx x 1 4 Accessible by words Bit Register Reset value Type Description Bit 31 12 Reserved 0x00000 resd Kept at its default value Bit 11 0 PCDTOx 0x000 rw Data offset for Preempted channel x Converted data stored in the ADC_PDTx Raw converted data ADC_PCDTOx 18 5 7 ADC voltage monitor high threshold register ADC_VWHB Accessible by words Bit Register Reset value Type Description Bit 31 1...

Page 321: ...sequence Bit 24 20 OSN11 0x00 rw Number of 11th conversion in ordinary sequence Bit 19 15 OSN10 0x00 rw Number of 10th conversion in ordinary sequence Bit 14 10 OSN9 0x00 rw Number of 9th conversion in ordinary sequence Bit 9 5 OSN8 0x00 rw Number of 8th conversion in ordinary sequence Bit 4 0 OSN7 0x00 rw Number of 7th conversion in ordinary sequence Note The number can be from 0 to 17 For exampl...

Page 322: ...ber is set to 3 it refers to the ADC_IN3 channel If PCLEN is less than 4 the conversion sequence starts from 4 PCLEN For example when ADC_PSQ 21 0 10 00110 00101 00100 00011 it indicates that the scan conversion follows the sequence 4 5 6 not 3 4 5 18 5 13ADC preempted data register x ADC_ PDTx x 1 4 Accessible by words Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept ...

Page 323: ... ty selection Blanki ng Functi on CMPINVSEL CMPNINVSEL V2V VREFINT SCALEN BRG EN VREFINT44 VREFINT34 VREFINT24 VREFINT14 Blanki ng Source Select TM R1_OC4 TM R3_OC3 TM R15_OC2 TM R15_OC1 19 2Main features Programmable hysteresis level Timer output as comparator blanking source Programmable output polarity Programmable output speed Selectable positive negative input sources I O pins Internal refere...

Page 324: ...it is necessary to disable the digital filtering of the comparator setting GFE 0 of the G_FILTER_EN register 19 5Functional overview 19 5 1 Analog comparator Positive Negative input selection Select an I O or VSSA as a positive input source through the CMPxNINVSEL 1 0 bit in the CMP_CTRLSTS register Select an internal reference voltage three voltage divider values or an I O as a negative input sou...

Page 325: ...etected on the filter input Figure 19 2 and Figure 19 3 shows the timing diagram when the H_PULSE_CNT and L_PULSE_CNT are with different values Figure 19 2 Glitch filter timing when H_PULSE_CNT 1 and L_PULSE_CNT 0 2 consecutive samples PCLK input Filter output filter Figure 19 3 Glitch filter timing when H_PULSE_CNT 2 and L_PULSE_CNT 1 3 consecutive samples PCLK input Filter output filter 2 consec...

Page 326: ...ts default value Bit 20 18 CMPBLANKING 0x0 rw Comparator blanking source 000 No blanking output 001 TMR1 OC4 as a blanking window source 010 Reserved 011 TMR3 OC3 as a blanking window source 100 TMR15 OC2 as a blanking window source 101 Reserved 110 TMR15 OC1 as a blanking window source 111 Reserved Bit 17 16 CMPHYST 0x0 rw Comparator hysteresis 00 No hysteresis 01 Low hysteresis 10 Medium hystere...

Page 327: ... high impedance input such as the non inverting input of Comparator high impedance switch Bit 0 CMPEN 0x0 rw Comparator enable This bit enables or disables a comparator 0 Comparator disabled 1 Comparator enabled 19 6 2 Glitch filter enable register G_FILTER_EN Bit Register Reset value Type Description Bit 15 1 Reserved 0x0000 resd Kept at its default value Bit 0 GFE 0x0 rw Glitch filter enable 0 N...

Page 328: ...Type Description Bit 15 6 Reserved 0x000 resd Kept at its default value Bit 5 0 L_PULSE_CNT 0x0 rw Low pulse Count The level of the filter input signal must wait H_PULSE_CNT 1 cycles before becoming active input so that the output can turn low level 0 1 x pclk 1 2 x pclk cycles 2 3 x pclk cycles 62 63 x pclk cycles 63 64 x pclk cycles ...

Page 329: ...d off Thus there are some limitations on the use of GPIO pin which is shared with the OPA pin The OPx_INy can still be used as GPIO or its alternate function pin As OPA input setting this pin as analog mode is recommended Note that the input of such pin must be less than VDD 0 3V It is also advised to set the OPx_OUT pin in analog mode There are a variety of possibilities causing the pin to output...

Page 330: ...32F421 Series Reference Manual 2022 11 11 Page 330 Rev 2 02 Location relationship between device pins and OPA pins Pin name OPA pin PA0 OP1_INP PA1 OP1_INM PA2 OP1_OUT PA4 OP2_INP PA5 OP2_INM PA6 OP2_OUT ...

Page 331: ...ects from TMR16_C1OUT USART1 and USART2 through the IR_SRC_SEL 1 0 bit in the SCFG_CFG1 register while the high frequency carrier signal is provided by the TMR17_C1OUT register The IR_POL bit in the SCFG_CFG1 register controls whether the IR_OUT output is reversed or not The IR_OUT signal is output through multiplexed function via PB9 or PA13 multiplexed mode needs to be configured in advance Figu...

Page 332: ...K and FCLK to continue to work In Deepsleep mode HICK oscillator is enabled to feed FCLK and HCLK There are several ID codes inside the MCU which is accessible by the debugger using the DEBUG_IDCODE at address 0xE0042000 It is part of the DEBUG and is mapped on the external PPB bus These codes are accessible by the SW debug port or by the user software They are even accessible while the MCU is und...

Page 333: ... 64KB LQFP32 0x50020102 AT32F421K8U7 64KB QFN32 5x5 0x50020103 AT32F421K8U7 4 64KB QFN32 4x4 0x50020104 AT32F421F8U7 64KB QFN20 0x50020105 AT32F421F8P7 64KB TSSOP20 0x50020086 AT32F421C6T7 32KB LQFP48 0x50020087 AT32F421K6T7 32KB LQFP32 0x50020088 AT32F421K6U7 32KB QFN32 5x5 0x50020089 AT32F421K6U7 4 32KB QFN32 4x4 0x5002008A AT32F421F6U7 32KB QFN20 0x5002008B AT32F421F6P7 32KB TSSOP20 0x5001000C ...

Page 334: ...MR6_PAUSE 0x0 rw TMR6 pause control bit 0 Work normally 1 Timer is disabled Bit 18 17 Reserved 0x0 resd Kept at its default value Bit 16 I2C2_SMBUS_TIMEOUT 0x0 rw I2C2 pause control bit 0 Work normally 1 I2C2 SMBUS timeout control is disabled Bit 15 I2C1_SMBUS_TIMEOUT 0x0 rw I2C1 pause control bit 0 Work normally 1 I2C1 SMBUS timeout control is disabled Bit 14 ERTC_PAUSE 0x0 rw ERTC pause control ...

Page 335: ...s the system clock source and the software must reprogram the system clock according to application requirements 1 In Deepsleep mode system clock is provided by the internal RC oscillator HICK When exiting from Deepsleep mode HICK is used as the system clock source and the software must reprogram the system clock according to application requirements Bit 0 SLEEP_DEBUG 0x0 rw Debug Sleep mode contr...

Page 336: ...iptions in 3 6 Power saving modes 3 Updated the descriptions in 4 3 2 Clock configuration register CRM_CFG 4 Updated the descriptions in 11 5 1 Control register1 I2C_CTRL1 5 Updated 13 Serial peripheral interface SPI 6 Updated the descriptions in 18 5 3 ADC control register2 ADC_CTRL2 2022 11 11 2 02 1 Updated descriptions of Section 5 8 1 2 Updated descriptions of Chapter 10 3 Updated description...

Page 337: ...ing legal situation in any injudical districts or infringement of any patent copyright or other intellectual property right ARTERY s products are not designed for the following purposes and thus not intended for the following uses A Applications that have specific requirements on safety for example life support applications active implant devices or systems that have specific requirements on produ...

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