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dc1762afb
DEMO MANUAL DC1762A
Quick start proceDure
Applying Power and Signals to the DC1762A
Demonstration Circuit
If a DC890 is used to acquire data from the DC1762A,
the DC890 must FIRST be connected to a powered USB
port or provided an external 6V to 9V BEFORE applying
4.5V to 6V across the pins marked V
+
and GND on the
DC1762A. DC1762A requires 4.5V for proper operation.
Regulators on the board produce the voltages required for
the ADC. The DC1762A demonstration circuit requires up
to 500mA depending on the sampling rate and the A/D
converter supplied.
The DC890 data collection board is powered by the USB
cable and does require an external power supply when
collecting data from and LVDS demo board. It must be
supplied an external 6V to 9V on turrets G7(+) and G1(–)
or the adjacent 2.1mm power jack.
Analog Input Network
For optimal distortion and noise performance the RC net-
work on the analog inputs may need to be optimized for
different analog input frequencies. For input frequencies
above 140MHz, refer to the respective ADC data sheet
for a proper input network. Other input networks may be
more appropriate for input frequencies less than 5MHz,
or above 140MHz.
In almost all cases, filters will be required on both analog
input and encode clock to provide data sheet SNR. In the
case of the DC1762A, a bandpass filter used for the clock
should be used prior to the DC1075 clock divider board.
The filters should be located close to the inputs to avoid
reflections from impedance discontinuities at the driven
end of a long transmission line. Most filters do not present
50Ω outside the passband. In some cases, 3dB to 10dB
pads may be required to obtain low distortion.
If your generator cannot deliver full-scale signals without
distortion, you may benefit from a medium power amplifier
based on a Gallium Arsenide Gain block prior to the final
filter. This is particularly true at higher frequencies where
IC based operational amplifiers may be unable to deliver
the combination of low noise figure and High IP3 point
required. A high order filter can be used prior to this final
amplifier, and a relatively lower Q filter used between the
amplifier and the demo circuit.
Apply the analog input signal of interest to the SMA
connector on the DC1762A demonstration circuit board
marked J5 AIN
+
. This input is capacitively coupled to a
Balun transformer ETC1-1-13 (lead free part number:
MABA007159-000000).
Encode Clock
NOTE: Apply an encode clock to the SMA connector on
the DC1762A demonstration circuit board marked J3
ENC
+
. As a default the DC1762A is populated to have a
single-ended input.
For the best noise performance, the encode input must
be driven with a very low jitter, square wave source. The
amplitude should be large, up to 3V
P-P
or 13dBm. When
using a sinusoidal signal generator a squaring circuit can
be used. Linear Technology also provides demo board
DC1075 that divides a high frequency sine wave by four,
producing a low jitter square wave for best results with
the LTC2165.
Using bandpass filters on the clock and the analog input will
improve the noise performance by reducing the wideband
noise power of the signals. In the case of the DC1762A a
bandpass filter used for the clock should be used prior to
the DC1075. Datasheet FFT plots are taken with 10 pole LC
filters made by TTE (Los Angeles, CA) to suppress signal
generator harmonics, non-harmonically related spurs and
broadband noise. Low phase noise Agilent 8644B genera-
tors are used with TTE bandpass filters for both the clock
input and the analog input.
An internally generated conversion clock output is available
on J1 which could be collected via a logic analyzer, or other
data collection system if populated with a SAMTEC MEC8-
150 type connector or collected by the DC890 QuikEval-II
Data Acquisition Board using PScope™ software.
