Arrow Central Europe GmbH
page 13
User Guide
Everest-CortexM1-Demo
3.3
Design Implementation
The following table lists the clock frequencies used in the design.
Table 2: Hardware Design Clock Frequencies
Clock
Frequency (MHz)
PF_OSC
160
PF_CCC OUT0_FABCLK
27.5
HCLK / PCLK
27.5
PF_TX_PLL
156.25
DIV_CLK
125
The top-level design implementation for Everest DEV Board PROTO is shown in Figure 4.
Figure 4: Design Implementation
– Top Level Everest DEV Board PROTO
The top-level design implementation for Everest DEV Board Rev. A and B has an extra
CoreGPIO called
SFP_CTRL
that receives the signal
SFP_MOD
,
SFP_TX_FAULT
and
SFP_RX_LOS,
including interrupt generation for those signal, and drives the signals
SFP_TX_DIS
,
SFP_RS0
and
SFP_RS1
.
