Controladores lógicos programables PLC baja gama expandibles entradas digitales AC 74368-SR22MRDC ARRAY Manual Ingles www.viaindustrial.com
Controladores lógicos programables PLC baja gama expandibles entradas digitales AC 74368-SR22MRDC ARRAY Manual Ingles www.viaindustrial.com
Logical frame of AND:
I1 I2 I3 I4 Q
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
3.1.2 AND with RLO Borderline Test
In SR, the symbol is as shown in follows:
Only when all the statuses of the inputs are 1 and at least the status of one input is 0 in
the last period, the output status of AND with RLO borderline test is 1.
If the input line of this function block (X) is unconnected, then this input is X=1.
The time diagram of AND with RLO borderline test is as shown in follows:
During the third period, all the statuses of the inputs are 1 and during the second
period, the status of I2 is 0, so the status of the output is 1.
While during the fourth period, all the status of the inputs are 1 but during the third
period, all the status of the inputs are 1, so the status of the output is 0.
