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Signals and Pinouts

ARM DUI 0188C

A-5

Table A-3 lists the signals on the HDRZ connector and the associated prototyping and
peripheral signal.

Table A-3 HDRZ signals

Generic Tile signal

Prototyping
pad

Interface Tile signal

Effect of peripheral
enable switches (and
other control signals)

SPARE[12:4]

T9-T1

SPARE[12:4]

SPARE[3:0]

S12-S9

SPARE[3:0]

C_TDO_OUT

C_TDO_IN

C_TDO_OUT

C_TDO_IN

(to use JTAG, remove
resistor R1 on J1 to remove
short)

C_TDI

C_TDO_IN

C_TDI

C_TDO_IN

(connected if

nTILE_DET

is HIGH)

C_TCK

B_C_TCK

C_TMS

D_TDI

D_TDO

D_TDI

D_TDO

(connected if

nTILE_DET

is HIGH)

D_TCK

D_RTCK

D_TCK

D_RTCK

(connected if

nTILE_DET

is HIGH)

CLK_GLOBAL

X17 (out)
X20 (in)
X16 (enable)

CLK_GLOBAL_OUT

CLK_GLOBAL_IN

(Interface tile generates
global clock if

CLK_GLOBAL_nEN

prototyping area is pulled
LOW)

CLK_POS_UP_OUT

X21

CLK_POS_UP_IN
EXT_CLK_POS_UP_IN

(default)
(selected by LK2)

CLK_POS_UP_IN

X18

CLK_POS_UP_OUT

CLK_POS_DN_IN

X19

CLK_POS_DN_OUT

X22

CLK_POS_DN_IN
EXT_CLK_POS_DN_IN

(default)
(selected by LK1)

Z[127:0]

Z128

DAC_CLK

Z129

DAC_DIN

Summary of Contents for Versatile/IT1

Page 2: ... ARM in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information...

Page 3: ...About the Interface Tile 1 2 1 2 Precautions 1 6 Chapter 2 Getting Started 2 1 Fitting the Interface Tile to a logic tile 2 2 2 2 Setting the peripheral enable switches 2 3 Appendix A Signals and Pinouts A 1 Connector signals A 2 A 2 User LEDs and switches A 19 A 3 Clock signals A 20 A 4 Prototyping pads A 21 Appendix B Specifications B 1 Electrical specification B 2 B 2 Mechanical details B 3 ...

Page 5: ...le IT1 User Guide Change History ii Table 2 1 Peripheral enable switch function 2 3 Table A 1 HDRX signals A 3 Table A 2 HDRY signals A 3 Table A 3 HDRZ signals A 5 Table A 4 Prototyping pad signals A 22 Table B 1 Electrical characteristics for 3 3V I O B 2 Table B 2 Current requirements B 2 ...

Page 7: ...r connector voltages A 2 Figure A 2 UART block diagram A 9 Figure A 3 UART connector J9 A 9 Figure A 4 Stepper block diagram A 10 Figure A 5 Stepper connector J8 A 10 Figure A 6 Camera connector J7 A 11 Figure A 7 CAN block diagram A 12 Figure A 8 CAN connector J4 A 12 Figure A 9 ADC DAC block diagram A 13 Figure A 10 ADC DAC connector J2 A 13 Figure A 11 IDE block diagram A 14 Figure A 12 IDE con...

Page 8: ...f Figures viii Copyright 2004 2007 ARM Limited All rights reserved ARM DUI 0188C Figure A 19 Clock signals A 20 Figure A 20 Prototyping pad locations A 21 Figure B 1 Location of headers and mounting holes B 3 ...

Page 9: ... All rights reserved ix Preface This preface introduces the ARM Versatile IT1 Interface Tile and associated reference documentation It contains the following sections About this document on page x Further reading on page xii Feedback on page xiii ...

Page 10: ...ation This document is organized into the following chapters Chapter 1 Introduction Read this chapter for an introduction to the Interface Tile This chapter shows the physical layout of the Interface Tile and identifies the main components Chapter 2 Getting Started Read this chapter for a description of how to set up and start using the Interface Tile This chapter describes how to connect the Inte...

Page 11: ...ption The underlined text can be entered instead of the full command or option name monospace italic Denotes arguments to commands and functions where the argument is to be replaced by a specific value italic Highlights important notes introduces special terminology denotes internal cross references and citations bold Highlights interface elements such as menu names and buttons Also used for terms...

Page 12: ...048 RealView ICE User Guide ARM DUI 0155 Trace Debug Tools User Guide ARM DUI 0118 ARM MultiTrace User Guide ARM DUI 0150 RealView LT XC2V4000 Logic Tile User Guide ARM DUI 0186 Versatile Platform Baseboard for ARM926EJ S User Guide ARM DUI 0224 ARM Integrator Compact Platform User Guide ARM DUI 0159 RealView Debugger User Guide ARM DUI 0153 RealView Compilation Tools Compilers and Libraries Guide...

Page 13: ...about this document please send email to errata arm com giving the document title the document number the page number s to which your comments refer an explanation of your comments General suggestions for additions and improvements are also welcome Feedback on the Interface Tile If you have any comments or suggestions about this product please contact your supplier giving the product name an expla...

Page 15: ...Copyright 2004 2007 ARM Limited All rights reserved 1 1 Chapter 1 Introduction This chapter introduces the Interface Tile It contains the following section About the Interface Tile on page 1 2 Precautions on page 1 6 ...

Page 16: ...erating at up to 200kHz four channel 12 bit DAC operating at up to 125kHz two CAN bus drivers USB host and OTG transceivers two I2C interfaces camera interface two stepper motor interfaces RS232 transceiver IDE interface clock buffers JTAG interface 513 pin prototyping area with 272 I O pins Figure 1 1 shows an example configuration that uses an Interface Tile Figure 1 1 Interface Tile mounted on ...

Page 17: ...ited All rights reserved 1 3 Figure 1 2 Interface Tile mounted on Logic Tile and Versatile PB926EJ S Figure 1 3 on page 1 4 shows a simplified view of the interfaces on the tile the JTAG tile detect clock and peripheral enable logic are not shown in detail ...

Page 18: ...U3 DAC DAC and ADC J2 16 way IDC U5 ADC U8 CAN1 CAN 1 and 2 J4 10 way IDC U10 CAN2 Z 139 138 JTAG I2C 1 I2C 2 J1 20 way IDC U9 USB host J3 USBA U11 USB OTG J5 OTG Camera J7 20 way IDC Z 159 156 U15 STEP1 Stepper 1 and 2 J8 14 way IDC U17 STEP2 U16 UART J9 10 way IDC U12 U13 IDE J6 40 way IDC Y 68 61 User Switch S2 8 1 Y 76 69 User LEDs D 8 1 Enable switch S1 8 1 Peripheral enable logic DAC ADC CAN...

Page 20: ...nt It is supplied without an enclosure and this leaves the board sensitive to electrostatic discharges and allows electromagnetic emissions Caution To avoid damage to the board when it has logic devices mounted observe the following precautions never subject the board to high electrostatic potentials always wear a grounding strap when handling the board only hold the board by the edges avoid touch...

Page 21: ...s reserved 2 1 Chapter 2 Getting Started This chapter describes how to set up and prepare the Interface Tile for use It contains the following sections Fitting the Interface Tile to a logic tile on page 2 2 Setting the peripheral enable switches on page 2 3 ...

Page 22: ...n Integrator IM LT1 module to the Integrator CP baseboard 2 Fit one or more Logic Tiles to the IM LT1 module 3 Fit the Interface Tile on top of the Logic Tile 4 Connect the cables for your peripheral to the Interface Tile connectors 5 Set the peripheral enable switches to enable the drivers that are being used Note There are many other possible combinations of Interface Tile Core Tile Analyzer Til...

Page 23: ...move the camera module from the Interface Tile to isolate the camera signals from the tile signals Table 2 1 Peripheral enable switch function Switch Peripheral Isolated peripheral signals Logic Tile signals S1 1 DAC DAC_nCS Z 130 128 S1 2 ADC ADC_nCS Z 135 131 S1 3 CAN 1 CAN1_RxD Z 137 136 S1 4 CAN 2 CAN2_RxD Z 139 138 S1 5 UART UART_TxD UART_RxD UART_nRTS UART_nDTR UART_nCTS UART_nDSR UART_nDCD ...

Page 25: ...d A 1 Appendix A Signals and Pinouts This index provides a summary of signals present on the Interface Tile It contains the following sections Connector signals on page A 2 User LEDs and switches on page A 19 Clock signals on page A 20 Prototyping pads on page A 21 ...

Page 26: ...nectors are mounted on the bottom of the Interface Tile Note All signals from the lower headers are routed straight through to the upper headers The path of some clock signals however can be broken and alternative clocks used see Clock signals on page A 20 Signals not listed in the tables are not connected to the prototyping area or peripheral connectors Even signals are on one connector row and o...

Page 27: ...ing and peripheral signal Table A 1 HDRX signals Generic tile signal name Prototyping pad X 11 0 G12 1 X 23 12 H12 1 X 35 24 J12 1 X 47 36 K12 1 X 59 48 M12 1 X 71 60 N12 1 X 83 72 P12 1 X 95 84 Q12 1 X 103 96 S8 1 X 115 104 AB12 1 X 127 116 AC12 1 X 135 128 AB22 15 X 143 136 AC22 15 Table A 2 HDRY signals Generic tile signal Prototyping pad Interface Tile signal Effect of peripheral enable switch...

Page 28: ...Y28 IDE_nIOCS16 Y29 IDE_PASSDIAG Y30 IDE_nACTIVE Y 33 31 IDE_BDIR 2 0 Y 36 34 IDE_nBOE 2 0 isolated by SW8 Y 68 61 LED 7 0 Y 76 69 SW 7 0 Y 79 77 T12 T10 Y 89 80 V10 V1 Y 91 90 V12 V11 Y 103 92 W12 W1 Y 115 104 Y12 Y1 Y 127 116 Z12 Z1 Y 135 128 Y22 Y15 Y 143 136 Z22 Z15 Table A 2 HDRY signals continued Generic tile signal Prototyping pad Interface Tile signal Effect of peripheral enable switches ...

Page 29: ...ve resistor R1 on J1 to remove short C_TDI C_TDO_IN C_TDI C_TDO_IN connected if nTILE_DET is HIGH C_TCK B_C_TCK C_TMS C_TMS D_TDI D_TDO D_TDI D_TDO connected if nTILE_DET is HIGH D_TCK D_RTCK D_TCK D_RTCK connected if nTILE_DET is HIGH CLK_GLOBAL X17 out X20 in X16 enable CLK_GLOBAL_OUT CLK_GLOBAL_IN Interface tile generates global clock if CLK_GLOBAL_nEN on prototyping area is pulled LOW CLK_POS_...

Page 30: ...Z141 B2 UART_RxD isolated by buffer SW5 Z142 B3 UART_nRTS isolated by buffer SW5 Z143 B4 UART_nDTR isolated by buffer SW5 Z144 B5 UART_nCTS isolated by buffer SW5 Z145 B6 UART_nDSR isolated by buffer SW5 Z146 B7 UART_nDCD isolated by buffer SW5 Z147 B8 UART_nRI isolated by buffer SW5 Z 151 148 B12 B9 Z152 D1 STEPPER1_IN 1 Z153 D2 STEPPER1_IN 2 Z154 D3 STEPPER1_IN 3 Z155 D4 STEPPER1_IN 4 Z156 D5 ST...

Page 31: ..._HSYNC Z187 CAM_YSYNC Z188 CAM_CLK Z189 CAM_STANDBY Z194 CAM_nRESET Z 202 195 I2C_D 7 0 Z203 I2C_nRST isolated by SW6 Z 205 204 I2C_A 1 0 Z206 I2C1_nCS isolated by SW6 Z207 I2C2_nCS isolated by SW6 Z208 I2C_nRD Z209 I2C_nWR Z210 I2C1_nINT isolated by SW6 Z211 I2C2_nINT isolated by SW6 Z212 USB1_MODE Table A 3 HDRZ signals continued Generic Tile signal Prototyping pad Interface Tile signal Effect o...

Page 32: ..._VMO Z216 USB1_VPO Z217 USB1_SPEED Z218 USB1_RCV isolated by SW7 Z219 USB1_VP isolated by SW7 Z220 USB1_VM isolated by SW7 Z221 USB2_nOE Z222 USB2_SUSPEND Z223 USB2_SPEED Z224 USB2_SCL Z225 USB2_SDA Z226 USB2_nRST isolated by SW7 Z227 USB2_nINT Z228 USB2_VP Z229 USB2_VM Z230 USB2_RCV isolated by SW7 Z 255 231 Table A 3 HDRZ signals continued Generic Tile signal Prototyping pad Interface Tile signa...

Page 33: ... A 5 on page A 10 shows the stepper connector B_Z 140 UART_TXD B_Z 142 UART_nRTS B_Z 146 UART_nDCD B_Z 145 UART_nDSR B_Z 147 UART_nRI B_Z 141 UART_RXD HDRZ B_Z 143 UART_nDTR MAX3243E U16 SER_TXD SER_nRTS SER_nDTR SER_RXD SER_nDCD SER_nDSR SER_nCTS B_Z 144 UART_nCTS SER_nRI Z140 Z142 Z146 Z145 Z147 Z141 Z143 Z144 S1 4 3 3V Prototyping pads SER_CTS SER_RX SER_TX SER_RI SER_DCD SER_DSR SER_RTS SCR_DT...

Page 34: ...the tile signals remove the camera from the socket STEP1_K12 Z152 STEP1_IN1 Z153 STEP1_IN2 Z154 STEP1_IN3 STEP1_K34 STEP1_OUT1 Z157 STEP2_IN2 Z158 STEP2_IN3 Z159 STEP2_IN4 Z156 STEP2_IN1 HDRZ UDN2559LB U15 Z155 STEP1_IN4 UDN2559LB U17 STEP1_OUT2 STEP1_OUT3 STEP1_OUT4 SGND STEP2_K12 STEP2_K34 STEP2_OUT1 STEP2_OUT2 STEP2_OUT3 STEP2_OUT4 SGND Prototyping pads STEP1_K12 STEP1_OUT4 STEP1_K34 SGND STEP1...

Page 35: ...igure A 7 on page A 12 shows the CAN block diagram and Figure A 8 on page A 12 shows the CAN connector CAM_D0 1 2 20 19 GND CAM_D1 CAM_D2 CAM_D3 CAM_D4 CAM_D5 CAM_D6 CAM_D7 3V3 CAM_SCL CAM_SDA 3V3 CAM_HSYNC CAM_VSYNC GND CAM_CLK GND CAM_nRESET CAM_STANDBY HDRZ Z176 Z177 Z178 Z179 Z180 Z181 Z182 Z183 Z184 Z185 Z186 Z187 Z188 Z194 Z189 ...

Page 36: ...r J4 A 1 6 ADC and DAC Figure A 9 on page A 13 shows the ADC DAC block diagram and Figure A 10 on page A 13 shows the ADC DAC connector HDRZ CAN1_H CAN1_L Z136 CAN1_TXD Z138 CAN2_TXD Z137 CAN1_RXD Z139 CAN2_RXD CAN2_H CAN2_L 120R 120R TJA1050 U8 TJA1050 U10 S1 3 S1 4 Prototyping pads GND CAN1_L GND GND CAN1_H GND GND CAN2_H 1 2 10 9 GND CAN2_L ...

Page 37: ...A 15 shows the IDE connector Z133 ADC_DOUT HDRZ Z134 ADC_BUSY DAC_CH 3 0 Regulator AVCC VREF AVCC VREF Analog to digital ADS7844E U3 Z131 ADC_DATA ADC_nCS Z135 ADC_CLK ADC_CH 7 0 Digital to analog AD5324 U5 Z129 DAC_DATA DAC_nCS Z128 DAC_CLK 5V 2 5V Regulator ZRC250 AGND AGND AGND 3V3 Input filter Z130 Z132 S1 2 S1 1 Prototyping pads 3V3 3V3 0 to 2 5V 0 to 2 5V 330R ADC_CH1 VREF ADC_CH0 3V3 AGND A...

Page 38: ...VCH 164245 U12 B_IDE 15 0 Y 21 19 IDE_DA 2 0 B_IDE_nIOR B_IDE_DMAACK B_IDE_CS 1 0 B_IDE_nIOW B_IDE_DA 2 0 IDE_nBOE1 Y32 IDE_BDIR1 Y26 IDE_IORDY Y27 IDE_IRQR Y25 IDE_DMAR Y29 IDE_PASSDIAG Y30 IDE_nACTIVE Y28 IDE_nIOCS16 IDE_nBOE2 Y33 IDE_BDIR2 B_IDE_DMAR B_IDE_IORDY B_IDE_PASSDIAG B_IDE_IRQR B_IDE_nIOCS16 B_IDE_nACTIVE P174ALVCH 164245 U13 B_IDE_nRST Y24_IDE_RST 2K2 3 3V 5V 3 3V 5V S1 8 Y34 Y35 Y36...

Page 39: ...rs are shown and Figure A 14 on page A 16 shows the host and OTG USB connectors 1 2 40 39 GND GND B_IDED8 B_IDEnRST B_IDED7 B_IDED9 B_IDED10 B_IDED11 B_IDED12 B_IDED13 B_IDED14 B_IDED15 NC SP_SYNC GND B_IDEnIOCS16 B_IDEOASSDUAG B_IDEDA2 B_IDEbCS1 GND GND GND GND B_IDED6 B_IDED5 B_IDED4 B_IDED3 B_IDED2 B_IDED1 B_IDED0 B_IDEDMAR B_IDEnIOW B_IDEnIOR B_IDEIORDY B_IDEDMAACK B_IDEIRQR B_IDEA1 B_IDEA2 B_...

Page 40: ...am Z212 USB1_MODE Z213 Z217 USB1_SPEED Z218 Z214 USB1_SUSPEND PD1USBP11AD U9 USB2_DATAM USB2_DAMAP HDRZ ISP1301 U11 Z215 USB1_VMO Z216 USB1_VPO Z219 Z221 USB2_nOE Z230 Z228 USB2_VP Z222 USB2_SUSPEND Z224 USB2_SCL Z223 USB2_SPEED Z229 USB2_VM Z225 USB2_SDA Z226 Z227 USB2_nINT USB2_ID USB1PWR USB1GND USB2PWR USB2GND USB1_DATAP USB1_DATAM USB1_nOE USB1_RCV USB1_VP S1 7 USB2_RCV USB2_nRST Z220 USB1_VM...

Page 41: ...18 shows the JTAG logic Note Remove resistor R1 to use the JTAG connector on the Interface tile Z206 I2C1_nCS Z208 I2C_nRD Z203 I2C_nRST Z 202 195 I2C_D 7 0 Z209 I2C_nWR PCA9564PW U4 HDRZ PCA9564PW U6 Z210 I2C1_nINT Z 205 204 I2C_A 1 0 I2C1_SDA I2C1_SCL 3 3V I2C2_SDA I2C2_SCL 3 3V 10K 10K Z207 I2C2_nCS Z211 I2C2_nINT 3 3V S1 6 3V3 3V3 3V3 3V3 ...

Page 42: ...ws the I2C and JTAG connector Figure A 17 I2C and JTAG connector J1 HDRZ upper nTILE_DET C_TDI D_TDI D_TCK D_RTCK D_TDO C_TDO_IN C_TMS C_TMS B_C_TCK C_TDO_IN C_TCK C_TDO_OUT HDRZ lower R1 0R link 3 3V C_TDO_OUT nTILE_DET GND C_TMS B_C_TCK GND 3V3 GND GND C_TDO_IN 1 2 16 15 GND GND I2C2_SDA I2C2_SCL 3V3 I2C1_SDA C_TDO_OUT I2C2_SCL ...

Page 43: ...s ARM DUI 0188C Copyright 2004 2007 ARM Limited All rights reserved A 19 A 2 User LEDs and switches Figure A 18 shows the signals for the user LEDs and switches Figure A 18 User switch and LED signals 5 9 6 6 6 6 6 6 6 6 ...

Page 44: ...DRZ headers and the clock selection links Figure A 19 Clock signals HDRZ upper pin 150 CLK_GLOBAL pin 130 CLK_POS_DN_IN pin 134 CLK_POS_UP_OUT EXT_CLK_POS_UP_IN HDRZ lower 33R 3 3V EXT_CLK_POS_DN_IN pin 134 CLK_POS_UP_IN pin130 CLK_POS_DN_OUT A B C A B C LK2 LK1 CLK_GLOBAL_OUT CLK_GLOBAL_nEN CLK_GLOBAL_IN 33R pin150 CLK_GLOBAL R_CLK_POS_UP_OUT 33R R_CLK_POS_DN_OUT 33R ...

Page 45: ...3 G 164 165 166 167 168 169 170 171 172 173 174 G 3V3 5V 175 G G G G G G G G G G G G G G G 0 1 2 3 4 5 6 7 8 9 10 G 3V3 VX 11 G 12 13 14 15 16 17 18 19 20 21 22 G 3V3 VX 23 G G G G G G G G G G G G G G G 24 25 26 27 28 29 30 31 32 33 34 G 3V3 35 G 36 37 38 39 40 41 42 43 44 45 46 G 3V3 47 G G G G G G G G G G G G G G G 48 49 50 51 52 53 54 55 56 57 58 G 3V3 59 G 60 61 62 63 64 65 66 67 68 69 70 G 3V...

Page 46: ... DUI 0188C Table A 4 Prototyping pad signals Pad hole ref Signal A15 5V A14 3V3 A13 GND A12 1 Z 139 128 A0 GND B15 5V B14 3V3 BA13 GND B12 1 Z 151 140 B0 GND C15 5V C14 3V3 C13 0 GND D15 5V D14 3V3 D13 GND D12 1 Z 163 152 D0 GND E15 5V E14 3V3 E13 GND E12 1 Z 175 164 E0 GND F15 5V ...

Page 47: ...4 3V3 F13 0 GND G15 VCCOX G14 3V3 G13 GND G12 1 X 11 0 G0 GND H15 VCCOX H14 3V3 H13 GND H12 1 X 23 12 H0 GND I15 VCCOX I14 3V3 I13 0 GND J15 VCCOX J14 3V3 J13 GND J12 1 X 35 24 J0 GND K15 VCCOX K14 3V3 K13 GND K12 1 X 47 36 K0 GND Table A 4 Prototyping pad signals continued Pad hole ref Signal ...

Page 48: ...VCCOX L14 3V3 L13 0 GND M15 VCCOX M14 3V3 M13 GND M12 1 X 59 48 M0 GND N15 VCCOX N14 3V3 N13 GND N12 1 X 71 60 N0 GND O15 VCCOX O14 3V3 O13 9 GND P15 VCCOX P14 3V3 P13 GND P12 1 X 83 72 P0 GND Q15 VCCOX Q14 3V3 Q13 GND Q12 1 X 95 84 Table A 4 Prototyping pad signals continued Pad hole ref Signal ...

Page 49: ...15 VCCOX R14 3V3 R13 0 GND S15 VCCOY S14 3V3 S13 GND S12 9 SPARE 3 0 S8 1 X 103 96 S0 GND T15 VCCOY T14 3V3 T13 GND T12 10 Y 79 77 T9 1 SPARE 12 4 T0 GND U15 VCCOY U14 3V3 U13 0 GND V15 5V V14 3V3 V13 GND V12 1 Y 91 80 V0 GND W22 16 GND Table A 4 Prototyping pad signals continued Pad hole ref Signal ...

Page 50: ...2 EXT_CLK_POS_DN_IN X21 EXT_CLK_POS_UP_IN X20 CLK_GLOBAL_IN X19 B_CLK_POS_DN_OUT X18 B_CLK_POS_UP_OUT X17 CLK_GLOBAL_OUT X16 CLK_GLOBAL_nEN X15 5V X14 3V3 X13 0 GND Y22 15 Y 135 128 Y14 3V3 Y13 GND Y12 1 Y 115 104 Y0 GND Z22 15 Y 143 136 Z14 3V3 Z13 GND Z12 1 Y 127 116 Z0 GND Table A 4 Prototyping pad signals continued Pad hole ref Signal ...

Page 51: ... ARM Limited All rights reserved A 27 AA22 15 GND AA14 3V3 AA13 0 GND AB22 15 X 135 128 AB14 3V3 AB13 GND AB12 1 X 115 104 AB0 GND AC22 15 X 143 136 AC14 3V3 AC13 GND AC12 1 X 127 116 AC0 GND Table A 4 Prototyping pad signals continued Pad hole ref Signal ...

Page 53: ...d All rights reserved B 1 Appendix B Specifications This appendix describes the mechanical and electrical specifications for the Interface Tile It contains the following sections Electrical specification on page B 2 Mechanical details on page B 3 ...

Page 54: ... details on FPGA I O B 1 2 Current requirements Table B 2 shows the current requirements at room temperature and nominal voltage for an Interface Tile with all interfaces active Note The driver output pins for the stepper motor can each sink 500ma at up to 25V supply The stepper motor voltage must be supplied by an external power supply Table B 1 Electrical characteristics for 3 3V I O Symbol Desc...

Page 55: ...ll rights reserved B 3 B 2 Mechanical details The Interface Tile is designed to be stackable on Logic Tiles or Core Tiles Figure B 1 shows the mechanical outline and location of the tile headers and mounting holes Figure B 1 Location of headers and mounting holes ...

Page 57: ... 10 CAN A 11 IDE A 13 Interface Tile 1 3 I2C A 16 JTAG A 17 LEDS A 19 stepper A 9 UART A 8 USB A 15 user switches A 19 C Camera A 10 CAN A 11 Clocks prototyping area A 21 signals A 20 Configuration switches 2 3 Connectors ADC DAC A 12 camera A 10 CAN A 11 header A 2 IDE A 13 I2C A 16 JTAG A 17 stepper A 9 UART A 8 USB A 15 D DAC A 12 E Electrical characteristics B 2 I IDE A 13 Installation Integra...

Page 58: ...ation 2 2 P Peripheral enable switches 2 3 Prototyping area A 21 S Signals ADC DAC A 12 camera A 10 CAN A 11 clock A 20 header A 3 A 5 IDE A 13 I2C A 16 JTAG A 17 LEDS A 19 prototyping A 21 stepper A 9 UART A 8 USB A 15 user switches A 19 Specification layout 1 4 Stepper A 9 Switches configuration 2 3 user A 19 U UART A 8 USB A 15 V VPB 926EJ S 1 2 ...

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