ARM V2M-Juno r2 Technical Reference Manual Download Page 133

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A.9

PCI Express expansion slots

The V2M-Juno r2 motherboard provides several PCIe slots that connect to the on-board switch.

This section contains the following subsections:
•

A.9.1 PCI Express ×4 connectors, one-lane slot 0 and slot 1

on page Appx-A-133

•

A.9.2 PCI Express ×8 connector, four-lane slot 2

on page Appx-A-135

•

A.9.3 PCI Express ×16 connector, four-lane slot 3

on page Appx-A-137

A.9.1

PCI Express ×4 connectors, one-lane slot 0 and slot 1

The V2M-Juno r2 motherboard provides two PCIe ×4 connectors that each provide one lane. The board
uses one lane on each connector and does not use the other six lanes.

Note

The PCIe I/O voltage at the connectors is 3.3V.

The following figure shows the PCIe ×4 connectors, one-lane slots 0 and 1, connectors J10 and J11.

Pin B1

Pin B32

Pin A32

Pin A1

Figure A-9 PCIe ×4 connector, one-lane slots 0 and 1, connectors J10 and J11

The following table shows the pin mapping for the one-lane PCI ×4 connector, one-lane slot 0, that is,
connector J11.

Table A-5 PCIe one-lane slot 0, connector J11, signal list

Pin Signal

12V

GND

12V

GND

No connection

PCIE_LOOP4

GND

PCIE_LOOP4

3V3

No connection

3V3

B10

3V3

A10

3V3

B11

PCIE_nWAKE0

A11

PCIE_nPERST5

B12 No connection

A12

GND

B13

GND

A13

PCIE_CLKP8

B14

PCIE_PETP2

A14

PCIE_CLKN8

B15

PCIE_PETN2

A15

GND

B16

GND

A16

PCIE_PERP2

A Signal Descriptions

A.9 PCI Express expansion slots

ARM 100114_0200_03_en

Appx-A-133

Non-Confidential

Summary of Contents for V2M-Juno r2

Page 2: ...WILL ARM BE LIABLE FOR ANY DAMAGES INCLUDING WITHOUT LIMITATION ANY DIRECT INDIRECT SPECIAL INCIDENTAL PUNITIVE OR CONSEQUENTIAL DAMAGES HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY ARISING OUT OF ANY USE OF THIS DOCUMENT EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES This document consists solely of commercial items You shall be responsible for ensuring that any use d...

Page 3: ...s uses and can radiate radio frequency energy and may cause harmful interference to radio communications There is no guarantee that interference will not occur in a particular installation If this equipment causes harmful interference to radio or television reception which can be determined by turning the equipment off or on you are encouraged to try to correct the interference by one or more of t...

Page 4: ...15 1 4 Connectors on front and rear panels 1 16 Chapter 2 Hardware Description 2 1 Overview of V2M Juno r2 motherboard hardware 2 18 2 2 Juno r2 ARM Development Platform SoC 2 22 2 3 External power 2 25 2 4 Power management and temperature protection 2 26 2 5 Clocks 2 28 2 6 Resets 2 35 2 7 Thin Links 2 38 2 8 IOFPGA 2 42 2 9 HDLCD interface 2 45 2 10 Interrupts 2 47 2 11 USB 2 0 interface 2 50 AR...

Page 5: ...y meter registers 4 107 Appendix A Signal Descriptions A 1 Debug connectors Appx A 122 A 2 Configuration 10Mbps Ethernet and dual USB connector Appx A 126 A 3 PCI Express Gigabit Ethernet and dual USB connector Appx A 127 A 4 SMC 10 100 Ethernet connector Appx A 128 A 5 Configuration USB connector Appx A 129 A 6 Header connectors Appx A 130 A 7 Keyboard and Mouse Interface KMI connector Appx A 131...

Page 6: ...ress Juno r2 Development Platform V2M Juno r2 Technical Reference Manual It contains the following About this book on page 7 Feedback on page 10 ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliates All rights reserved 6 Non Confidential ...

Page 7: ...iguration process of the Versatile Express V2M Juno r2 motherboard Chapter 4 Programmers Model This chapter describes the programmers model of the Versatile Express V2M Juno r2 motherboard Appendix A Signal Descriptions This appendix describes the signals present at the interface connectors of the Versatile Express V2M Juno r2 motherboard Appendix B Specifications This appendix contains the electr...

Page 8: ... timing diagrams Variations when they occur have clear labels You must not assume any timing information that is not explicit in the diagrams Shaded bus and signal areas are undefined so the bus or signal can assume any value within the shaded area at that time The actual level is unimportant and does not affect normal operation Clock HIGH to LOW Transient HIGH LOW to HIGH Bus stable Bus to high i...

Page 9: ...ose Input Output PLO61 Technical Reference Manual ARM DUI 0142 ARM PrimeCell Multimedia Card Interface PL180 Technical Reference Manual ARM DDI 0172 ARM Dual Timer Module SP804 Technical Reference Manual ARM DDI 0271 ARM Watchdog Module SP805 Technical Reference Manual ARM DDI 0270 CoreLink SMC 35x Static Memory Controller Series Technical Reference Manual ARM DDI 0380 AMBA 3 AHB Lite Protocol Spe...

Page 10: ...e title ARM Versatile Express Juno r2 Development Platform V2M Juno r2 Technical Reference Manual The number ARM 100114_0200_03_en If applicable the page number s to which your comments refer A concise explanation of your comments ARM also welcomes general suggestions for additions and improvements Note ARM tests the PDF only in Adobe Acrobat and Acrobat Reader and cannot guarantee the quality of ...

Page 11: ...recautions on page 1 12 1 2 About the Versatile Express Juno r2 Development Platform on page 1 13 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 1 4 Connectors on front and rear panels on page 1 16 ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliates All rights reserved 1 11 Non Confidential ...

Page 12: ...ment It is supplied with an enclosure that leaves the board sensitive to electrostatic discharges and permits electromagnetic emissions Caution To avoid damage to the V2M Juno r2 motherboard observe the following precautions Connect the external power supply to the board before powerup to prevent damage Never subject the board to high electrostatic potentials Observe Electrostatic discharge ESD pr...

Page 13: ...mum operating frequency 600MHz Overdrive Not supported Separate power domains support power management through Dynamic Voltage and Frequency Scaling DVFS of the Cortex A72 and Cortex A53 clusters and the Mali T624 GPU cluster Note See the Juno ARM Development Platform SoC Technical Reference Manual Revision r2p0 for more information on the Juno r2 SoC LogicTile site The V2M Juno r2 motherboard pro...

Page 14: ...DMI outputs The Juno r2 SoC sends two independent 24 bit RGB video channels to the HDMI transmitters Both HDMI ports share the same single I2S audio from the Juno r2 SoC Additional user key entry The V2M Juno r2 motherboard supports trusted keyboard entry and additional key entry to simulate hand held devices User LEDs The V2M Juno r2 motherboard provides eight user LEDs that connect to the IOFPGA...

Page 15: ...2 0 0 SATA 2 0 1 Hardware Reset ON OFF Soft Reset Configuration USB HDMI0 HDMI1 GbE dual USB Configuration 10Mbps Ethernet dual USB Keyboard and mouse Secure keyboard and user push button connector Dual UART PCIe slots Slot3 Slot2 Slot1 Slot0 User LEDs USER0 USER7 System LEDS ON1 ON2 DBG_USB SB_5V 5V 3V3 Power LEDs 3V coin battery User push buttons Configuration switches SW1 SW0 SMC Ethernet Figur...

Page 16: ...nfiguration Ethernet 10Mbps Port 3 Port 4 USB 2 0 ports Secure keyboard and user push button connector P JTAG Gigabit Ethernet HDMI 1 HDMI 0 UART 0 SW0 SW1 Configuration switches Configuration USB Hardware Reset ON OFF Soft Reset 12V DC UART 1 Figure 1 3 Rear panel 1 Introduction 1 4 Connectors on front and rear panels ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliates All rig...

Page 17: ...2 5 Clocks on page 2 28 2 6 Resets on page 2 35 2 7 Thin Links on page 2 38 2 8 IOFPGA on page 2 42 2 9 HDLCD interface on page 2 45 2 10 Interrupts on page 2 47 2 11 USB 2 0 interface on page 2 50 2 12 SMC 10 100 Ethernet interface on page 2 51 2 13 UART interface on page 2 52 2 14 PCI Express system on page 2 54 2 15 Keyboard and mouse interface on page 2 56 2 16 Additional user key entry on pag...

Page 18: ...are evaluation and tooling development using the Juno r2 SoC The following figure shows the hardware infrastructure of the V2M Juno r2 motherboard 2 Hardware Description 2 1 Overview of V2M Juno r2 motherboard hardware ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliates All rights reserved 2 18 Non Confidential ...

Page 19: ...rs USB 2 0 4 port hub PHY USB 2 0 USB 2 0 USB 2 0 USB 2 0 USB 2 0 UART 1 UART 0 UART HDMI 0 HDLCD 0 HDMI PHY HDMI 1 HDLCD 1 HDMI PHY SCC I2 S audio P JTAG Trace I2 C UART SEL I2 C PCIe I2 C Configuration Ethernet Configuartion EEPROM Keyboard Mouse SPI Secure keyboard and user push buttons User push buttons SPI SB UART SEL Reset push buttons I2 C I2 C User microSD NOR flash User LEDs Thin Links AX...

Page 20: ... One PCI Express switch Provides connectivity to the SATA 1000Base T Gbe Ethernet and PCIe expansion slots Four PCIe Gen 2 lanes to the Juno r2 SoC Two SATA ports Connects to a Silicon Image Sil3232 SATA controller with a x1 Gen 1 connection to the PCIe switch Serial ATA Generation 2 transfer rate of 3 0 Gbps Two 4 lane and two 1 lane PCIe Gen 2 expansion slots that connect directly to the PCIe sw...

Page 21: ...d mouse ports Six user push buttons for additional user key entry System registers Current voltage power and energy meters Timers Eight user LEDs Application software defines their meaning On board clocks that generate source clocks for Juno r2 SoC and V2M Juno r2 motherboard systems A real time clock in the MCC A 3V coin battery powers the real time clock when the board is powered down Three syst...

Page 22: ...ter a quad core Mali T624 graphics cluster interfaces on chip peripherals and internal network connect The following figure shows the architecture of the Juno r2 SoC 2 Hardware Description 2 2 Juno r2 ARM Development Platform SoC ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliates All rights reserved 2 22 Non Confidential ...

Page 23: ...ents ES NV counter ROTPK EK HUK DDR3L 1600 32 bit DDR3L PHY DDR3L 1600 32 bit DDR3L PHY DDR3L memory devices channel 0 DDR3L memory devices channel 1 IC FPGA master interface TLX 400 HDMI audio I2 S IC control I2 C Dual serial UART UART PL011 UART PL011 SMC SMC PL354 LogicTile expansion connector Board ICs HDMI 0 1 RS232 interface IOFPGA PMIC Clock sources Resets CoreLink GIC 400 GICv2m extension ...

Page 24: ...terface to off chip PHY PL354 Static Memory Controller SMC PL330 Direct Memory Access DMA controller CoreSight processor debug P JTAG and trace APB subsystem Dual UART I2S 4 channel stereo audio Power Voltage and Temperature PVT monitoring of Juno r2 ARM Development Platform SoC Non volatile counter A real time clock that retains its stored value after powerdown System Control Processor SCP This i...

Page 25: ...wer supply unit directly to the board On board regulators supply power to the V2M Juno r2 motherboard power domains and to the power domains of the Juno r2 SoC Power LEDs indicate the power domains that are active 5V 5V domain powered 3V3 3V3 domain powered SB_5V Standby 5V domain powered Related references 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 1 4 Connectors on fr...

Page 26: ...powerup or reset Direct control of the PMIC through the SCP interface during runtime supports voltage scaling Varying the Juno r2 SoC PLL dividers during runtime supports frequency scaling Note ARM recommends that you use this method to achieve frequency scaling and do not use external control of the clock generators through the V2M Juno r2 motherboard SCP I2C interface Dedicated logic blocks in t...

Page 27: ... PXL_REF_CLK PXL_CLK_IN ATX_ON CB_VRAMP Figure 2 3 Power control and DVFS system Related concepts 4 5 1 APB energy register summary on page 4 107 2 4 2 PVT sensor The Juno r2 SoC provides a Power Voltage and Temperature PVT sensor that powers down the chip when it exceeds the maximum operating temperature It also selectively powers down parts of the chip when it exceeds the temperature budget The ...

Page 28: ...tors to the correct operational clock frequencies The board txt file also defines these default clock frequencies You can change the operational clock frequencies by modifying the configuration board txt file Note ARM recommends that you operate the V2M Juno r2 motherboard at the default clock frequencies Related concepts 3 3 3 Contents of the MB directory on page 3 72 2 5 2 Juno r2 SoC and V2M Ju...

Page 29: ...LL OSCCLK 4 I2 S TLX 400 AXI master interface TLX 400 AXI slave interface I2S_CLK TMIF_CLKO TSIF_CLKO HDRX TMIF CLKI TSIF CLKI USB 2 0 PHY USB 4 port hub CLK 48M MCC HDRY SCC CFG_CLK DDR3L A53_PLL_CLK GPU_PLL_CLK A72_PLL_CLK Cortex A53 cluster Cortex A72 cluster Mali T624 GPU cluster SCP Cortex M3 CoreSight and trace Versatile Express LogicTile daughterboard HDRX HDRY SB bus IOFPGA SMB_FB CLK SMB_...

Page 30: ...2 motherboard clock 800MHz FAXICLK Fast AXI clock 533MHz SAXICLK Slow AXI clock 400MHz PCIEA_CLK 133MHz Transaction layer clock in the PCI Express Root Complex PCIE_TCLK 133MHz Clocks the AXI logic associated with the PCI Express Root Complex USBHCLK Primary clock for the BIU of the USB EHCI and OHCI host controllers 160MHz TMIF_CLK2X AXI master interface reference clock in the forward direction 1...

Page 31: ... system ULPI_CLK USB2 2 0 xtal clock generator 60MHz Fixed frequency clock Clocks the USB 2 0 Transceiver Macrocell Interface Low Pin Interface ULPI from the off chip PHY USB_CLK48 CLK_48M clock generator 48MHz Primary clock input to the USB controller PCIE_PHY_REF_CLK CLK_PCIE clock generator 125MHz Fixed frequency differential clock PCIe reference clock SMC_MCLK OSCLK 5 50MHz Clocks the PL354 St...

Page 32: ...n from the TLX 400 Thin Links AXI slave interface on the Juno r2 SoC The MCC uses the board txt configuration file in the microSD card to set the frequency of the board clock generators You can adjust these default clock frequencies by editing this file You can also adjust the board clocks during runtime by using the SYS_CFG register interface The Juno r2 SoC has internal PLLs and clock generators...

Page 33: ...ust SMB_CLK SMC_CLKO SMC_FB_CLK PL180 CLK_24MHz 1Hz TIM_CLK 3 0 WDT CLK Figure 2 5 IOFPGA clocks The bootup clock for the peripherals in the SMB_CLK domain during powerup and configuration is OSCCLK 9 on the V2M Juno r2 motherboard The clock source then switches to SMB_CLKO from the Juno r2 SoC that becomes the master clock for the SMB_CLK domain during runtime 2 Hardware Description 2 5 Clocks AR...

Page 34: ...ock for the following blocks inside the SMB_CLK clock domain PL180 MultiMedia Card Interface PL050 keyboard and mouse interfaces Energy meters that is the voltage current power and accumulated energy meters The clock generator that generates the 32kHz and 1MHz source clocks for the SP810 System Controller and the 1Hz clock for the PL031 Real Time Clock Note The SP810 System Controller selects 32kH...

Page 35: ...t of the system For more than two seconds puts the system into the standby state in the same way as pressing the Hardware Reset button Note The ON OFF Soft Reset push button is the red push button The V2M Juno r2 motherboard labels it as nPBON When you use the system with bare metal software you must make the following setting in the config txt file to enable direct control of the OFF Soft Reset f...

Page 36: ...Daughterboard Configuration Controller HDRY CB_nRST CB_nRST CB_RSTREQ CB_RSTREQ CB_nPOR Control Figure 2 6 V2M Juno r2 motherboard resets CB_nPOR This is the main powerup reset for the Juno r2 ARM Development Platform SoC and the devices and peripherals on the V2M Juno r2 motherboard including the IOFPGA The CB_nPOR signal drives the nPORESET signal inside the Juno r2 SoC 2 Hardware Description 2 ...

Page 37: ...nce The following figure shows the reset and configuration timing sequence MCC reset MCC config nPBRESET Hard Reset ON OFF Soft Reset CB_VRAMP All PSUs ON MB IOFPGA OSCCLKs SCCs DB FPGAs OSCCLKs SCCs SCP boot IOFPGA_nRST CFG_nRST CB_nPOR nPORESET CB_nRST CB_nTRST ADP boot System running Warm reset ATXON CB_CFGnRST DCC config Figure 2 7 V2M Juno r2 motherboard reset and configuration timing cycle 2...

Page 38: ... the Thin Links AXI master interface When the Thin Links ACE slave interface is in use one of the Juno r2 SoC clusters is disabled The default Thin Links clock frequency of 61 5MHz gives the following operating speeds Juno r2 SoC master interface Forward direction that is from the Juno r2 SoC to the FPGA 68MBps Reverse direction that is from the FPGA to the Juno r2 SoC 78MBps Juno r2 SoC slave int...

Page 39: ...LID_O TMIF_DATA_O 7 0 Forward data link layer TDATA FLOW FWD 1 0 TVALID FLOW FWD TDATA STREAM FWD 15 0 TVALID STREAM FWD Slave domain ADB 400 FPGA logic FPGA_ACLK TDATA FLOW REV 2 0 TVALID FLOW REV TDATA STREAM REV 15 0 TVALID STREAM REV TMIF_CLKO Clock gen TMIF_CLKI TCLK REV 1x TCLK_REV_2x Reg slice 2 1 mux Reg slice demux Juno r2 ARM Development Platform SoC Reverse data link layer Async Reg sli...

Page 40: ...Clock gen TCLK FWD 1x TSIF_CLKO TSIF_CLKI TCLK_FWD_2x Reg slice 2 1 mux Reg slice demux Juno r2 ARM Development Platform SoC Juno r2 SoC logic Forward data link layer Async Reg slice demux HDRX Reg slice 2 1 mux TDATA FLOW FWD 1 0 TVALID FLOW FWD TDATA STREAM FWD 55 0 TVALID STREAM FWD Slave domain TVALID FLOW REV TDATA STREAM REV 47 0 TVALID STREAM REV Clock gen TSIF_CLK2x TSIF CLK1x FAXICLK ADB ...

Page 41: ...REV Clock gen TCLK FWD 1x TSIF_CLKO TSIF_CLKI TCLK_FWD_2x Reg slice 2 1 mux Reg slice demux Juno r2 ARM Development Platform SoC Forward data link layer Async Reg slice demux HDRX Reg slice 2 1 mux TDATA FLOW FWD 1 0 TVALID FLOW FWD TDATA STREAM FWD 54 0 TVALID STREAM FWD Slave domain TVALID FLOW REV TDATA STREAM REV 46 0 TVALID STREAM REV Clock gen TSIF_CLK2x TSIF CLK1x TDATA FLOW REV 2 0 ADB 400...

Page 42: ... SMC interface The following figure shows the internal architecture of the IOFPGA and its connectivity to external peripherals including the external interrupts to the GIC 400 interrupt controller in the Juno r2 SoC 2 Hardware Description 2 8 IOFPGA ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliates All rights reserved 2 42 Non Confidential ...

Page 43: ...1MHz 32kHz En En TIM CLK WDT CLK KMI 0 KMI 1 LEDs DVI I2 C Not used DVFS Switches HDRY Versatile Express LogicTile daughteraboard FPGA HDRY SB_IRQ 11 NOR flash User microSD Energy meters SB_IRQ 9 SB_IRQ 6 SB_IRQ 8 SB_IRQ 7 SB_IRQ 0 SB_IRQ 12 GIC 400 SB_IRQ 12 0 PL180 SB_IRQ 10 SB_IRQ 5 PCIe switch PCIe I2 C HDMI PHYs PCIe clock Cfg User push buttons 10 100 Eth LAN 9118 Figure 2 11 IOFPGA internal ...

Page 44: ...User microSD card r1p0 SP804 Dual timer r2p0 SP805 Watchdog Timer r2p0 PL350 Series SMC Controller r1p0 AHB bus AMBA 3 AHB Lite Protocol Specification v1 0 APB bus AMBA 3 APB Protocol Specification v1 0 Note The peripheral versions apply to the Revision B V2M Juno r2 motherboard Related concepts 4 2 2 IOFPGA system peripherals memory map on page 4 85 2 Hardware Description 2 8 IOFPGA ARM 100114_02...

Page 45: ...on the V2M Juno r2 motherboard The HDMI controllers drive the HDMI connectors The Juno r2 SoC configures the HDMI controllers at powerup or reset over the AP I2C bus The HDMI controllers support I2S audio from the Juno r2 SoC They drive the audio to the HDMI connectors The same audio stream connects to both HDMI connectors Note Software that ARM supplies with the V2M Juno r2 motherboard configures...

Page 46: ...Mali T624 GPU HDLCDC0 PXL_CLK OUT HDLCDC1 PXL_CLK OUT HDLCD PLL PXL_REF_CLK PXL_PLL_CLK Figure 2 12 V2M Juno r2 motherboard HDLCD interface Related references 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 1 4 Connectors on front and rear panels on page 1 16 A 8 HDMI connectors on page Appx A 132 2 Hardware Description 2 9 HDLCD interface ARM 100114_0200_03_en Copyright 201...

Page 47: ...ard site The other three external interrupts are reserved The MCC generates its interrupt when you press the ON OFF Soft Reset push button All interrupts connect to the GIC 400 in the Juno r2 SoC through the IOFPGA The following figure shows an overview of the external interrupt signals from the V2M Juno r2 motherboard peripherals to the GIC 400 interrupt controller in the Juno r2 SoC 2 Hardware D...

Page 48: ... SoC interrupts overview The following table shows the mapping of the external interrupt signals to the GIC 400 in the Juno r2 SoC It lists the sources of the interrupts that originate in the V2M Juno r2 motherboard or the LogicTile Express fitted in the daughterboard site Table 2 5 External interrupt signals to Juno r2 SoC Interrupt ID GIC IRQ ID Motherboard signal name Source 96 99 64 67 Juno r2...

Page 49: ...oard and mouse interface 198 166 SB_IRQ 9 IOFPGA SP804 Dual timer 0 1 and SP804 dual timer 2 3 199 167 SB_IRQ 10 IOFPGA APB system registers from SYS_MISC SWINT Register 200 168 SB_IRQ 11 LogicTile FPGA daughterboard Interrupt from FPGA on LogicTile daughterboard 201 169 SB_IRQ 12 MCC Interrupt generated by pressing the ON OFF Soft Reset push button 202 223 170 191 Juno r2 SoC internal peripherals...

Page 50: ... and dual USB 2 0 connector J37 Versatile Express V2M Juno r2 motherboard Juno r2 ARM Development Platform SoC USB 2 0 4 port hub PHY USB 2 0 USB 2 0 USB 2 0 USB 2 0 Port 1 Port 2 Port 3 Port 4 Figure 2 14 V2M Juno r2 motherboard USB 2 0 interface Related references 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 1 4 Connectors on front and rear panels on page 1 16 A 2 Confi...

Page 51: ... following figure shows the SMC 10 100 Ethernet interface Versatile Express V2M Juno r2 motherboard Juno r2 ARM Development Platform SoC IOFPGA SMC 10 100 Ethernet LAN 9118 Figure 2 15 V2M Juno r2 motherboard SMC 10 100 Ethernet interface Related references 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 1 4 Connectors on front and rear panels on page 1 16 A 4 SMC 10 100 Eth...

Page 52: ...ected The Juno r2 SoC UART 1 interface connects to the UART 1 transceiver UART1 The Daughterboard Configuration Controller connects to the UART 1 transceiver Note If you set option UART1 for both MBLOG and DBLOG MBLOG overrides DBLOG and the UART 1 transceiver connects to the MCC UART 0 transceiver connects to the UART 0 interface on the Juno r2 SoC and the Daughterboard Configuration Controller i...

Page 53: ...igure 2 16 V2M Juno r2 motherboard UART interface Related concepts 2 13 UART interface on page 2 52 Related references 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 1 4 Connectors on front and rear panels on page 1 16 A 11 Dual UART connector on page Appx A 143 2 Hardware Description 2 13 UART interface ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliate...

Page 54: ...d Juno r2 ARM Development Platform SoC PCIe PCIe Gen 2 switch Part of PCIe Gigabit Ethernet and dual USB 2 0 connector J37 4 4 4 8 16 1 1 4 PCI Express expansion slots Slot 0 4 Slot 1 Slot 2 Slot 3 GbE controller Ethernet SATA 2 0 0 SATA 2 0 1 SATA 2 0 controller PCIe root complex 1 Gen 1 1 Gen 1 Figure 2 17 V2M Juno r2 motherboard PCIe system Related references 1 3 Location of components on the V...

Page 55: ...he SATA 2 0 controller have a Serial ATA Generation 2 transfer rate of 3 0 Gbps 300MBs Related references 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 A 10 SATA 2 0 connectors on page Appx A 141 2 14 4 Gigabit Ethernet port The PCIe switch connects to the Gigabit Ethernet controller over a single lane PCIe Gen 1 connection The controller is a Marvell 88E8057 A0 NNB2C000 G...

Page 56: ...uno r2 motherboard IOFPGA PL050 0 KMI 0 KMI 1 PL050 1 Keyboard Mouse Figure 2 18 V2M Juno r2 motherboard KMI interface Related references 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 1 4 Connectors on front and rear panels on page 1 16 A 7 Keyboard and Mouse Interface KMI connector on page Appx A 131 2 Hardware Description 2 15 Keyboard and mouse interface ARM 100114_0200...

Page 57: ...d provides a secure keyboard entry port for text entry using an external keyboard The following figure shows the additional user key interface and its connections to the user push buttons on the V2M Juno r2 motherboard Note One user push button input NU NMI to the FPGA is not available to the external secure keyboard custom device Versatile Express V2M Juno r2 motherboard 3V3 GND IOFPGA NU NMI VOL...

Page 58: ...ard and user push buttons PLO61 0 9 pin Mini Din Figure 2 20 Example trusted keyboard design Related references 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 1 4 Connectors on front and rear panels on page 1 16 A 12 Secure keyboard and user push buttons connector on page Appx A 145 2 Hardware Description 2 16 Additional user key entry ARM 100114_0200_03_en Copyright 2015 2...

Page 59: ... example DSTREAM or a compatible third party debugger You connect a compatible trace port analyzer for example DSTREAM or a compatible third party debugger to the TRACEA SINGLE connector to run 16 bit trace or to both the TRACEA SINGLE and TRACEB DUAL connector to run 32 bit trace The following figure shows an overview of the V2M Juno r2 motherboard debug and trace architecture 2 Hardware Descript...

Page 60: ...t AXI port AXI port to system AXI port from system SCP subsystem SWO Funnel cssys1 Input 0 Input 1 Input 2 Triggers Funnel Cortex A53 Input 0 Input 1 Input 2 Input 3 Funnel Cortex A72 Input 0 Input 1 ETF 0 ETF 1 Funnel cssys2 TPIU ETR Replicator Input 0 Input 1 CTI2 CTM channels Replicator ATB ATB APB Versatile Express V2M Juno r2 motherboard TRACEA SINGLE P JTAG TRACEB DUAL Juno r2 ARM Developmen...

Page 61: ... 4 Connectors on front and rear panels on page 1 16 A 1 1 P JTAG connector on page Appx A 122 A 1 2 Trace connectors on page Appx A 123 2 Hardware Description 2 17 Debug and trace ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliates All rights reserved 2 61 Non Confidential ...

Page 62: ...V2M Juno r2 motherboard configuration system on page 3 63 3 2 Configuration process and operating modes on page 3 65 3 3 Configuration files on page 3 70 3 4 Configuration switches on page 3 75 3 5 Use of reset push buttons on page 3 77 3 6 Command line interface on page 3 78 ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliates All rights reserved 3 62 Non Confidential ...

Page 63: ...PU MCC enables S32K_CLK SYS_REF_CLK and V2M Juno r2 board clocks MCC reads the daughterboard configuration files and starts configuration of the daughterboard MCC releases the SCC reset CFG_nRST MCC pre loads the flash images Apply power You can use the UART port to Access the MCC command line interface Access the microSD card through the configuration USB port Standby state No ON OFF Soft Reset b...

Page 64: ...no r2 SoC calibration data Note The HBI number is a unique code that identifies the board The root directories of the microSD card contain sub directories in the form HBI BoardNumber Boardrevision for example HBI0262D HBI0262D is the HBI number of the V2M Juno r2 motherboard If the MCC does not find a configuration directory that matches the HBI number of the board the configuration process fails ...

Page 65: ...uno r2 SoC are mostly powered down The powerup and configuration sequence takes them to the operating state Operating state This is the full operating mode Peripherals clocks and application code all operate The powerdown sequence takes the board to the standby state and the sleep state sequence takes it to the sleep state Sleep state This state powers down the Juno r2 SoC clusters and preserves o...

Page 66: ... Soft Reset button pressed briefly Powerdown sequence Hardware RESET button pressed or ON OFF Soft Reset button pressed for more than 2 seconds SCP wake up sequence ON OFF Soft Reset button pressed briefly Figure 3 2 Transitions between standby state operating state and sleep state 3 2 2 Powerup and configuration sequence The powerup and configuration sequence takes the V2M Juno r2 motherboard fro...

Page 67: ...nd then performs the basic setup of the Juno r2 SoC including the PLLs internal clocks and peripherals inside the Juno r2 SoC The SCP releases the Power Policy Units PPUs to start the cluster boot sequences 11 The MCC measures the board power supplies 12 The MCC reads the IOFPGA image from the configuration microSD card and loads it into the IOFPGA 13 The MCC sets the board oscillator frequencies ...

Page 68: ...te sequence is as follows 1 A short press of the On Off Soft Reset button less than two seconds Warning Pressing and holding the On Off Soft Reset button for more than two seconds initiates the powerdown sequence and puts the V2M Juno r2 motherboard into the standby state This might result in loss of data 2 The System Control Processor SCP sends the Message Handling Unit MHU sleep command to the a...

Page 69: ...state data to on chip secure RAM so that the application cluster that is either the Cortex A72 or Cortex A53 resumes in the correct state and does not boot up from standby 5 The SCP releases the Power Policy Unit PPU to start the application cluster boot sequence 6 The application code resumes from the point when the Juno r2 SoC went into the sleep state 3 Configuration 3 2 Configuration process a...

Page 70: ...nfiguration files if you change the system configuration The configuration microSD card contains default configuration files If you connect a workstation to the configuration USB port or configuration Ethernet port the configuration memory device that is the configuration microSD card appears as a USB Mass Storage Device USBMSD and you can add edit or delete files You can use a standard text edito...

Page 71: ...herboard variants present in the system The subdirectory names match the HBI codes for the specific motherboard variants The files in these directories contain clock register and other settings for the boards SITE1 directory Contains configuration files that relate to the Juno r2 SoC and to external memory that the Juno r2 SoC can access SITE2 directory Contains configuration files for any LogicTi...

Page 72: ... FALSE LOG DB MICRO in run mode FALSE UART1 when MBLOG is not UART1 USERSWITCH 00000000 Userswitch 7 0 in binary CONFSWITCH 00000000 Configuration Switch 7 0 in binary ASSERTNPOR TRUE External resets assert nPOR WDTRESET NONE Watchdog reset options NONE RESETMB RESETDB PCIMASTER DB1 Port Failover DB1 SL3 MASTERSITE DB1 Boot Master DB1 SL3 REMOTE NONE Selects remote command options NONE USB FTP SMC...

Page 73: ...3 3 4 Contents of the SITE1 directory The SITE1 directory contains files that relate to the Juno r2 SoC and to external memory on the V2M Juno r2 motherboard that the Juno r2 SoC can access The SITE1 subdirectory contains an HBI0262D subdirectory that matches the HBI code of the V2M Juno r2 motherboard The HBI0262D subdirectory contains the following files A board txt file Contains configuration i...

Page 74: ... 0x00F00000 Image Flash Address NOR3FILE SOFTWARE juno dtb Image File Name NOR3LOAD 00000000 Image Load Address NOR3ENTRY 00000000 Image Entry Point 3 3 5 Contents of the SITE2 directory The SITE2 directory contains configuration files for LogicTile daughterboards that you can fit in the V2M Juno r2 motherboard daughterboard site See the Technical Reference Manual for your fitted daughterboard for...

Page 75: ...1 the boot loader runs the OS automatically at powerup If the OS software supports this feature under UEFI this boot process starts automatically irrespective of the switch setting SYS_SW 30 indicates the value of physical configuration switch SW0 A user application can also modify SYS_SW 0 but the change does not take effect until the next reset Remote UART control switch SW1 SW1 in the ON positi...

Page 76: ...herboard The following figure shows the cable wiring 1 2 3 4 5 6 7 8 9 V2M Juno r2 UART connector Server or host computer UART connector 1 2 3 4 5 6 7 8 9 STANDBY LOW SYSTEM HIGH MCC DSR CTS Figure 3 4 Modem cable wiring You can control the SER0_DSR and SER0_CTS signals using control logic on the host computer Alternatively you can use a custom terminal program such as ARM VETerminal exe that ARM ...

Page 77: ...ters the operating state Note The MCC does not read the configuration files or perform a board reconfiguration as a result of a software reset The CB_nPOR signal drives the nPORESET signal inside the Juno r2 SoC Related concepts 2 6 1 Reset push buttons on page 2 35 Related references 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 1 4 Connectors on front and rear panels on ...

Page 78: ...erboard Configuration Controller on the LogicTile daughterboard You must set the DBLOG option in the config txt to TRUE to enter LogicTile daughterboard system commands at the UART1 port The setting takes effect after the next reset The workstation settings must be 115 2kBaud 8N1 representing 8 data bits no parity one stop bit No hardware or software flow control See the appropriate Technical Refe...

Page 79: ...nu Enter DEBUG at the main menu to switch to the debug submenu The debug submenu is valid only in operating state The following table shows the debug commands Table 3 2 V2M Juno r2 motherboard MCC debug command menu Command Description DATE Display current date DEBUG 0 1 Enable or disable debug printing 0b0 Disable 0b1 Enable DEPOSIT address data Write word to system memory address EXAM address nn...

Page 80: ...ase configuration section of EEPROM ERASEDEV 0 Erase device section of EEPROM ERASERANGE 0 start end Erase EEPROM between start and end ERASEIMAGE image_id Erase image named image_id stored in Motherboard EEPROM ERASEIMAGES Erase images stored in Motherboard EEPROM HELP or Display this help READIMAGES Read images stored in Motherboard EEPROM READCF 0 Read configuration EEPROM READRANGE 0 start end...

Page 81: ...ions 4 1 About this programmers model on page 4 82 4 2 V2M Juno r2 motherboard memory maps on page 4 83 4 3 APB system registers on page 4 89 4 4 APB system configuration registers on page 4 103 4 5 APB energy meter registers on page 4 107 ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliates All rights reserved 4 81 Non Confidential ...

Page 82: ...ions Attempting to access these locations can result in UNPREDICTABLE behavior Unless otherwise stated in the accompanying text Do not modify undefined register bits Ignore undefined register bits on reads All register bits are reset to a logic 0 by a system or powerup reset 4 3 1 APB system register summary on page 4 89 4 4 1 APB system configuration register summary on page 4 103 and 4 5 1 APB e...

Page 83: ...emory maps on page 4 88 4 2 1 Juno r2 SoC top level application and SMC interface memory maps The Juno r2 SoC SMC occupies the expansion AXI memory at 0x0008000000 and supports chip selects that access components systems and memory on the V2M Juno r2 motherboard The security status is exported security Chip select CS3 inside the SMC accesses the low bandwidth system peripherals inside the IOFPGA a...

Page 84: ...rved Reserved 251MB 0x0070000000 Juno r2 SoC peripherals 5MB 0x007FB00000 0xFFFFFFFFFF Figure 4 1 Juno r2 SoC top level application and SMC interface memory maps Note The region 0x007FB00000 to 0x007FFFFFFF Juno r2 SoC peripherals contains some Reserved memory space See the Juno ARM Development Platform SoC Technical Reference Manual Revision r2p0 for details of this part of the memory map Expansi...

Page 85: ...e information 4 2 2 IOFPGA system peripherals memory map The memory map of the IOFPGA system peripherals is at chip select CS3 in the SMC interface The chip select CS3 is at 0x001C000000 and provides access to low bandwidth system peripherals in the IOFPGA that the Juno r2 SoC does not provide The following figure shows the mapping of the IOFPGA system peripherals memory map into the SMC memory ma...

Page 86: ...000 0x001C080000 0x001C070000 0x001C0F0000 0x001C100000 0x001C110000 0x001C120000 0x001C140000 0x001C160000 0x001C170000 0x001C180000 0x001C1D0000 0x001C1E0000 Reserved 46MB 0x001C1F0000 0x001EFFFFFF IOFPGA peripherals memory map SBCon 1 PCIe Clk configuration 64KB 0x001C050000 SP810 System controller 0x0018000000 0x0014040000 CS0 NOR 64MB Reserved 65280KB CS1 IOFPGA block RAM 256KB CS3 IOFPGA per...

Page 87: ...FFF 128KB Reserved Do not write to or read from these addresses 0x1C160000 0x1C16FFFF 64KB CS3 SBCon 2 HDMI PHYs configuration 0x1C170000 0x1C17FFFF 64KB PL031 RTC 0x1C180000 0x1C1CFFFF 320KB Reserved Do not write to or read from these addresses 0x1C1D0000 0x1C1DFFFF 64KB CS3 PL061 GPIO 0 Additional user key entry 0x1C1E0000 0x1C1EFFFF 64KB Reserved Do not write to or read from these addresses 0x1...

Page 88: ...00 256GB 216GB 512GB Reserved PCIe expansion Reserved Figure 4 3 V2M Juno r2 motherboard DDR3L memory map The following table shows the V2M Juno r2 motherboard DDR3L memory map Table 4 3 V2M Juno r2 motherboard DDR3L memory map Address range Size Description 0x0080000000 0x00FFFFFFFF 2GB DDR3L 0x0880000000 0x09FFFFFFFF 6GB DDR3L 4 2 4 Additional Juno r2 SoC memory maps The Juno r2 SoC contains add...

Page 89: ...ister on page 4 92 0x0024 SYS_100HZ RO RW 0xXXXXXXXX 32 See 4 3 5 SYS_100HZ Register on page 4 92 0x0030 SYS_FLAG RO 0x00000000 32 See 4 3 6 SYS_FLAG Registers on page 4 93 0x0030 SYS_FLAGSSET WO 32 See 4 3 6 SYS_FLAG Registers on page 4 93 0x0034 SYS_FLAGSCLR WO 32 See 4 3 6 SYS_FLAG Registers on page 4 93 0x0038 SYS_NVFLAGS RO 0x00000000 32 See 4 3 6 SYS_FLAG Registers on page 4 93 0x0038 SYS_NV...

Page 90: ... configurations The following figure shows the bit assignments 31 28 16 15 8 0 27 12 11 7 Rev HBI Build Arch FPGA Figure 4 4 SYS_ID Register bit assignments The following table shows the bit assignments Table 4 6 SYS_ID Register bit assignments Bits Name Function 31 28 Rev Board revision 0x0 Rev A board This is the prototype board and contains the Juno r0 SoC 0x1 Rev B board This board contains th...

Page 91: ...urations Available in all V2M Juno r2 motherboard configurations The following figure shows the bit assignments 31 28 8 0 Reserved 27 7 Soft user switch 30 29 nUART0DSR nUART0CTS SW 0 SW 1 Figure 4 5 SYS_SW Register bit assignments The following table shows the bit assignments Table 4 7 SYS_SW Register bit assignments Bits Name Function 31 SW 1 Indicates the value of the physical configuration swi...

Page 92: ...traints There are no usage constraints Configurations Available in all V2M Juno r2 motherboard configurations The following figure shows the bit assignments 31 8 0 Reserved 7 LED 7 0 Figure 4 6 SYS_LED Register bit assignments The following table shows the bit assignments Table 4 8 SYS_LED Register bit assignments Bits Name Function 31 8 Reserved If you write to this register you must write all ze...

Page 93: ...FLAGSSET SYS_FLAGSCLR SYS_NVFLAGSSET and SYS_NVFLAGSCLR registers to set and clear the bits in the Flag Registers Usage constraints The SYS_FLAGS and SYS_NVFLAGS Registers are read only The SYS_FLAGSSET SYS_FLAGSCLR SYS_NVFLAGSSET and SYS_NVFLAGSCLR Registers are write only Configurations Available in all V2M Juno r2 motherboard configurations SYS_FLAGS Register The SYS_FLAGS Register is one of th...

Page 94: ...raints There are no usage constraints Configurations Available in all V2M Juno r2 motherboard configurations The following figure shows the bit assignments 31 0 Reserved 7 8 SOFT_CONFIG_SWITCH Figure 4 8 SYS_CFGSW Register bit assignments The following table shows the bit assignments Table 4 10 SYS_CFGSW Register bit assignments Bits Name Function 31 8 Reserved If you write to this register you mu...

Page 95: ...reset CB_nRST sets the register to zero and then the count resumes Related concepts 4 3 1 APB system register summary on page 4 89 4 3 9 SYS_MISC Register The SYS_MISC Register characteristics are Purpose Denotes the presence or absence of a LogicTile Express daughterboard fitted in the daughterboard site Usage constraints Bit 19 is read write Bit 13 is read only Configurations Available in all V2...

Page 96: ...s register you must write all zeros to these bits If you read this register you must ignore these bits Related concepts 4 3 1 APB system register summary on page 4 89 4 3 10 SYS_PCIE_CNTL Register The SYS_PCIE_CNTL Register characteristics are Purpose Error signal from PCIe switch and reset signal to PCIe Express slots Usage constraints There are no usage constraints Configurations Available in al...

Page 97: ...63 0 32 SYS_PCIE_GBE_L 31 SYS_PCIE_GBE_H Reserved 48 47 Figure 4 12 SYS_PCIE_GBE Register bit assignments The following table shows the bit assignments Table 4 14 SYS_PCI_GBE Register bit assignments Bits Name Function 63 48 Reserved If you read this register you must ignore these bits 47 32 SYS_PCIE_GBE_H Most significant 16 bits of the PCI Express Ethernet MAC address 31 0 SYS_PCIE_GBE_L Least s...

Page 98: ...register summary on page 4 89 4 3 13 SYS_PROC_ID1 Register The SYS_PROC_ID1 Register characteristics are Purpose Contains identification information about the FPGA image and the LogicTile Express daughterboard fitted to the V2M Juno r2 motherboard Usage constraints There are no usage constraints Configurations Available in all V2M Juno r2 motherboard configurations The following figure shows the b...

Page 99: ...ted concepts 4 3 1 APB system register summary on page 4 89 4 3 14 SYS_FAN_SPEED Register The SYS_FAN_SPEED Register characteristics are Purpose Contains a value that represents the fan operating speed The MCC uses this value to moderate the speed of the cooling fan on the V2M Juno r2 motherboard Usage constraints There are no usage constraints Configurations Available in all V2M Juno r2 motherboa...

Page 100: ...lated concepts 4 3 1 APB system register summary on page 4 89 4 3 15 SP810_CTRL Register The SP810_CTRL Register characteristics are Purpose This register in the SP810 system controller selects the source clocks for the four SP804 timers in the IOFPGA Usage constraints There are no usage constraints Configurations Available in all V2M Juno r2 motherboard configurations The following figure shows t...

Page 101: ...l Selects the source clock for SP804 2 timer clock TIM_CLK 2 0b0 TIM_CLK 2 32kHz 0b1 TIM_CLK 2 1MHz Note The default is 0b0 18 Reserved If you write to this register you must write all zeros to these bits If you read this register you must ignore these bits 17 TimerEn1Sel Selects the source clock for SP804 1 timer clock TIM_CLK 1 0b0 TIM_CLK 1 32kHz 0b1 TIM_CLK 1 1MHz Note The default is 0b0 16 Re...

Page 102: ...MHz Note The default is 0b0 14 0 Reserved If you write to this register you must write all zeros to these bits If you read this register you must ignore these bits Related concepts 4 3 1 APB system register summary on page 4 89 4 Programmers Model 4 3 APB system registers ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliates All rights reserved 4 102 Non Confidential ...

Page 103: ...DATA_OUT Register characteristics are Purpose The application software in the Juno r2 SoC writes data to the SYS_CFGDATA Register during a write operation This data represents a value or function that the write operation sends to the addressed component for example the frequency value of a clock generator The MCC or Daughterboard Configuration Controller writes return data to the SYS_CFGDATA Regis...

Page 104: ... Writing to this bit generates an interrupt 30 nRead_Write 0b0 Read access 0b1 Write access 29 26 DCC 4 bit number that selects the Daughterboard Configuration Controller on the daughterboard For example 0x0 Selects DCC 0 0x1 Selects DCC 1 25 20 Function 6 bit value that defines the function of the daughterboard device that the transaction writes to or reads from These bits support the following f...

Page 105: ...figuration register summary on page 4 103 4 4 4 SYS_CFGSTAT Register The SYS_CFGSTAT Register characteristics are Purpose Contains system configuration status information about read and write operations between the application software in the Juno r2 SoC and a component on a fitted LogicTile Express daughterboard or the V2M Juno r2 motherboard Usage constraints The SYS_CFGSTAT Register is read onl...

Page 106: ...n successful 0b1 Configuration failed 0 Configuration complete A write to SYS_CFGCTRL clears this bit 0b0 Configuration not complete 0b1 Configuration complete Related concepts 4 4 1 APB system configuration register summary on page 4 103 4 Programmers Model 4 4 APB system configuration registers ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliates All rights reserved 4 106 Non ...

Page 107: ...lusters that is the parts of the chip that operate from the VSYS power supply Caution You cannot use a core in one cluster to obtain a current or power consumption value of the same cluster Because the process of reading a current or power register alters the current and power consumption of that cluster such a measurement is not valid For this reason you cannot use a Cortex A72 core to obtain the...

Page 108: ...00 32 See 4 5 11 SYS_POW_A72 Register on page 4 114 0x00F8 SYS_POW_A53 RO 0x00000000 32 See 4 5 12 SYS_POW_A53 Register on page 4 115 0x00FC SYS_POW_GPU RO 0x00000000 32 See 4 5 13 SYS_POW_GPU Register on page 4 115 0x0100 SYS_ENM_L_SYS RW 0x00000000 32 See 4 5 14 SYS_ENM_SYS Register on page 4 116 0x0104 SYS_ENM_H_SYS RW 0x00000000 32 See 4 5 14 SYS_ENM_SYS Register on page 4 116 0x0108 SYS_ENM_L...

Page 109: ...ment 4096 represents 5A Full scale is 0xFFF Measured current SYS_I_SYS 1 761 amperes The CB_nRST reset signal resets the register to zero The register then updates every 100µs after the reset Related concepts 4 5 1 APB energy register summary on page 4 107 4 5 3 SYS_I_A72 Register The SYS_I_A72 Register characteristics are Purpose Contains a 12 bit representation of the instantaneous current consu...

Page 110: ...he following figure shows the bit assignments 31 0 Reserved 11 12 SYS_I_A53 Figure 4 22 SYS_I_A53 Register bit assignments The following table shows the bit assignments Table 4 26 SYS_I_A53 Register bit assignments Bits Name Function 31 12 Reserved If you read this register you must ignore these bits 11 0 SYS_I_A53 12 bit representation of the instantaneous current consumption of the Cortex A53 cl...

Page 111: ... Purpose Contains a 12 bit representation of the instantaneous supply voltage of the Juno r2 SoC outside the clusters Usage constraints This register is read only Configurations Available in all V2M Juno r2 motherboard configurations The following figure shows the bit assignments 31 0 Reserved 11 12 SYS_V_SYS Figure 4 24 SYS_V_SYS Register bit assignments The following table shows the bit assignme...

Page 112: ...ge of the Cortex A72 cluster Full scale measurement 4096 represents 2V5 Full scale is 0xFFF Measured voltage SYS_V_A72 1 1622 volts The CB_nRST reset signal resets the register to zero The register then updates every 100µs after the reset Related concepts 4 5 1 APB energy register summary on page 4 107 4 5 8 SYS_V_A53 Register The SYS_V_A53 Register characteristics are Purpose Contains a 12 bit re...

Page 113: ... shows the bit assignments 31 0 Reserved 11 12 SYS_V_GPU Figure 4 27 SYS_V_GPU Register bit assignments The following table shows the bit assignments Table 4 31 SYS_V_GPU Register bit assignments Bits Name Function 31 12 Reserved If you read this register you must ignore these bits 11 0 SYS_V_GPU 12 bit representation of the instantaneous supply voltage of the Mali T624 GPU cluster Full scale meas...

Page 114: ...nRST reset signal resets the register to zero The register then updates every 100µs after the reset Related concepts 4 5 1 APB energy register summary on page 4 107 4 5 11 SYS_POW_A72 Register The SYS_POW_A72 Register characteristics are Purpose Contains a 24 bit representation of the instantaneous power consumption of the Cortex A72 cluster Usage constraints This register is read only You must us...

Page 115: ...otherboard configurations The following figure shows the bit assignments 31 0 Reserved 24 SYS_POW_A53 23 Figure 4 30 SYS_POW_A53 Register bit assignments The following table shows the bit assignments Table 4 34 SYS_POW_A53 Register bit assignments Bits Name Function 31 24 Reserved If you read this register you must ignore these bits 23 0 SYS_POW_A53 24 bit representation of the instantaneous power...

Page 116: ...e CB_nRST reset signal resets the register to zero The register then updates every 100µs after the reset Related concepts 4 5 1 APB energy register summary on page 4 107 4 5 14 SYS_ENM_SYS Register The SYS_ENM_SYS Register characteristics are Purpose Contains a 64 bit representation of the accumulated energy consumption of the fabric of the Juno r2 SoC outside the clusters Usage constraints Writin...

Page 117: ...ccumulated energy SYS_ENM_CH0_H_SYS SYS_ENM_L_SYS 12348030000 joules The CB_nRST reset signal resets the register to zero The register then updates every 100µs after the reset Related concepts 4 5 1 APB energy register summary on page 4 107 4 5 15 SYS_ENM_A72 Register The SYS_ENM_A72 Register characteristics are Purpose Contains a 64 bit representation of the accumulated energy consumption of the ...

Page 118: ... SYS_ENM_L_A72 6174020000 joules The CB_nRST reset signal resets the register to zero The register then updates every 100µs after the reset Related concepts 4 5 1 APB energy register summary on page 4 107 4 5 16 SYS_ENM_A53 Register The SYS_ENM_A53 Register characteristics are Purpose Contains a 64 bit representation of the accumulated energy consumption of the Cortex A53 cluster Usage constraints...

Page 119: ...YS_ENM_L_A53 12348030000 joules The CB_nRST reset signal resets the register to zero The register then updates every 100µs after the reset Related concepts 4 5 1 APB energy register summary on page 4 107 4 5 17 SYS_ENM_GPU Register The SYS_ENM_GPU Register characteristics are Purpose Contains a 64 bit representation of the accumulated energy consumption of the Mali T624 GPU cluster Usage constrain...

Page 120: ...µs after the reset 31 0 SYS_ENM_L_GPU Least significant 32 bits of a 64 bit representation of the accumulated energy consumption of the Mali T624 GPU cluster The memory address offset of these bits is 0x0118 Accumulated energy SYS_ENM_H_GPU SYS_ENM_L_GPU 6174020000 joules The CB_nRST reset signal resets the register to zero The register then updates every 100µs after the reset Related concepts 4 5...

Page 121: ...t connector on page Appx A 128 A 5 Configuration USB connector on page Appx A 129 A 6 Header connectors on page Appx A 130 A 7 Keyboard and Mouse Interface KMI connector on page Appx A 131 A 8 HDMI connectors on page Appx A 132 A 9 PCI Express expansion slots on page Appx A 133 A 10 SATA 2 0 connectors on page Appx A 141 A 11 Dual UART connector on page Appx A 143 A 12 Secure keyboard and user pus...

Page 122: ...G connector J25 Table A 1 P JTAG connector J25 signal list Pin Signal Pin Signal 1 VTREFC 1V8 2 CS_BS_VSUPPLY 1V8 3 nTRST 4 GND 5 TDI 6 GND 7 SWDIO TMS 8 GND 9 SWDCLK TCK 10 GND 11 GND RTCK 12 GND 13 SWO TDO 14 GND 15 nSRST 16 GND 17 No connection EDBGRQ 18 GNDDETECT 19 No connection DBGACK 20 GND Note Pins 9 and 17 have pulldown resistors to 0V Pin 11 has a pulldown resistor to 0V V2M Juno r2 mot...

Page 123: ...hat you can use All trace and SWD signals operate at 1 8V The trace connectors cannot supply power to a trace unit The following figure shows the MICTOR 38 connector 2 38 1 37 Figure A 2 MICTOR 38 connector J27 and J28 The following table shows the pin mapping for the Trace and SWD signals on the TRACEA SINGLE connector J28 Table A 2 TRACEA SINGLE connector J28 signal list Pin Signal Pin Signal 1 ...

Page 124: ...ection 3 No connection 4 No connection 5 GND 6 TRACE_CLKB 7 No connection 8 No connection 9 No connection 10 No connection 11 No connection 12 1V8 reference 13 No connection 14 No connection 15 No connection 16 TRACEDATA 23 17 No connection 18 TRACEDATA 22 19 No connection 20 TRACEDATA 21 21 No connection 22 TRACEDATA 20 23 TRACEDATA 31 24 TRACEDATA 19 25 TRACEDATA 30 26 TRACEDATA 18 27 TRACEDATA ...

Page 125: ...cation of components on the V2M Juno r2 motherboard on page 1 15 A Signal Descriptions A 1 Debug connectors ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliates All rights reserved Appx A 125 Non Confidential ...

Page 126: ...al purpose USB 2 0 ports on the V2M Juno r2 motherboard The following figure shows the configuration 10Mbps Ethernet and dual USB 2 0 connector J40 USB 2 0 port 1 USB 2 0 port 2 Configuration Ethernet 10Mbps Figure A 3 Configuration 10Mbps Ethernet and dual USB 2 0 connector J40 Related concepts 2 11 USB 2 0 interface on page 2 50 3 3 1 Overview of configuration files and microSD card directory st...

Page 127: ...al purpose USB 2 0 ports on the V2M Juno r2 motherboard The following figure shows the PCIe Gigabit Ethernet and dual USB 2 0 connector J37 USB 2 0 port 3 USB 2 0 port 4 PCIe Ethernet 1000Base T Figure A 4 PCIe Gigabit Ethernet and dual USB 2 0 connector J37 Related concepts 2 11 USB 2 0 interface on page 2 50 2 14 4 Gigabit Ethernet port on page 2 55 Related references 1 3 Location of components ...

Page 128: ...et connector J50 Related concepts 2 12 SMC 10 100 Ethernet interface on page 2 51 Related references 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 1 4 Connectors on front and rear panels on page 1 16 A Signal Descriptions A 4 SMC 10 100 Ethernet connector ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliates All rights reserved Appx A 128 Non Confidential...

Page 129: ...hows the configuration USB 2 0 connector J48 Figure A 6 Configuration USB 2 0 connector J48 Related concepts 3 3 1 Overview of configuration files and microSD card directory structure on page 3 70 Related references 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 1 4 Connectors on front and rear panels on page 1 16 A Signal Descriptions A 5 Configuration USB connector ARM 10...

Page 130: ... site Header Y J4 routes the buses and power interconnect between the V2M Juno r2 motherboard and the LogicTile FPGA daughterboard The constraints file an415_wrapper xdc available in AN415 Example Express 20MG design for a V2M Juno Motherboard lists the header signals Related references 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 A Signal Descriptions A 6 Header connecto...

Page 131: ... 2 Keyboard Figure A 7 Dual mini DIN KMI connector J59 Related concepts 2 15 Keyboard and mouse interface on page 2 56 Related references 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 1 4 Connectors on front and rear panels on page 1 16 A Signal Descriptions A 7 Keyboard and Mouse Interface KMI connector ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliat...

Page 132: ...l list Pin Signal Pin Signal 1 DVI_TX2P 2 GND 3 DVI_TX2N 4 DVI_TX1P 5 GND 6 DVI_TX1N 7 DVI_TX0P 8 GND 9 DVI_TX0N 10 DVI_TXCP 11 GND 12 DVI_TXCN 13 DVI_CECAO 14 No connection 15 DVI_DSCLO 16 DVI_DSDAO 17 GND 18 DVI_5V0 19 DVI_HPDO Related concepts 2 9 HDLCD interface on page 2 45 Related references 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 1 4 Connectors on front and re...

Page 133: ... 4 connectors one lane slots 0 and 1 connectors J10 and J11 Pin B1 Pin B32 Pin A32 Pin A1 Figure A 9 PCIe 4 connector one lane slots 0 and 1 connectors J10 and J11 The following table shows the pin mapping for the one lane PCI 4 connector one lane slot 0 that is connector J11 Table A 5 PCIe one lane slot 0 connector J11 signal list Pin Signal Pin Signal B1 12V A1 GND B2 12V A2 12V B3 12V A3 12V B4...

Page 134: ... A32 No connection The following table shows the pin mapping for the one lane PCI 4 connector one lane slot 1 that is connector J10 Table A 6 PCIe one lane slot 1 connector J10 signal list Pin Signal Pin Signal B1 12V A1 GND B2 12V A2 12V B3 12V A3 12V B4 GND A4 GND B5 No connection A5 No connection B6 No connection A6 PCIE_LOOP3 B7 GND A7 PCIE_LOOP3 B8 3V3 A8 No connection B9 No connection A9 3V3...

Page 135: ...ts on page 2 54 Related references 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 A 9 2 PCI Express 8 connector four lane slot 2 The V2M Juno r2 motherboard provides one PCIe 8 connector that provides four PCIe lanes The board uses four lanes of the eight and does not use the other four lanes Note The PCIe I O voltage at the connector is 3 3V The following figure shows the ...

Page 136: ...RSNT2 A17 PCIE_PERN12 B18 GND A18 GND B19 PCIE_PETP13 A19 No connection B20 PCIE_PETN13 A20 GND B21 GND A21 PCIE_PERP13 B22 GND A22 PCIE_PERN13 B23 PCIE_PETP14 A23 GND B24 PCIE_PETN14 A24 GND B25 GND A25 PCIE_PERP14 B26 GND A26 PCIE_PERN14 B27 PCIE_PETP15 A27 GND B28 PCIE_PETN15 A28 GND B29 GND A29 PCIE_PERP15 B30 No connection A30 PCIE_PERN15 B31 PCIE_nPRSNT2 A31 GND B32 GND A32 No connection B33...

Page 137: ...nents on the V2M Juno r2 motherboard on page 1 15 A 9 3 PCI Express 16 connector four lane slot 3 The V2M Juno r2 motherboard provides one PCIe 16 connector that provides four PCIe lanes The board uses four lanes of the 16 and does not use the other 12 lanes Note The PCIe IO voltage at the connector is 3 3V The following figure shows the PCIe 16 connector four lane slot 3 connector J9 Pin B1 Pin B...

Page 138: ...PRSNT1 A17 PCIE_PERN8 B18 GND A18 GND B19 PCIE_PETP9 A19 No connection B20 PCIE_PETN9 A20 GND B21 GND A21 PCIE_PERP9 B22 GND A22 PCIE_PERN9 B23 PCIE_PETP10 A23 GND B24 PCIE_PETN10 A24 GND B25 GND A25 PCIE_PERP10 B26 GND A26 PCIE_PERN10 B27 PCIE_PETP11 A27 GND B28 PCIE_PETN11 A28 GND B29 GND A29 PCIE_PERP11 B30 No connection A30 PCIE_PERN11 B31 PCIE_nPRSNT1 A31 GND B32 GND A32 No connection B33 No ...

Page 139: ...1 No connection A51 GND B52 GND A52 No connection B53 GND A53 No connection B54 No connection A54 GND B55 No connection A55 GND B56 GND A56 No connection B56 GND A56 No connection B57 No connection A57 GND B58 No connection A58 GND B59 No connection A59 GND B60 GND A60 No connection B61 GND A61 No connection B62 No connection A62 GND B63 No connection A63 GND B64 GND A64 No connection B65 GND A65 ...

Page 140: ...7 No connection B78 No connection A78 GND B79 No connection A79 GND B80 GND A80 No connection B81 PCIE_nPRSNT1 A81 No connection B82 No connection A82 GND Related concepts 2 14 2 PCI Express expansion slots on page 2 54 Related references 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 A Signal Descriptions A 9 PCI Express expansion slots ARM 100114_0200_03_en Copyright 2015...

Page 141: ... connector J39 signal list SATA connector pin number SATA connector pin name Motherboard signal to SATA 2 0 controller S1 GND S2 A SATA_TX0_P_C S3 A SATA_TX0_N_C S4 GND S5 B SATA_RX0_N_C S6 B SATA_RX0_P_C S7 GND The following table shows the pin mapping for the SATA 1 connector J38 Table A 10 SATA1 connector J38 signal list SATA connector pin number SATA connector pin name Motherboard signal to SA...

Page 142: ...tion of components on the V2M Juno r2 motherboard on page 1 15 A Signal Descriptions A 10 SATA 2 0 connectors ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliates All rights reserved Appx A 142 Non Confidential ...

Page 143: ...for UART 0 This is the upper connector J57A of the dual UART connector J57 Table A 11 UART 0 connector J57A signal list Pin Signal A1 No connection A2 SER0_RX A3 SER0_TX A4 SER0_DTR A5 GND A6 SER0_DSR A7 SER0_RTS A8 SER0_CTS A9 No connection The following table shows the pin mapping for UART 1 This is the lower connector J57B of the dual UART connector J57 Table A 12 UART 1 connector J57B signal l...

Page 144: ...rface on page 2 52 Related references 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 1 4 Connectors on front and rear panels on page 1 16 A Signal Descriptions A 11 Dual UART connector ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliates All rights reserved Appx A 144 Non Confidential ...

Page 145: ...ttons connector J58 Table A 13 Secure keyboard and user push buttons connector J58 signal list Pin Signal 1 SEC_DF 2 SEC_PB0 3 GND 4 SEC_PB1 5 5V_KMI 6 SEC_CF 7 SEC_PB2 8 SEC_PB3 9 SEC_PB4 Related concepts 2 16 Additional user key entry on page 2 57 Related references 1 3 Location of components on the V2M Juno r2 motherboard on page 1 15 1 4 Connectors on front and rear panels on page 1 16 A Signa...

Page 146: ...e ATX power connector J20 on the V2M Juno r2 motherboard Table A 14 ATX power connector J20 signal list Pin Signal Pin Signal 1 3V3 13 3V3 2 3V3 14 12V 3 GND 15 GND 4 5V 16 nATXON 5 GND 17 GND 6 5V 18 GND 7 GND 19 GND 8 PWOK 20 No connection 9 SB_5V 21 5V 10 12V 22 5V 11 12V 23 5V 12 3V3 24 GND Related concepts 2 3 External power on page 2 25 Related references 1 3 Location of components on the V2...

Page 147: ...specifications of the Versatile Express V2M Juno r2 motherboard It contains the following section B 1 Electrical specification on page Appx B 148 ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliates All rights reserved Appx B 147 Non Confidential ...

Page 148: ...supply voltages of 0 8V 0 9V and 1 0V Table B 1 Cortex A72 Cortex A53 and Mali T624 GPU maximum operating frequencies Operating voltage Cortex A72 Cortex A53 Mali T624 GPU 0 8V Underdrive 600MHz 450MHz 450MHz 0 9V Nominal 1GHz 800MHz 600MHz 1 0V Overdrive 1 2GHz 950MHz Not supported B Specifications B 1 Electrical specification ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliate...

Page 149: ... the technical changes between released issues of this book It contains the following section C 1 Revisions on page Appx C 150 ARM 100114_0200_03_en Copyright 2015 2017 ARM Limited or its affiliates All rights reserved Appx C 149 Non Confidential ...

Page 150: ...otherboard Updated list of typical applications in the SOFTWARE directory 3 3 6 Contents of the SOFTWARE directory on page 3 74 V2M Juno r2 motherboard Corrected signal name in reset architecture diagram 2 6 2 Reset architecture on page 2 35 V2M Juno r2 motherboard Table C 3 Differences between issue 0200 01 and issue 0200 02 Change Location Affects Corrected Thin Links operating speeds 2 2 Juno r...

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