ARM Prospector P1100, User Manual, Page: 94 / 154

Programmer’s Reference
4-8 Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A
4.2.4 System control module registers
The system control module registers provide status and control for the operating system
timer, real-time clock, interrupt controller, and power management features of the
SA-1100. This group of registers also provides access to and control of the GPIO pins.
Table 4-4 lists the registers in this group. Detailed descriptions of these registers can be
found in the Intel StrongARM SA-1100 Microprocessor Developer’s Guide.
0x8007 0064
SSP Control Register 1 Bit 0 Receive FIFO Interrupt Enable
Bit 1 Transmit FIFO Interrupt Enable
Bit 2 Loopback Mode
Bit 3 Serial Clock Polarity
Bit 4 Serial Clock Phase
Bit 5 External Clock Select
0x8007 006C
SSP Data Register
0x8007 0074
SSP Status Register Bit 1 Transmit FIFO Not Full
Bit 2 Receive FIFO Not Empty
Bit 3 SSP Busy Flag
Bit 4 Transmit FIFO Service Request
Bit 5 Receive FIFO Service Request
Bit 6 Receive FIFO Overrun
Table 4-3 Peripheral module registers (continued)
Address Register Notes
Table 4-4 System controller module registers
Address Register Notes
OS Timer
0x9000 0000
OS Timer Match Register 0
0x9000 0004
OS Timer Match Register 1
0x9000 0008
OS Timer Match Register 2
0x9000 000C OS Timer Match Register 3
0x9000 0010
OS Timer Counter Register
0x9000 0014
OS Timer Status Register
0x9000 0018
OS Timer Watchdog Enable Register
0x9000 001C
OS Timer Interrupt Enable Register