ARM Prospector P1100, User Manual, Page: 111 / 154

Programmer’s Reference
ARM DUI 0122A Copyright © ARM Limited 2000. All rights reserved. 4-25
• The host responds by asserting PLD_SPI_nCS0 between 0.1ms and 5ms and
supplying the first burst of clock pulses.
• The slave places a sequence of eight data bits onto CPU_SPI_RXD on the
falling edge of CPU_SPI_SCLK.
• The next byte is transferred if KEY_nATN is held LOW, signaling that more
data is available. At least 150µs must be allowed between the start of one byte
transfer and the start of the next.
• After the last byte is transferred, the keyboard controller de-asserts KEY_nATN
to indicate that the transfer is complete. In response, the host de-asserts
PLD_SPI_CS0 to release the SPI bus. A new transfer can begin 120µs after the
de-assertion of KEY_nATN.
4.4.6 Keyboard controller interrupts
The keyboard controller asserts the signal KEY_nATN when any of the Human Input
Device (HID) manager blocks are enabled and detect certain events. The KEY_nATN
signal is used by the system controller PLD to assert the keyboard interrupt which is
connected to the GIO0 pin of the SA-1100.
The interrupt service routine should read a report from the keyboard controller, as
described in Keyboard controller host reads and report transfers on page 4-24.
The HID managers issue the following report types:
Keyboard data reports
These return changes on the internal or external keyboard matrix.
Input may also be from an external keyboard device connected to
J19. Figure 4-5 shows the format of a keyboard data report.
Figure 4-5 Keyboard data report
Header =
0x88
LRC
Key number